FR2344094A1 - Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires - Google Patents
Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoiresInfo
- Publication number
- FR2344094A1 FR2344094A1 FR7606879A FR7606879A FR2344094A1 FR 2344094 A1 FR2344094 A1 FR 2344094A1 FR 7606879 A FR7606879 A FR 7606879A FR 7606879 A FR7606879 A FR 7606879A FR 2344094 A1 FR2344094 A1 FR 2344094A1
- Authority
- FR
- France
- Prior art keywords
- hierarchy
- exchanges
- memories
- management system
- contiguous levels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7606879A FR2344094A1 (fr) | 1976-03-10 | 1976-03-10 | Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires |
US05/776,359 US4173781A (en) | 1976-03-10 | 1977-03-10 | System of coherent management of exchanges between two contiguous levels of a hierarchy of memories |
DE19772710477 DE2710477A1 (de) | 1976-03-10 | 1977-03-10 | Anordnung zur kohaerenten leitung des informationsaustauschs zwischen zwei aneinanderstossenden niveaus einer speicherhierarchie |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7606879A FR2344094A1 (fr) | 1976-03-10 | 1976-03-10 | Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2344094A1 true FR2344094A1 (fr) | 1977-10-07 |
FR2344094B1 FR2344094B1 (fr) | 1978-12-08 |
Family
ID=9170234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7606879A Granted FR2344094A1 (fr) | 1976-03-10 | 1976-03-10 | Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires |
Country Status (3)
Country | Link |
---|---|
US (1) | US4173781A (fr) |
DE (1) | DE2710477A1 (fr) |
FR (1) | FR2344094A1 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0051745A2 (fr) * | 1980-11-10 | 1982-05-19 | International Business Machines Corporation | Hiérarchie de mémoires avec anté-mémoire pour un système de multiprocesseurs |
EP0434250A2 (fr) * | 1989-12-22 | 1991-06-26 | Digital Equipment Corporation | Appareil et procédé de réduction d'interférences dans des antémémoires à deux niveaux |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE16426T1 (de) * | 1979-01-09 | 1985-11-15 | Sullivan Computer | Computer mit speicher fuer mehrere gleichzeitige benutzer. |
US4484262A (en) * | 1979-01-09 | 1984-11-20 | Sullivan Herbert W | Shared memory computer method and apparatus |
JPS5680872A (en) * | 1979-12-06 | 1981-07-02 | Fujitsu Ltd | Buffer memory control system |
US4823259A (en) * | 1984-06-29 | 1989-04-18 | International Business Machines Corporation | High speed buffer store arrangement for quick wide transfer of data |
US4730249A (en) * | 1986-01-16 | 1988-03-08 | International Business Machines Corporation | Method to operate on large segments of data in a virtual memory data processing system |
US4785395A (en) * | 1986-06-27 | 1988-11-15 | Honeywell Bull Inc. | Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement |
US4885680A (en) * | 1986-07-25 | 1989-12-05 | International Business Machines Corporation | Method and apparatus for efficiently handling temporarily cacheable data |
US5034885A (en) * | 1988-03-15 | 1991-07-23 | Kabushiki Kaisha Toshiba | Cache memory device with fast data-write capacity |
US5689679A (en) * | 1993-04-28 | 1997-11-18 | Digital Equipment Corporation | Memory system and method for selective multi-level caching using a cache level code |
US6047357A (en) * | 1995-01-27 | 2000-04-04 | Digital Equipment Corporation | High speed method for maintaining cache coherency in a multi-level, set associative cache hierarchy |
US7281092B2 (en) * | 2005-06-02 | 2007-10-09 | International Business Machines Corporation | System and method of managing cache hierarchies with adaptive mechanisms |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3581291A (en) * | 1968-10-31 | 1971-05-25 | Hitachi Ltd | Memory control system in multiprocessing system |
US3588839A (en) * | 1969-01-15 | 1971-06-28 | Ibm | Hierarchical memory updating system |
US3771137A (en) * | 1971-09-10 | 1973-11-06 | Ibm | Memory control in a multipurpose system utilizing a broadcast |
US3820078A (en) * | 1972-10-05 | 1974-06-25 | Honeywell Inf Systems | Multi-level storage system having a buffer store with variable mapping modes |
US3911401A (en) * | 1973-06-04 | 1975-10-07 | Ibm | Hierarchial memory/storage system for an electronic computer |
US3938097A (en) * | 1974-04-01 | 1976-02-10 | Xerox Corporation | Memory and buffer arrangement for digital computers |
FR2308164A1 (fr) * | 1975-04-17 | 1976-11-12 | Cii | Procede et moyens pour une gestion coherente des informations dans une hierarchie de memoires |
US4077059A (en) * | 1975-12-18 | 1978-02-28 | Cordi Vincent A | Multi-processing system with a hierarchial memory having journaling and copyback |
-
1976
- 1976-03-10 FR FR7606879A patent/FR2344094A1/fr active Granted
-
1977
- 1977-03-10 DE DE19772710477 patent/DE2710477A1/de active Granted
- 1977-03-10 US US05/776,359 patent/US4173781A/en not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0051745A2 (fr) * | 1980-11-10 | 1982-05-19 | International Business Machines Corporation | Hiérarchie de mémoires avec anté-mémoire pour un système de multiprocesseurs |
EP0051745A3 (en) * | 1980-11-10 | 1984-07-18 | International Business Machines Corporation | Cache storage hierarchy for a multiprocessor system |
EP0434250A2 (fr) * | 1989-12-22 | 1991-06-26 | Digital Equipment Corporation | Appareil et procédé de réduction d'interférences dans des antémémoires à deux niveaux |
EP0434250A3 (en) * | 1989-12-22 | 1992-01-08 | Digital Equipment Corporation | Apparatus and method for reducing interference in two-level cache memories |
US5136700A (en) * | 1989-12-22 | 1992-08-04 | Digital Equipment Corporation | Apparatus and method for reducing interference in two-level cache memories |
Also Published As
Publication number | Publication date |
---|---|
US4173781A (en) | 1979-11-06 |
FR2344094B1 (fr) | 1978-12-08 |
DE2710477C2 (fr) | 1988-12-01 |
DE2710477A1 (de) | 1977-09-15 |
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