EP1062651B1 - Procede d'affichage de donnees sur afficheur matriciel avec ordre de balayage alterne en groupes adjacentes de colomnes - Google Patents
Procede d'affichage de donnees sur afficheur matriciel avec ordre de balayage alterne en groupes adjacentes de colomnes Download PDFInfo
- Publication number
- EP1062651B1 EP1062651B1 EP99907671A EP99907671A EP1062651B1 EP 1062651 B1 EP1062651 B1 EP 1062651B1 EP 99907671 A EP99907671 A EP 99907671A EP 99907671 A EP99907671 A EP 99907671A EP 1062651 B1 EP1062651 B1 EP 1062651B1
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- European Patent Office
- Prior art keywords
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0283—Arrangement of drivers for different directions of scanning
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Definitions
- the present invention relates to a method for displaying data on a matrix display, more particularly a matrix display constituted by N data lines and M selection lines at the intersections of which are located image points or pixels, in which the N lines of data are grouped in P blocks of N 'lines of data each.
- liquid crystal screens used in direct vision or projection. These screens are, in general, composed of a first substrate comprising selection lines, referenced below lines, and data lines, referenced below columns, at the intersections of which the image points are located and of a second substrate comprising a counter electrode, the liquid crystals being inserted between the two substrates.
- the image points consist in particular of pixel electrodes connected through switching circuits, such as transistors, to the selection lines and to the data lines.
- the selection lines and the data lines are respectively connected to peripheral control circuits generally called "drivers" (in English).
- the line drivers scan the lines one after the other and close the switching circuits, that is to say pass the transistors of each line.
- the column drivers apply information to each line of data, namely, charge the electrodes of the selected pixels and modify the optical properties of the liquid crystal included between these electrodes and the counter-electrode, thus allowing the formation of images on the screen.
- each column is connected by its own connection line to the screen column drivers.
- the principle of multiplexing is used between the outputs of the driver-columns and the columns of the screen so as to reduce the number of tracks at the input of the cell.
- each block consists of transistors 3, one of the electrodes of which is connected to a column and the other electrode of which is connected to the same electrode of the other transistors of the block, all of these electrodes being connected to a video input referenced DB1 for the first block, DB2 for the second block, DBP for the last block.
- the gates of the transistors 3 each receive a demultiplexing signal DW1, DW2, DW3 ... DW9.
- Each block has the same structure.
- FIG. 2 The timing diagrams of the voltages recorded on the successive columns of the same block 1 receiving a video signal DB1 to DBP are shown in FIG. 2. It was assumed for the plotting of these timing diagrams, that the DC and AC voltage errors introduced by the column - line - column coupling (referenced 2 in FIGURE 1), the origin of which was described in French patent n ° 96 00259 filed on January 11, 1996, are perfectly corrected by the compensation circuit presented in this same patent .
- Each chronogram represents a time-line of a given column (1 to 9) of a block connected for example to DB1.
- the decomposition of the signals can be done as follows: 1. Preload of all columns of the matrix 4 ⁇ s 2. Stabilization of the preload 0,5 ⁇ s 3. Sampling of the video on the 9 columns of the DB block 9 x 2 ⁇ s 4. Equalization between column and pixel 7,5 ⁇ s 5. Deselection of the line 2 .mu.s.
- the object of the present invention is to propose a method for displaying data on a matrix display which overcomes this drawback.
- the scanning of 1 at N 'then from N' to 1, every other selection line is made.
- scanning from 1 to N 'then from N' to 1 is performed on 4 successive selection lines, the scanning being carried out in a first direction during 2 successive selection lines and in a second direction during the 2 other following selection lines.
- the process according to the present invention mainly applies to a matrix display of the type of that shown in FIGURE 1.
- This display consists of N rows of data or columns and M rows of selection in intersections of which the image points or pixels are not represented.
- the N columns are grouped into P blocks 1 of N ′ columns each.
- P blocks 1 of N ′ columns each For example, in FIGURE 1, a block of 9 columns is shown.
- the column control circuit will include 80 blocks of 9 adjacent columns and will operate with frequency approximately 500 kHz sampling rate.
- each block 1 receives in parallel one of the P or 80 data signals which is demultiplexed by signals DW1 to DW9 on the N 'or 9 columns of a block.
- each block 1 is successively scanned from line C1 to C9 in applying sampling pulses DW1 to DW9, and one obtains on each column C1 to C9, signals as shown in FIGURE 2. Then for the next line L2, each block is scanned starting from column C9 to the column C1 by applying sampling pulses from DW9 to DW1 from so as to reduce the DC error as explained in the introduction with reference to FIGURE 2.
- the inversion of the scanning is carried out by reversing the arrival of the sampling pulses each two lines among four lines according to the following table: line frame 1 frame 2 frame 3 1 DW 1 to 9 DW 1 to 9 DW 1 to 9 2 DW 1 to 9 DW 1 to 9 DW 1 to 9 3 DW 9 to 1 DW 9 to 1 DW 9 to 1 4 DW 9 to 1 DW 9 to 1 DW 9 to 1 5 DW 1 to 9 DW 1 to 9 DW 1 to 9 6 DW 1 to 9 DW 1 to 9 DW 1 to 9 DW 1 to 9 DW 1 to 9
- the present invention also relates to a circuit making it possible to set up this process.
- This circuit consists of at least one logic circuit programmable associated with a line counter determining the reversal of the direction of scanning.
- the signal referenced Preset at the output of the line counter 11 controlled by the CL line clock is sent respectively on a modulo N '15 counter and on a DW 16 counter.
- the modulo N' counter 15 is controlled by the data clock CD and operates in such a way that:
- the DW 16 counter is controlled by the DW clock CDW and works as follows:
- This information at the output of the DW counter is sent on a circuit level 17 and returned to the modulo counter N '15.
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Description
Dans le cas d'écran de définition importante, le principe du multiplexage est utilisé entre les sorties du driver-colonnes et les colonnes de l'écran de manière à réduire le nombre de pistes en entrée de la cellule. Ainsi, dans la demande de brevet française n° 96 00259 déposée le 11 janvier 1996 au nom de la demanderesse, on a décrit un circuit de commande-colonnes d'un afficheur matriciel tel que représenté sur la FIGURE 1. Dans ce cas, les colonnes sont regroupées en P blocs 1 de N' colonnes, à savoir 9 colonnes C1, C2, C3... C9 dans le mode de réalisation représenté. Chaque bloc est constitué de transistors 3 dont une des électrodes est reliée à une colonne et dont l'autre électrode est connectée à la même électrode des autres transistors du bloc, l'ensemble de ces électrodes étant connecté à une entrée vidéo référencée DB1 pour le premier bloc, DB2 pour le second bloc, DBP pour le dernier bloc. Les grilles des transistors 3 reçoivent chacune un signal de demultiplexage DW1, DW2, DW3... DW9. Chaque bloc présente la même structure.
1. Précharge de toutes les colonnes de la matrice | 4µs |
2. Stabilisation de la précharge | 0,5µs |
3. Echantillonnage de la vidéo sur les 9 colonnes du bloc DB | 9 x 2µs |
4. Egalisation entre colonne et pixel | 7,5µs |
5. Désélection de la ligne | 2µs. |
D'autres caractéristiques et avantages de la présente invention apparaítront à la lecture de la description faite ci-après, cette description étant faite avec référence aux dessins ci-annexés dans lesquels :
- La FIGURE 1 déjà décrite est une représentation schématique d'un afficheur matriciel dans lequel les colonnes sont regroupées par blocs, qui sera utilisé pour la mise en oeuvre de la présente invention.
- La FIGURE 2, déjà décrite, représente les chronogrammes, sur un temps-ligne, des colonnes impaires d'un bloc DB constitué de 9 colonnes, et
- La FIGURE 3 est une représentation schématique d'un circuit utilisé pour mettre en oeuvre la présente invention..
ligne | trame 1 | trame 2 | trame 3 |
1 | DW 1 à 9 | DW 1 à 9 | DW 1 à 9 |
2 | DW 1 à 9 | DW 1 à 9 | DW 1 à 9 |
3 | DW 9 à 1 | DW 9 à 1 | DW 9 à 1 |
4 | DW 9 à 1 | DW 9 à 1 | DW 9 à 1 |
5 | DW 1 à 9 | DW 1 à 9 | DW 1 à 9 |
6 | DW 1 à 9 | DW 1 à 9 | DW 1 à 9 |
- si le bit de poids 2 en sortie du compteur-lignes (11) vaut 0 (xxxxxx00
ou xxxxxx01), les mots DWj' sont lus de 1 à N' et les P données vidéos, stockées
dans la mémoire ligne 13, sont transférées à un circuit de commande D/A 14, à
savoir un convertisseur numérique/analogique en amont de la cellule suivant l'ordre
des DWs selon le tableau ci-dessous :
DW DB numéro de colonne 1 k
avec k entier et 1 ≤ k ≤ PN'x(k-1)+1
avec k entier et 1 ≤ k ≤ P2 k
avec k entier et 1 ≤ k ≤ PN'x(k-1)+2
avec k entier et 1 ≤ k ≤ PN' k
avec k entier et 1 ≤ k ≤ PN' x (k-1) + N'
avec k entier et 1 ≤ k ≤ P - sinon les mots DWj sont lus de N' à 1 et les P données vidéo sont
transférées au circuit de commande D/A 14 selon l'ordre indiqué dans le tableau qui
suit:
DW DB numéro de colonne N' k
avec k entier et 1 ≤ k ≤ PN'x(k-1)+N'
avec k entier et 1 ≤ k ≤ P2 k
avec k entier et 1 ≤ k ≤ PN'x (k-1) + 2
avec k entier et 1 ≤ k ≤ P1 k
avec k entier et 1 ≤ k ≤ PN'x(k-1)+1
avec k entier et 1 ≤ k ≤ P
Claims (4)
- Procédé d'affichage de données sur un afficheur matriciel constitué par N lignes de données et M lignes de sélection aux intersections desquelles sont situés les points-images ou pixels, dans lequel les N lignes de données sont regroupées en P blocs de N' lignes de données chacun (N = P x N'), chaque bloc recevant en parallèle un des P signaux de données qui est démultiplexé sur les N' lignes dudit bloc, caractérisé en ce que, alternativement selon les lignes de sélection, le balayage des N' lignes de données d'un bloc est réalisé soit de 1 à N' soit de N' à 1.
- Procédé selon la revendication. 1, caractérisé en ce que le balayage de 1 à N' puis de N' à 1 est réalisé une ligne de sélection sur deux.
- Procédé selon la revendication 1, caractérisé en ce que le balayage de 1 à N' puis de N' à 1 est réalisé sur quatre lignes de sélection successives, le balayage étant réalisé dans un premier sens pendant deux lignes de sélection successives et dans un second sens pendant les deux autres lignes de sélection suivantes.
- Circuit pour la mise en oeuvre du procédé selon l'une quelconque des revendications 1 à 3, caractérisé en ce qu'il est constitué par au moins un circuit logique programmable associé à un compteur ligne déterminant l'inversion du sens de balayage.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9802919 | 1998-03-10 | ||
FR9802919A FR2776107A1 (fr) | 1998-03-10 | 1998-03-10 | Procede d'affichage de donnees sur un afficheur matriciel |
PCT/FR1999/000524 WO1999046753A1 (fr) | 1998-03-10 | 1999-03-09 | Procede d'affichage de donnees sur afficheur matriciel avec ordre de balayage alterne en groupes adjacents de colonnes |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1062651A1 EP1062651A1 (fr) | 2000-12-27 |
EP1062651B1 true EP1062651B1 (fr) | 2002-07-03 |
Family
ID=9523867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP99907671A Expired - Lifetime EP1062651B1 (fr) | 1998-03-10 | 1999-03-09 | Procede d'affichage de donnees sur afficheur matriciel avec ordre de balayage alterne en groupes adjacentes de colomnes |
Country Status (7)
Country | Link |
---|---|
US (1) | US6924785B1 (fr) |
EP (1) | EP1062651B1 (fr) |
JP (1) | JP4727038B2 (fr) |
KR (1) | KR100587433B1 (fr) |
DE (1) | DE69902015T2 (fr) |
FR (1) | FR2776107A1 (fr) |
WO (1) | WO1999046753A1 (fr) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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TW540020B (en) * | 2001-06-06 | 2003-07-01 | Semiconductor Energy Lab | Image display device and driving method thereof |
JP2004037498A (ja) * | 2002-06-28 | 2004-02-05 | Seiko Epson Corp | 電気光学装置の駆動回路、電気光学装置、電子機器及び電気光学装置の駆動方法 |
JP2004145300A (ja) * | 2002-10-03 | 2004-05-20 | Seiko Epson Corp | 電子回路、電子回路の駆動方法、電子装置、電気光学装置、電気光学装置の駆動方法及び電子機器 |
JP2006072385A (ja) * | 2002-10-03 | 2006-03-16 | Seiko Epson Corp | 電子装置及び電子機器 |
FR2873227B1 (fr) * | 2004-07-13 | 2006-09-15 | Thales Sa | Afficheur matriciel |
FR2889763B1 (fr) * | 2005-08-12 | 2007-09-21 | Thales Sa | Afficheur matriciel a affichage sequentiel des couleurs et procede d'adressage |
US8184974B2 (en) | 2006-09-11 | 2012-05-22 | Lumexis Corporation | Fiber-to-the-seat (FTTS) fiber distribution system |
FR2913818B1 (fr) * | 2007-03-16 | 2009-04-17 | Thales Sa | Matrice active d'un ecran electroluminescent organique |
TWI334126B (en) * | 2007-07-17 | 2010-12-01 | Au Optronics Corp | Voltage adjusting circuit, method, and display apparatus having the same |
FR2934919B1 (fr) * | 2008-08-08 | 2012-08-17 | Thales Sa | Registre a decalage a transistors a effet de champ. |
ES2715850T3 (es) | 2009-08-06 | 2019-06-06 | Global Eagle Entertainment Inc | Sistema de entretenimiento en vuelo de interconexión en red en serie de fibra hasta el asiento |
US8424045B2 (en) | 2009-08-14 | 2013-04-16 | Lumexis Corporation | Video display unit docking assembly for fiber-to-the-screen inflight entertainment system |
WO2011022708A1 (fr) | 2009-08-20 | 2011-02-24 | Lumexis Corp. | Configuration de réseau de système de divertissement en vol à fibres optiques à mise en réseau série |
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JPS5692573A (en) * | 1979-12-26 | 1981-07-27 | Citizen Watch Co Ltd | Display panel |
FR2573899B1 (fr) | 1984-11-28 | 1986-12-26 | France Etat | Circuit electronique forme de transistors en couches minces pour commander un dispositif matriciel |
JPS61223791A (ja) * | 1985-03-29 | 1986-10-04 | 松下電器産業株式会社 | アクテイブマトリツクス基板 |
DE3630779C1 (en) * | 1986-09-10 | 1992-12-10 | Ant Nachrichtentech | Secret transmission of video signals e.g. for pay TV - sending image in permutated series by placing lines in meandering form e.g. first line scanning left to right second right to left etc. |
JPS63261326A (ja) * | 1987-04-20 | 1988-10-28 | Seiko Instr & Electronics Ltd | 電気光学装置の駆動回路 |
JPH01143024A (ja) * | 1987-11-30 | 1989-06-05 | Sony Corp | 光情報処理装置 |
JPH05143024A (ja) * | 1991-11-22 | 1993-06-11 | Matsushita Electric Ind Co Ltd | マトリクス型画像表示装置の駆動方法及び駆動回路 |
FR2693005B1 (fr) | 1992-06-26 | 1995-03-31 | Thomson Lcd | Disposition d'encapsulation et de passivation de circuit pour écrans plats. |
US5426447A (en) * | 1992-11-04 | 1995-06-20 | Yuen Foong Yu H.K. Co., Ltd. | Data driving circuit for LCD display |
JP3329008B2 (ja) * | 1993-06-25 | 2002-09-30 | ソニー株式会社 | 双方向信号伝送回路網及び双方向信号転送シフトレジスタ |
JP2646974B2 (ja) * | 1993-11-11 | 1997-08-27 | 日本電気株式会社 | 走査回路およびその駆動方法 |
JP3590648B2 (ja) * | 1994-03-23 | 2004-11-17 | 株式会社日立国際電気 | 原画像データの圧縮処理の方法及び原画像データの伸張処理の方法 |
JPH0850465A (ja) * | 1994-05-30 | 1996-02-20 | Sanyo Electric Co Ltd | シフトレジスタ及び表示装置の駆動回路 |
JPH0830242A (ja) * | 1994-07-13 | 1996-02-02 | Casio Comput Co Ltd | 液晶駆動装置 |
JPH08106272A (ja) * | 1994-10-03 | 1996-04-23 | Semiconductor Energy Lab Co Ltd | 表示装置駆動回路 |
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JPH08234169A (ja) * | 1994-10-20 | 1996-09-13 | Canon Inc | 表示制御装置、及び表示制御方法 |
JP3487660B2 (ja) * | 1994-12-26 | 2004-01-19 | 株式会社日立製作所 | 液晶表示装置 |
JP3454971B2 (ja) * | 1995-04-27 | 2003-10-06 | 株式会社半導体エネルギー研究所 | 画像表示装置 |
JP3639969B2 (ja) * | 1995-08-03 | 2005-04-20 | カシオ計算機株式会社 | 表示装置 |
FR2743658B1 (fr) | 1996-01-11 | 1998-02-13 | Thomson Lcd | Procede d'adressage d'un ecran plat utilisant une precharge des pixels circuit de commande permettant la mise en oeuvre du procede et son application aux ecrans de grandes dimensions |
FR2743662B1 (fr) | 1996-01-11 | 1998-02-13 | Thomson Lcd | Perfectionnement aux registres a decalage utilisant des transistors mis de meme polarite |
KR100214484B1 (ko) * | 1996-06-07 | 1999-08-02 | 구본준 | 순차 및 이중스캐닝방식을 위한 티에프티-엘씨디구동회로 |
JP2980042B2 (ja) * | 1996-11-27 | 1999-11-22 | 日本電気株式会社 | 走査回路 |
JP3077650B2 (ja) * | 1997-10-27 | 2000-08-14 | 日本ビクター株式会社 | アクティブマトリクス方式液晶パネルの駆動装置 |
-
1998
- 1998-03-10 FR FR9802919A patent/FR2776107A1/fr active Pending
-
1999
- 1999-03-09 JP JP2000536058A patent/JP4727038B2/ja not_active Expired - Lifetime
- 1999-03-09 US US09/623,407 patent/US6924785B1/en not_active Expired - Lifetime
- 1999-03-09 DE DE69902015T patent/DE69902015T2/de not_active Expired - Fee Related
- 1999-03-09 EP EP99907671A patent/EP1062651B1/fr not_active Expired - Lifetime
- 1999-03-09 KR KR1020007009888A patent/KR100587433B1/ko not_active IP Right Cessation
- 1999-03-09 WO PCT/FR1999/000524 patent/WO1999046753A1/fr active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR20010041675A (ko) | 2001-05-25 |
JP2002507007A (ja) | 2002-03-05 |
DE69902015T2 (de) | 2003-03-06 |
KR100587433B1 (ko) | 2006-06-09 |
DE69902015D1 (de) | 2002-08-08 |
JP4727038B2 (ja) | 2011-07-20 |
WO1999046753A1 (fr) | 1999-09-16 |
FR2776107A1 (fr) | 1999-09-17 |
EP1062651A1 (fr) | 2000-12-27 |
US6924785B1 (en) | 2005-08-02 |
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