DE69928050D1 - Taktregenerator - Google Patents
TaktregeneratorInfo
- Publication number
- DE69928050D1 DE69928050D1 DE69928050T DE69928050T DE69928050D1 DE 69928050 D1 DE69928050 D1 DE 69928050D1 DE 69928050 T DE69928050 T DE 69928050T DE 69928050 T DE69928050 T DE 69928050T DE 69928050 D1 DE69928050 D1 DE 69928050D1
- Authority
- DE
- Germany
- Prior art keywords
- clock regenerator
- regenerator
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
- H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22778098 | 1998-08-12 | ||
JP10227780A JP2000059213A (ja) | 1998-08-12 | 1998-08-12 | クロック再生装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69928050D1 true DE69928050D1 (de) | 2005-12-08 |
DE69928050T2 DE69928050T2 (de) | 2006-07-27 |
Family
ID=16866275
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69928050T Expired - Fee Related DE69928050T2 (de) | 1998-08-12 | 1999-08-11 | Taktregenerator |
Country Status (5)
Country | Link |
---|---|
US (1) | US6442703B1 (de) |
EP (1) | EP0980163B1 (de) |
JP (1) | JP2000059213A (de) |
KR (1) | KR100346674B1 (de) |
DE (1) | DE69928050T2 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3727206B2 (ja) * | 1999-11-11 | 2005-12-14 | Necエレクトロニクス株式会社 | クロック乗換回路及びその方法 |
JP4454798B2 (ja) * | 2000-06-09 | 2010-04-21 | Necエレクトロニクス株式会社 | クロック再生装置 |
JP4504580B2 (ja) * | 2001-02-20 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | 逓倍pll回路 |
US6806755B1 (en) * | 2001-04-23 | 2004-10-19 | Quantum 3D | Technique for glitchless switching of asynchronous clocks |
JP4545985B2 (ja) * | 2001-05-17 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | ロック検出回路および位相同期ループ回路 |
US7099424B1 (en) * | 2001-08-28 | 2006-08-29 | Rambus Inc. | Clock data recovery with selectable phase control |
US6582082B2 (en) * | 2001-11-13 | 2003-06-24 | Prokia Technology Co., Ltd | Projection system including a compact optical engine having enhanced heat dissipating efficiency |
US6868509B2 (en) * | 2001-12-07 | 2005-03-15 | Invensys Systems, Inc. | Method and apparatus for network fault correction via adaptive fault router |
JP5446425B2 (ja) * | 2009-04-23 | 2014-03-19 | 住友電気工業株式会社 | クロック・データ再生回路及び局側装置 |
US8811555B2 (en) * | 2010-02-04 | 2014-08-19 | Altera Corporation | Clock and data recovery circuitry with auto-speed negotiation and other possible features |
JP5711949B2 (ja) * | 2010-12-03 | 2015-05-07 | ローム株式会社 | シリアルデータの受信回路、受信方法およびそれらを用いたシリアルデータの伝送システム、伝送方法 |
JPWO2012143970A1 (ja) * | 2011-04-19 | 2014-07-28 | 三菱電機株式会社 | 周波数シンセサイザ |
CN103684440B (zh) * | 2012-09-04 | 2017-10-27 | 瑞昱半导体股份有限公司 | 时脉与数据回复电路以及时脉与数据回复方法 |
KR102151184B1 (ko) | 2013-07-24 | 2020-09-02 | 삼성전자주식회사 | 클록 데이터 복원 회로 및 이를 포함하는 타이밍 컨트롤러 그리고 이의 구동 방법 |
JP6585000B2 (ja) | 2016-05-09 | 2019-10-02 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4069462A (en) * | 1976-12-13 | 1978-01-17 | Data General Corporation | Phase-locked loops |
US4415984A (en) * | 1980-06-25 | 1983-11-15 | Burroughs Corporation | Synchronous clock regenerator for binary serial data signals |
JPS63249976A (ja) | 1987-04-07 | 1988-10-17 | Matsushita Electric Ind Co Ltd | クロツク抽出回路 |
JP2532716B2 (ja) | 1990-04-16 | 1996-09-11 | 松下電器産業株式会社 | 位相ずれ判定装置 |
JPH04215338A (ja) | 1990-12-13 | 1992-08-06 | Matsushita Electric Ind Co Ltd | Pll回路 |
JPH06112817A (ja) * | 1992-09-25 | 1994-04-22 | Fujitsu Ltd | Pll 周波数シンセサイザ回路 |
AUPM972594A0 (en) * | 1994-11-28 | 1994-12-22 | Curtin University Of Technology | Steered frequency phase locked loop |
JPH0993090A (ja) | 1995-09-21 | 1997-04-04 | Pioneer Electron Corp | 受信機 |
US5623649A (en) * | 1995-10-31 | 1997-04-22 | Texas Instruments Incorporated | Method and apparatus for passing a bus clock signal from a computer to an expansion chassis |
US5786733A (en) * | 1995-12-04 | 1998-07-28 | Nec Corporation | Phase-locked oscillating circuit with a frequency fluctuation detecting circuit |
US5692166A (en) * | 1996-04-19 | 1997-11-25 | Motorola, Inc. | Method and system for resynchronizing a phase-shifted received data stream with a master clock |
JPH10163864A (ja) | 1996-12-02 | 1998-06-19 | Hitachi Ltd | 位相同期ループ制御方式 |
JP4144913B2 (ja) * | 1997-01-20 | 2008-09-03 | 富士通株式会社 | 半導体装置 |
US6108793A (en) * | 1997-07-18 | 2000-08-22 | Fujitsu Limited | Semiconductor device having timing-stabilization circuit and method of testing such semiconductor device |
JPH1141222A (ja) | 1997-07-23 | 1999-02-12 | Hitachi Ltd | 非同期データ復調回路 |
-
1998
- 1998-08-12 JP JP10227780A patent/JP2000059213A/ja active Pending
-
1999
- 1999-08-11 EP EP99115838A patent/EP0980163B1/de not_active Expired - Lifetime
- 1999-08-11 DE DE69928050T patent/DE69928050T2/de not_active Expired - Fee Related
- 1999-08-12 US US09/373,531 patent/US6442703B1/en not_active Expired - Fee Related
- 1999-08-12 KR KR1019990033074A patent/KR100346674B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20000017276A (ko) | 2000-03-25 |
EP0980163A3 (de) | 2002-05-22 |
JP2000059213A (ja) | 2000-02-25 |
EP0980163B1 (de) | 2005-11-02 |
KR100346674B1 (ko) | 2002-07-27 |
US6442703B1 (en) | 2002-08-27 |
EP0980163A2 (de) | 2000-02-16 |
DE69928050T2 (de) | 2006-07-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |