DE69532006D1 - Speichersteuerverfahren und Vorrichtung geeignet für ein Informationsverarbeitungssystem - Google Patents
Speichersteuerverfahren und Vorrichtung geeignet für ein InformationsverarbeitungssystemInfo
- Publication number
- DE69532006D1 DE69532006D1 DE69532006T DE69532006T DE69532006D1 DE 69532006 D1 DE69532006 D1 DE 69532006D1 DE 69532006 T DE69532006 T DE 69532006T DE 69532006 T DE69532006 T DE 69532006T DE 69532006 D1 DE69532006 D1 DE 69532006D1
- Authority
- DE
- Germany
- Prior art keywords
- information processing
- processing system
- control method
- memory control
- apparatus suitable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010365 information processing Effects 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/0822—Copy directories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
- G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Multi Processors (AREA)
- Storage Device Security (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11990494A JP3360933B2 (ja) | 1994-06-01 | 1994-06-01 | 情報処理システムにおける記憶制御方法および記憶制御装置 |
JP11990494 | 1994-06-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69532006D1 true DE69532006D1 (de) | 2003-11-27 |
DE69532006T2 DE69532006T2 (de) | 2004-05-19 |
Family
ID=14773096
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69532006T Expired - Lifetime DE69532006T2 (de) | 1994-06-01 | 1995-04-07 | Speichersteuerverfahren und Vorrichtung geeignet für ein Informationsverarbeitungssystem |
DE69518473T Expired - Lifetime DE69518473T2 (de) | 1994-06-01 | 1995-04-07 | Speichersteuerverfahren und -vorrichtung, geeignet für ein Informationsverarbeitungssystem mit einem Cachespeicher |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69518473T Expired - Lifetime DE69518473T2 (de) | 1994-06-01 | 1995-04-07 | Speichersteuerverfahren und -vorrichtung, geeignet für ein Informationsverarbeitungssystem mit einem Cachespeicher |
Country Status (4)
Country | Link |
---|---|
US (1) | US5829039A (de) |
EP (2) | EP0903669B1 (de) |
JP (1) | JP3360933B2 (de) |
DE (2) | DE69532006T2 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6263408B1 (en) * | 1999-03-31 | 2001-07-17 | International Business Machines Corporation | Method and apparatus for implementing automatic cache variable update |
US20050021947A1 (en) * | 2003-06-05 | 2005-01-27 | International Business Machines Corporation | Method, system and program product for limiting insertion of content between computer programs |
US9727468B2 (en) | 2004-09-09 | 2017-08-08 | Intel Corporation | Resolving multi-core shared cache access conflicts |
US7814166B2 (en) | 2006-01-27 | 2010-10-12 | Sony Computer Entertainment Inc. | Methods and apparatus for virtualizing an address space |
US8510596B1 (en) | 2006-02-09 | 2013-08-13 | Virsec Systems, Inc. | System and methods for run time detection and correction of memory corruption |
WO2007096980A1 (ja) | 2006-02-24 | 2007-08-30 | Fujitsu Limited | 記録制御装置および記録制御方法 |
JP4373485B2 (ja) | 2006-02-28 | 2009-11-25 | 富士通株式会社 | 情報処理装置及び該制御方法 |
US8904189B1 (en) | 2010-07-15 | 2014-12-02 | The Research Foundation For The State University Of New York | System and method for validating program execution at run-time using control flow signatures |
WO2015038944A1 (en) | 2013-09-12 | 2015-03-19 | Virsec Systems, Inc. | Automated runtime detection of malware |
US10354074B2 (en) | 2014-06-24 | 2019-07-16 | Virsec Systems, Inc. | System and methods for automated detection of input and output validation and resource management vulnerability |
EP3161638A1 (de) | 2014-06-24 | 2017-05-03 | Virsec Systems, Inc. | Automatisierte grundursachenanalyse einzelner oder n-gestufter anwendungen |
CA3027728A1 (en) | 2016-06-16 | 2017-12-21 | Virsec Systems, Inc. | Systems and methods for remediating memory corruption in a computer application |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4503497A (en) * | 1982-05-27 | 1985-03-05 | International Business Machines Corporation | System for independent cache-to-cache transfer |
DE3686660T2 (de) * | 1985-02-05 | 1993-04-15 | Digital Equipment Corp | Vorrichtung und verfahren zur zugriffsteuerung in einer mehrcachespeicherdatenverarbeitungsanordnung. |
US4949239A (en) * | 1987-05-01 | 1990-08-14 | Digital Equipment Corporation | System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system |
CA1325289C (en) * | 1989-02-03 | 1993-12-14 | Digital Equipment Corporation | Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor computer system |
US5297269A (en) * | 1990-04-26 | 1994-03-22 | Digital Equipment Company | Cache coherency protocol for multi processor computer system |
US5265232A (en) * | 1991-04-03 | 1993-11-23 | International Business Machines Corporation | Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data |
US5428761A (en) * | 1992-03-12 | 1995-06-27 | Digital Equipment Corporation | System for achieving atomic non-sequential multi-word operations in shared memory |
DE69323790T2 (de) * | 1992-04-29 | 1999-10-07 | Sun Microsystems, Inc. | Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem |
US5398325A (en) * | 1992-05-07 | 1995-03-14 | Sun Microsystems, Inc. | Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems |
US5434993A (en) * | 1992-11-09 | 1995-07-18 | Sun Microsystems, Inc. | Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories |
-
1994
- 1994-06-01 JP JP11990494A patent/JP3360933B2/ja not_active Expired - Lifetime
-
1995
- 1995-04-07 DE DE69532006T patent/DE69532006T2/de not_active Expired - Lifetime
- 1995-04-07 EP EP98122596A patent/EP0903669B1/de not_active Expired - Lifetime
- 1995-04-07 DE DE69518473T patent/DE69518473T2/de not_active Expired - Lifetime
- 1995-04-07 EP EP95302328A patent/EP0690383B1/de not_active Expired - Lifetime
-
1997
- 1997-06-05 US US08/869,740 patent/US5829039A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69532006T2 (de) | 2004-05-19 |
EP0690383B1 (de) | 2000-08-23 |
DE69518473D1 (de) | 2000-09-28 |
EP0690383A3 (de) | 1996-06-05 |
JP3360933B2 (ja) | 2003-01-07 |
EP0903669A2 (de) | 1999-03-24 |
US5829039A (en) | 1998-10-27 |
EP0690383A2 (de) | 1996-01-03 |
JPH07325760A (ja) | 1995-12-12 |
EP0903669A3 (de) | 1999-07-28 |
DE69518473T2 (de) | 2001-01-04 |
EP0903669B1 (de) | 2003-10-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE |