DE602005006791D1 - Halbleiterspeicher und sein Seitenpufferspeicher mit verbessertem Layout - Google Patents

Halbleiterspeicher und sein Seitenpufferspeicher mit verbessertem Layout

Info

Publication number
DE602005006791D1
DE602005006791D1 DE602005006791T DE602005006791T DE602005006791D1 DE 602005006791 D1 DE602005006791 D1 DE 602005006791D1 DE 602005006791 T DE602005006791 T DE 602005006791T DE 602005006791 T DE602005006791 T DE 602005006791T DE 602005006791 D1 DE602005006791 D1 DE 602005006791D1
Authority
DE
Germany
Prior art keywords
page buffer
memory
improved layout
semiconductor memory
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005006791T
Other languages
English (en)
Inventor
Luca Crippa
Rino Micheloni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
SK Hynix Inc
Original Assignee
STMicroelectronics SRL
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, Hynix Semiconductor Inc filed Critical STMicroelectronics SRL
Publication of DE602005006791D1 publication Critical patent/DE602005006791D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564Miscellaneous aspects
    • G11C2211/5642Multilevel memory with buffers, latches, registers at input or output

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
DE602005006791T 2005-07-28 2005-07-28 Halbleiterspeicher und sein Seitenpufferspeicher mit verbessertem Layout Active DE602005006791D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP05106973A EP1748443B1 (de) 2005-07-28 2005-07-28 Halbleiterspeicher und sein Seitenpufferspeicher mit verbessertem Layout

Publications (1)

Publication Number Publication Date
DE602005006791D1 true DE602005006791D1 (de) 2008-06-26

Family

ID=35520515

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005006791T Active DE602005006791D1 (de) 2005-07-28 2005-07-28 Halbleiterspeicher und sein Seitenpufferspeicher mit verbessertem Layout

Country Status (3)

Country Link
US (1) US7408819B2 (de)
EP (1) EP1748443B1 (de)
DE (1) DE602005006791D1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1748443B1 (de) * 2005-07-28 2008-05-14 STMicroelectronics S.r.l. Halbleiterspeicher und sein Seitenpufferspeicher mit verbessertem Layout
TWI594246B (zh) * 2016-05-24 2017-08-01 旺宏電子股份有限公司 記憶體元件及其製作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5683891A (en) * 1979-12-13 1981-07-08 Fujitsu Ltd Semiconductor storage device
KR0140179B1 (ko) * 1994-12-19 1998-07-15 김광호 불휘발성 반도체 메모리
JP4250325B2 (ja) * 2000-11-01 2009-04-08 株式会社東芝 半導体記憶装置
US6377507B1 (en) * 2001-04-06 2002-04-23 Integrated Memory Technologies, Inc. Non-volatile memory device having high speed page mode operation
KR100387529B1 (ko) * 2001-06-11 2003-06-18 삼성전자주식회사 랜덤 억세스 가능한 메모리 셀 어레이를 갖는 불휘발성반도체 메모리 장치
US7042770B2 (en) * 2001-07-23 2006-05-09 Samsung Electronics Co., Ltd. Memory devices with page buffer having dual registers and method of using the same
KR100512178B1 (ko) * 2003-05-28 2005-09-02 삼성전자주식회사 플렉서블한 열 리던던시 스킴을 갖는 반도체 메모리 장치
EP1748443B1 (de) * 2005-07-28 2008-05-14 STMicroelectronics S.r.l. Halbleiterspeicher und sein Seitenpufferspeicher mit verbessertem Layout

Also Published As

Publication number Publication date
US7408819B2 (en) 2008-08-05
EP1748443A1 (de) 2007-01-31
US20070025148A1 (en) 2007-02-01
EP1748443B1 (de) 2008-05-14

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Representative=s name: KLUNKER, SCHMITT-NILSON, HIRSCH, 80797 MUENCHEN

8364 No opposition during term of opposition