DE3071782D1 - Buffer memory control system - Google Patents
Buffer memory control systemInfo
- Publication number
- DE3071782D1 DE3071782D1 DE8080304397T DE3071782T DE3071782D1 DE 3071782 D1 DE3071782 D1 DE 3071782D1 DE 8080304397 T DE8080304397 T DE 8080304397T DE 3071782 T DE3071782 T DE 3071782T DE 3071782 D1 DE3071782 D1 DE 3071782D1
- Authority
- DE
- Germany
- Prior art keywords
- control system
- buffer memory
- memory control
- buffer
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15841779A JPS5680872A (en) | 1979-12-06 | 1979-12-06 | Buffer memory control system |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3071782D1 true DE3071782D1 (en) | 1986-10-30 |
Family
ID=15671290
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8080304397T Expired DE3071782D1 (en) | 1979-12-06 | 1980-12-05 | Buffer memory control system |
Country Status (8)
Country | Link |
---|---|
US (1) | US4395763A (de) |
EP (1) | EP0030463B1 (de) |
JP (1) | JPS5680872A (de) |
AU (1) | AU535788B2 (de) |
BR (1) | BR8007988A (de) |
CA (1) | CA1149965A (de) |
DE (1) | DE3071782D1 (de) |
ES (1) | ES8201343A1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4533995A (en) * | 1981-08-03 | 1985-08-06 | International Business Machines Corporation | Method and system for handling sequential data in a hierarchical store |
US4504902A (en) * | 1982-03-25 | 1985-03-12 | At&T Bell Laboratories | Cache arrangement for direct memory access block transfer |
JPS5958681A (ja) * | 1982-09-28 | 1984-04-04 | Fujitsu Ltd | ペ−ジイン制御方式 |
US4627000A (en) * | 1984-04-12 | 1986-12-02 | General Electric Company | Apparatus and method for copying data from one electronic demand register to another |
US4646233A (en) * | 1984-06-20 | 1987-02-24 | Weatherford James R | Physical cache unit for computer |
US4942518A (en) * | 1984-06-20 | 1990-07-17 | Convex Computer Corporation | Cache store bypass for computer |
JPH0616272B2 (ja) * | 1984-06-27 | 1994-03-02 | 株式会社日立製作所 | メモリアクセス制御方式 |
JPS61112260A (ja) * | 1984-11-07 | 1986-05-30 | Hitachi Ltd | 多重階層記憶システムにおけるスワツプ制御装置 |
JP3024422B2 (ja) * | 1993-04-01 | 2000-03-21 | 三菱電機株式会社 | プログラマブルコントローラおよびプログラマブルコントローラの運転方法 |
KR100247467B1 (ko) * | 1997-11-07 | 2000-03-15 | 윤종용 | 엠엠씨 커맨드를 이용한 교체 블록 로딩 방법 |
US10891227B2 (en) * | 2018-11-29 | 2021-01-12 | International Business Machines Corporation | Determining modified tracks to destage during a cache scan |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1196752A (en) * | 1967-05-04 | 1970-07-01 | Int Computers Ltd | Improvements relating to Data Handling Arrangements. |
US3588829A (en) * | 1968-11-14 | 1971-06-28 | Ibm | Integrated memory system with block transfer to a buffer store |
US3735360A (en) * | 1971-08-25 | 1973-05-22 | Ibm | High speed buffer operation in a multi-processing system |
US3771137A (en) * | 1971-09-10 | 1973-11-06 | Ibm | Memory control in a multipurpose system utilizing a broadcast |
FR129151A (de) * | 1974-02-09 | |||
US3967247A (en) * | 1974-11-11 | 1976-06-29 | Sperry Rand Corporation | Storage interface unit |
FR2344094A1 (fr) * | 1976-03-10 | 1977-10-07 | Cii | Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires |
US4161024A (en) * | 1977-12-22 | 1979-07-10 | Honeywell Information Systems Inc. | Private cache-to-CPU interface in a bus oriented data processing system |
-
1979
- 1979-12-06 JP JP15841779A patent/JPS5680872A/ja active Granted
-
1980
- 1980-11-28 AU AU64799/80A patent/AU535788B2/en not_active Ceased
- 1980-12-04 ES ES497457A patent/ES8201343A1/es not_active Expired
- 1980-12-05 CA CA000366292A patent/CA1149965A/en not_active Expired
- 1980-12-05 DE DE8080304397T patent/DE3071782D1/de not_active Expired
- 1980-12-05 EP EP80304397A patent/EP0030463B1/de not_active Expired
- 1980-12-05 US US06/213,401 patent/US4395763A/en not_active Expired - Lifetime
- 1980-12-05 BR BR8007988A patent/BR8007988A/pt not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPS6330655B2 (de) | 1988-06-20 |
BR8007988A (pt) | 1981-06-23 |
ES497457A0 (es) | 1981-12-16 |
CA1149965A (en) | 1983-07-12 |
EP0030463A2 (de) | 1981-06-17 |
JPS5680872A (en) | 1981-07-02 |
AU535788B2 (en) | 1984-04-05 |
EP0030463B1 (de) | 1986-09-24 |
EP0030463A3 (en) | 1983-03-16 |
US4395763A (en) | 1983-07-26 |
AU6479980A (en) | 1981-06-11 |
ES8201343A1 (es) | 1981-12-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |