DE20108758U1 - Anordnung von Speicherchipgehäusen auf DIMM-Platine - Google Patents

Anordnung von Speicherchipgehäusen auf DIMM-Platine

Info

Publication number
DE20108758U1
DE20108758U1 DE20108758U DE20108758U DE20108758U1 DE 20108758 U1 DE20108758 U1 DE 20108758U1 DE 20108758 U DE20108758 U DE 20108758U DE 20108758 U DE20108758 U DE 20108758U DE 20108758 U1 DE20108758 U1 DE 20108758U1
Authority
DE
Germany
Prior art keywords
memory chip
arrangement
chip packages
dimm board
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE20108758U
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE20108758U priority Critical patent/DE20108758U1/de
Publication of DE20108758U1 publication Critical patent/DE20108758U1/de
Priority to US10/155,847 priority patent/US20020196612A1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/185—Mounting of expansion boards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/184—Mounting of motherboards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/186—Securing of expansion boards in correspondence to slots provided at the computer enclosure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09409—Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Description

Der Beschreibungstext wurde nicht elektronisch erfaßt
Der Beschreibungstext wurde nicht elektronisch erfaßt
Der Beschreibungstext wurde nicht elektronisch erfaßt
Der Beschreibungstext wurde nicht elektronisch erfaßt
Der Beschreibungstext wurde nicht elektronisch erfaßt

Claims (2)

1. Anordnung von mehreren Speicherchipgehäusen mit jeweils mindestens einem im Inneren des Speicherchipgehäuses ange­ ordneten Speicherchip mit mehreren Pins, die aus dem je­ weiligen Speicherchipgehäuse herausgeführt sind, auf einer Platine, die an einer Längsseite eine mehrpolige Kontakt­ schiene für das Einstecken in einen Sockel eines Mother­ boards aufweist, dadurch gekennzeichnet, dass die mehreren Speicherchipgehäuse (2) in zwei Reihen (6, 7) parallel zu der Längsseite (3) der Platine (1) an­ geordnet sind.
2. Anordnung nach Anspruch 1, dadurch gekennzeichnet, dass die mehreren Speicherchipgehäuse (2) mit ihrer Längs­ seite (8) parallel zu der Längsseite (3) der Platine (1) angeordnet sind.
DE20108758U 2001-05-25 2001-05-25 Anordnung von Speicherchipgehäusen auf DIMM-Platine Expired - Lifetime DE20108758U1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE20108758U DE20108758U1 (de) 2001-05-25 2001-05-25 Anordnung von Speicherchipgehäusen auf DIMM-Platine
US10/155,847 US20020196612A1 (en) 2001-05-25 2002-05-24 Arrangement of memory chip housings on a DIMM circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE20108758U DE20108758U1 (de) 2001-05-25 2001-05-25 Anordnung von Speicherchipgehäusen auf DIMM-Platine

Publications (1)

Publication Number Publication Date
DE20108758U1 true DE20108758U1 (de) 2001-08-09

Family

ID=7957316

Family Applications (1)

Application Number Title Priority Date Filing Date
DE20108758U Expired - Lifetime DE20108758U1 (de) 2001-05-25 2001-05-25 Anordnung von Speicherchipgehäusen auf DIMM-Platine

Country Status (2)

Country Link
US (1) US20020196612A1 (de)
DE (1) DE20108758U1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005051497B3 (de) * 2005-10-26 2006-12-07 Infineon Technologies Ag Speichermodul mit einer elektronischen Leiterplatte und einer Mehrzahl von gleichartigen Halbleiterchips
DE102005051998B3 (de) * 2005-10-31 2007-01-11 Infineon Technologies Ag Halbleiterspeichermodul

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7656678B2 (en) 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US7423885B2 (en) 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US7760513B2 (en) 2004-09-03 2010-07-20 Entorian Technologies Lp Modified core for circuit module system and method
US7443023B2 (en) 2004-09-03 2008-10-28 Entorian Technologies, Lp High capacity thin module system
US7511968B2 (en) * 2004-09-03 2009-03-31 Entorian Technologies, Lp Buffered thin module system and method
KR100665840B1 (ko) * 2004-12-10 2007-01-09 삼성전자주식회사 데이지 체인 구조의 메모리 모듈 및 그의 형성 방법
US7511969B2 (en) * 2006-02-02 2009-03-31 Entorian Technologies, Lp Composite core circuit module system and method
WO2008051940A2 (en) * 2006-10-23 2008-05-02 Virident Systems, Inc. Methods and apparatus of dual inline memory modules for flash memory
US20080112142A1 (en) * 2006-11-10 2008-05-15 Siva Raghuram Memory module comprising memory devices
US10236032B2 (en) * 2008-09-18 2019-03-19 Novachips Canada Inc. Mass data storage system with non-volatile memory modules
JP1529446S (de) * 2014-10-16 2015-07-21

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005051497B3 (de) * 2005-10-26 2006-12-07 Infineon Technologies Ag Speichermodul mit einer elektronischen Leiterplatte und einer Mehrzahl von gleichartigen Halbleiterchips
US7375971B2 (en) 2005-10-26 2008-05-20 Infineon Technologies Ag Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type
DE102005051998B3 (de) * 2005-10-31 2007-01-11 Infineon Technologies Ag Halbleiterspeichermodul

Also Published As

Publication number Publication date
US20020196612A1 (en) 2002-12-26

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Legal Events

Date Code Title Description
R207 Utility model specification

Effective date: 20010913

R156 Lapse of ip right after 3 years

Effective date: 20041201