CN216980559U

CN216980559U - Display panel and display device

Info

Publication number: CN216980559U
Application number: CN202220041126.3U
Authority: CN
Inventors: 刘柯志; 黎倩
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-01-07
Filing date: 2022-01-07
Publication date: 2022-07-15
Anticipated expiration: 2032-01-07

Abstract

The embodiment of the disclosure provides a display panel and a display device, relates to the technical field of display, and aims to solve the problem of improving the transparency of a transparent display device. The display panel is provided with a display area, the display area comprises a plurality of sub-display areas which are distributed at intervals, and one sub-display area comprises at least two sub-pixel areas. The display panel comprises a substrate, an insulation stack structure and an encapsulation layer. The insulating stacked structure comprises a plurality of insulating medium layers which are stacked on the substrate, a plurality of first isolation grooves are formed in the surface, away from the substrate, of the insulating stacked structure, and at least one first isolation groove is arranged along the circumferential direction of the sub-display area. The packaging layer is arranged on one side, far away from the substrate, of the insulating stacked structure, and a part of the packaging layer is located in the first isolation grooves.

Description

Display panel and display device

Technical Field

The utility model relates to the technical field of display, in particular to a display panel and a display device.

Background

The organic light emitting display device has the advantages of self-luminescence, fast response, wide viewing angle, high brightness, bright color, lightness and thinness, etc., and thus becomes an important display technology.

The organic light emitting display device may be a transparent display device. When the transparent display device displays a picture, a user can see the displayed image from the front side of the screen and can see an object on the back side of the transparent display device through the screen. Transparent display devices have been widely used in smart homes, vehicle applications, military industries, and other industries.

However, how to improve the transparency of the transparent display device has become an urgent problem to be solved in the industry.

SUMMERY OF THE UTILITY MODEL

Embodiments of the present invention provide a display panel and a display device, aiming to improve the transparency of a transparent display device.

In order to achieve the above purpose, the embodiment of the utility model adopts the following technical scheme:

in a first aspect, a display panel is provided, where the display panel has a display area, and the display area includes a plurality of sub-display areas distributed at intervals, and a sub-display area includes at least two sub-pixel areas. The display panel includes a substrate, an insulation stack structure, and an encapsulation layer. The insulating stacked structure comprises a plurality of insulating medium layers which are stacked on the substrate, a plurality of first isolation grooves are formed in the surface, away from the substrate, of the insulating stacked structure, and at least one first isolation groove is arranged along the circumferential direction of the sub-display area. The packaging layer is arranged on one side, far away from the substrate, of the insulating stacked structure, and a part of the packaging layer is located in the first isolation grooves.

In some embodiments, at least one of the plurality of insulating dielectric layers is a transmittance enhancing dielectric layer. The transmittance enhancement medium layer is provided with a plurality of through grooves, the through grooves penetrate through the transmittance enhancement medium layer along the thickness direction of the display panel, and the through grooves are used for forming a first isolation groove.

In some embodiments, the insulating dielectric layer closest to the encapsulation layer is a transmittance enhancement dielectric layer. Or, in the plurality of insulating dielectric layers, each of the N continuous insulating dielectric layers close to the encapsulation layer is a transmittance enhancement dielectric layer. The two adjacent transmittance enhancement medium layers are a first transmittance enhancement medium layer and a second transmittance enhancement medium layer, and the second transmittance enhancement medium layer is positioned on one side, far away from the substrate, of the first transmittance enhancement medium layer. The through groove on the first transmittance enhancement medium layer is communicated with the through groove on the second transmittance enhancement medium layer. And N is greater than or equal to 2 and less than or equal to the number of the insulating dielectric layers in the insulating stacked structure.

In some embodiments, an orthographic projection of a through groove on the first transmittance enhancement medium layer on the substrate is within an orthographic projection of a through groove on the second transmittance enhancement medium layer on the substrate.

In some embodiments, the plurality of insulating dielectric layers includes a plurality of inorganic insulating layers, each inorganic insulating layer being an insulating dielectric layer. The plurality of insulating medium layers further comprise at least one organic insulating layer, the at least one organic insulating layer is positioned on one side, away from the substrate, of the plurality of inorganic insulating layers, and each organic insulating layer is an insulating medium layer. The plurality of insulating medium layers further comprise a pixel defining layer which is positioned on one side of the at least one organic insulating layer far away from the substrate, and the pixel defining layer is an insulating medium layer. At least one of the plurality of inorganic insulating layers, the at least one organic insulating layer and the pixel defining layer is a transmittance enhancing dielectric layer.

In some embodiments, the insulation stack structure further includes a plurality of first isolation walls, at least one first isolation wall is disposed along a circumferential direction of the sub-display area, and is located at a side of the at least one first isolation groove disposed along the circumferential direction of the sub-display area, which is away from the sub-display area, and is used for forming a sidewall of the at least one first isolation groove disposed along the circumferential direction of the sub-display area. Or the insulating stacked structure further comprises a plurality of second isolation walls, each second isolation wall is located between two adjacent sub-display areas, the second isolation walls extend to form an isolation net, and the isolation net separates the first isolation grooves surrounding different sub-display areas.

In some embodiments, the first isolation wall includes a first isolation pattern and a second isolation pattern sequentially arranged along a direction away from the substrate, and an orthogonal projection of the second isolation pattern on the substrate is located within an orthogonal projection of the first isolation pattern on the substrate.

In some embodiments, the display panel further includes an electrode layer located on a side of the insulating stacked structure away from the substrate, the electrode layer includes a plurality of electrode patterns spaced apart from each other, and an electrode pattern covers at least a partial region of a sub-display region.

In some embodiments, the display panel further includes a plurality of signal lines disposed in the display region and disposed on a side of the electrode layer adjacent to the substrate, each of the electrode patterns being coupled to one of the signal lines.

In some embodiments, the display panel further includes a light-emitting functional layer on a side of the insulating stack structure away from the substrate, the light-emitting functional layer includes a plurality of light-emitting functional patterns spaced apart from each other, and a light-emitting functional pattern covers at least a partial region of a sub-display region.

In some embodiments, the encapsulation layer comprises an organic encapsulation layer, a portion of which is located in the first isolation trench.

In some embodiments, the surface of the insulating stacked structure away from the substrate further has at least one second isolation groove, and the at least one second isolation groove is disposed along the circumferential direction of the display area. A portion of the encapsulation layer is located in the at least one second isolation trench.

In some embodiments, the display panel further includes a retaining wall disposed on a side of the insulating stacked structure away from the substrate and disposed on a side of the at least one second isolation trench away from the display area, the retaining wall surrounding the display area. The packaging layer covers the retaining wall.

In a second aspect, a display device is provided, which includes the display panel provided in any of the above embodiments.

In the display panel provided by the embodiment of the disclosure, the insulating stacked structure is located between the substrate and the encapsulation layer, and a surface of the insulating stacked structure, which is far away from the substrate, is provided with a plurality of first isolation grooves, and at least one first isolation groove is arranged along the circumferential direction of the sub-display area. At the first isolation groove, the thickness of the insulation stack structure is smaller than the thickness at other positions of the insulation stack structure, and therefore, the light transmittance of the display panel at the first isolation groove can be higher, and the transparency of the display panel can be improved.

It can be understood that the display device provided by the second aspect includes the display panel, and therefore, the beneficial effects achieved by the display device can refer to the beneficial effects of the display panel in the foregoing, which are not described in detail herein.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a block diagram of a display device according to some embodiments;

FIG. 2 is a block diagram of a display panel according to some embodiments;

FIGS. 3A-3F are block diagrams of sub-display areas in a display panel according to some embodiments;

FIG. 4 is a cross-sectional view of the display panel of FIG. 2 along section line AA';

FIG. 5 is a partial enlarged view of a region Q1 in the display panel of FIG. 2;

FIG. 6 is a top view of a display panel according to some embodiments;

FIG. 7 is a partial enlarged view of a region Q2 in the display panel of FIG. 6;

FIG. 8 is a top view of a display panel according to some embodiments;

FIG. 9 is an enlarged view of a portion of the area Q3 in the display panel of FIG. 8;

FIG. 10 is a top view of a display panel according to some embodiments;

FIG. 11 is a partial enlarged view of a region Q4 in the display panel of FIG. 10;

FIG. 12 is a cross-sectional view of the display panel of FIG. 8 along section line BB';

FIG. 13 is an enlarged view of a portion of a region Q5 of the display panel of FIG. 2;

FIG. 14 is a cross-sectional view of the display panel of FIG. 13 taken along section line CC';

FIG. 15 is an enlarged view of a portion of the area Q6 in the display panel of FIG. 6;

FIG. 16 is a top view of a display panel according to some embodiments;

FIG. 17 is a block diagram of an electrode pattern and signal lines in a display panel according to some embodiments;

FIG. 18A is a top view of a display panel according to some embodiments;

FIG. 18B is a cross-sectional view of the display panel of FIG. 18A along section line DD';

FIG. 19 is a top view of a display panel according to some embodiments;

fig. 20 is a sectional view of the display panel in fig. 19 along a sectional line EE'.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C", both including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" is meant to be open and inclusive in that a process, step, calculation, or other action that is "based on" one or more stated conditions or values may, in practice, be based on additional conditions or exceed the stated values.

As used herein, "substantially" or "approximately" includes the stated value as well as an average value that is within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

As used herein, "parallel," "perpendicular," and "equal" include the stated case and cases that approximate the stated case to within an acceptable range of deviation as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where an acceptable deviation from approximately parallel may be, for example, within 5 °; "perpendicular" includes absolute perpendicular and approximately perpendicular, where an acceptable deviation from approximately perpendicular may also be within 5 °, for example. "equal" includes absolute and approximate equality, where the difference between the two, which may be equal within an acceptable deviation of approximately equal, is less than or equal to 5% of either.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Embodiments of the present disclosure provide a display device. FIG. 1 is a block diagram of a display device according to some embodiments. Referring to fig. 1, a display device 1 is a product having an image (including a still image or a moving image, wherein the moving image may be a video) display function. For example, the display device 1 may be: a display, a television, a billboard, a Digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a Personal Digital Assistant (PDA), a Digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a home appliance, an information inquiry apparatus (e.g., an inquiry apparatus for business in a section of e-government affairs, a bank, a hospital, electric power, etc.), a monitor, and the like.

The display device 1 may include a display panel 10, and the display device 1 may further include a driving control circuit 20 coupled to the display panel 10. The drive control circuit 20 is configured to supply an electric signal to the display panel 10. Illustratively, the drive control circuit 20 may include: a data driving circuit 210 (also referred to as a Source Driver IC), the data driving circuit 210 being configured to provide a data driving signal (also referred to as a data signal) to the display panel 10. The driving Control circuit 20 may further include a timing Control circuit 220 (also referred to as a timing controller, or Timer Control Register, abbreviated as TCON) coupled to the data driving circuit 210.

In some embodiments, the driving control circuit 20 may further include a scan driving circuit 110. In other embodiments, the scan driving circuit 110 may be integrated in the display panel 10, and the display panel 10 may also include the scan driving circuit 110. Since the scan driving circuit 110 is disposed on the display panel 10, the scan driving circuit 110 may also be referred to as a Gate Driver on Array (GOA) scan driving circuit disposed on the Array substrate.

Specifically, the timing control circuit 220 may be coupled to the scan driving circuit 110, and may also be coupled to the data driving circuit 210. The timing control circuit 220 may be configured to receive a display signal, for example, a power signal, a video image signal, a communication signal (e.g., a signal corresponding to the IIC communication protocol), a mode control signal (e.g., a mode control signal corresponding to the test mode, or a mode control signal corresponding to the normal display mode), and the like. The video image signal is, for example, an MIPI (Mobile Industry Processor Interface) signal or an LVDS (Low-Voltage Differential Signaling) signal. The video image signal may include: image data and timing control signals. The image data includes, for example, pixel data of a plurality of sub-pixels, and the pixel data may be RGB data or the like. The timing control signals include, for example, a Data Enable (Data Enable, which may be abbreviated as DE), a line sync (Hsync, which may be abbreviated as HS), and a field sync (Vsync, which may be abbreviated as VS).

The timing control circuit 220 may be further configured to output a first control signal and image data to the data driving circuit 210 and a second control signal to the scan driving circuit 110 in response to the display signal. Wherein the first control signal is configured to control the operation timing of the data driving circuit 210, and the second control signal is configured to control the operation timing of the scan driving circuit 110.

The data driving circuit 210 may be configured to convert the received image data into data signals of a plurality of light emitting devices E (to be described later) in the display panel 10 and output the data signals to pixel driving circuits DC (to be described later) coupled to the respective light emitting devices E at an operation timing determined by the first control signal. The scan driving circuit 110 is configured to output the scan signals to the plurality of pixel driving circuits DC at the operation timing determined by the second control signal.

Some embodiments of the present disclosure also provide a display panel. The display panel may be used as the display panel in the display device provided in any of the above embodiments. Of course, the display panel may also be applied to other display devices, and the embodiment of the disclosure is not limited thereto.

Referring to fig. 1, the display panel 10 may be one of an OLED (Organic Light Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diode) display panel, and a micro LED (including a MiniLED or a micro LED, where the LED is a Light Emitting Diode) display panel.

With continued reference to fig. 1, the display panel 10 may include a plurality of light emitting devices E. The display panel 10 may further include a plurality of pixel driving circuits DC. A light emitting device E (e.g., each light emitting device E) may be DC coupled to a pixel driving circuit.

The light emitting device E may be one of an organic light emitting diode OLED, a quantum dot light emitting diode QLED, and a light emitting diode LED.

The pixel driving circuit DC may be configured to supply an electrical signal (e.g., a driving voltage or a driving current) to the light emitting device E coupled to the pixel driving circuit DC in response to the received scan signal and data signal to drive the light emitting device E to emit light, so that the display panel 10 may display a picture.

The pixel driving circuit DC may comprise a plurality of transistors and at least one (e.g. one; as another example a plurality) of capacitors. For example, the pixel driving circuit DC may have a structure of "2T 1C", "6T 1C", "7T 1C", "6T 2C", or "7T 2C". Here, "T" denotes a transistor, for example, a thin film transistor. The numbers preceding "T" indicate the number of transistors. "C" represents a capacitor, and the number located in front of "C" represents the number of capacitors.

FIG. 2 is a block diagram of a display panel according to some embodiments. Fig. 3A-3C are block diagrams of sub-display regions in a display panel according to some embodiments. It should be noted that fig. 2 only shows the structure of the display area of the display panel, and the structure of the peripheral area, for example, the scan driving circuit, is omitted.

Referring to fig. 2, the display panel 10 has a display area AA and a peripheral area SA. The peripheral area SA may be located on at least one side (e.g., one side; e.g., four sides, including upper and lower sides and left and right sides) of the display area AA.

Referring to fig. 2 and 3A to 3D, the display area AA includes a plurality of sub-display areas K spaced apart from each other. A sub-display section K (e.g., each sub-display section K) includes at least two (e.g., three; e.g., four; e.g., eight) sub-pixel sections P. In the display panel 10, a plurality of (e.g., all) sub-display sections K may be distributed in an array. For example, the plurality of sub-display regions K distributed along the X-axis direction may be a row of sub-display regions, and the plurality of sub-display regions K distributed along the Y-axis direction may be a column of sub-display regions, where the X-axis direction and the Y-axis direction are perpendicular and parallel to the extending direction of the display panel 10.

One sub-pixel region P (e.g., each sub-pixel region P) may emit light. Specifically, at least a portion of a light emitting device may be positioned in a sub-pixel region P, and the light emitting device may emit light so that the sub-pixel region P may emit light.

Referring to fig. 3A to 3D, a sub-display section K (e.g., each sub-display section K) may include a plurality of sub-pixel regions P. The plurality of sub-pixel regions P may include a plurality of sub-pixel regions P having different emission colors. The luminance of the different color sub-pixel regions P in the sub-display region K is adjusted, and the display of multiple colors can be realized through color combination and superposition, thereby realizing full-color display of the display panel 10. Illustratively, the plurality of sub-pixel regions P of one sub-display region K includes three sub-pixel regions P having different emission colors, for example, a first sub-pixel region P1, a second sub-pixel region P2, and a third sub-pixel region P3, and the first sub-pixel region P1, the second sub-pixel region P2, and the third sub-pixel region P3 may emit three primary colors of light, respectively, for example, the first sub-pixel region P1 may emit red light, the second sub-pixel region P2 may emit green light, and the third sub-pixel region P3 may emit blue light.

In some possible implementations, referring to fig. 3A and 3B, a sub-display region K includes three sub-pixel regions P, for example, the sub-display region K may include a first sub-pixel region P1, a second sub-pixel region P2, and a third sub-pixel region P3. Also illustratively, referring to fig. 3C and 3E, a sub-display region K includes four sub-pixel regions P, and for example, the sub-display region K may include a first sub-pixel region P1, a third sub-pixel region P3, and two second sub-pixel regions P2. Also illustratively, referring to fig. 3D and 3F, a sub-display region K includes eight sub-pixel regions P, and particularly, the sub-display region K may include two first sub-pixel regions P1, two third sub-pixel regions P3, and four second sub-pixel regions P2.

It is understood that the sub-pixel regions P in a sub-display region K of the display panel may have other arrangements, and the embodiment of the disclosure is not limited thereto.

Fig. 4 is a cross-sectional view of the display panel of fig. 2 along a section line AA'. Referring to fig. 4, the display panel 10 includes a substrate 110. The substrate 110 may provide a basis for other structures in the display panel 10. The substrate 110 may be rigid or flexible. When the substrate 110 is a rigid substrate, a material forming the rigid substrate may be glass, and when the substrate 110 is a flexible substrate, a material forming the flexible substrate may be PI (polyimide), PET (polyethylene terephthalate), ultra-thin glass, or the like.

In some embodiments, the substrate 110 is a flexible substrate. For example, the material of the substrate 110 may include PI. At this time, in the process of manufacturing the display panel 10, the substrate 110 may be manufactured on a rigid base, and then other structures of the display panel 10 may be manufactured on the substrate 110. The rigid substrate may provide support in the fabrication of the display panel 10. Thereafter, the display panel 10 may be peeled off from the rigid substrate to form the display panel 10. Illustratively, the rigid substrate may be a glass substrate.

In addition, the substrate 110 may be a transparent substrate. For example, the material of the substrate 110 includes PI, which may be transparent, so that the substrate 110 is a transparent substrate. Thus, the light transmittance of the display panel 10 can be improved, and the transparency of the display panel 10 can be improved.

The display panel 10 may further include a buffer layer 120. The buffer layer 120 may be disposed on the substrate 110 and in contact with the substrate 110. The buffer layer 120 may be configured to block moisture and impurity particles in the substrate 110, reducing moistureAnd damage of the light emitting device by the impurity particles in the substrate 110, and thus the lifespan of the display panel 10 may be extended. The material of the buffer layer 120 includes, for example, SiO₂Or SiOC.

With continued reference to fig. 4, the display panel 10 may include a first electrode layer 131, a second electrode layer 132, and a light emitting layer 133 between the first electrode layer 131 and the second electrode layer 132. The display panel 10 may further include one or more light emitting function layers 134 between the first electrode layer 131 and the second electrode layer 132. The first electrode layer 131, the second electrode layer 132, the light emitting layer 133, and the one or more light emitting function layers 134 may form a plurality of light emitting devices E.

The first electrode layer 131 may be disposed on a side of the second electrode layer 132 close to the substrate 110. The first electrode layer 131 may include a plurality of first electrodes 131p, and a first electrode 131p (e.g., each first electrode 131p) may be configured as an electrode, e.g., an anode, of the light emitting device E. The material of the first electrode layer 131 may include a metal compound, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

The second electrode layer 132 may include a plurality of second electrodes 132p, and a second electrode 132p (e.g., each second electrode 132p) may be configured as an electrode (e.g., a cathode) of a light emitting device E. The material of the second electrode layer 132 may include a metal or an alloy, such as a metal of magnesium (Mg), titanium (Ti), silver (Ag), or an alloy formed of a plurality of metals. The material of the second electrode layer 132 may further include a metal compound, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The second electrode layer 132 may be transparent or translucent. Thus, the second electrode layer 132 may allow light emitted from the light emitting layer 133 to exit through the second electrode layer 132. At this time, the light emitting device E may be a top emission type light emitting device.

The light emitting layer 133 may include a plurality of light emitting patterns 133p, and a light emitting pattern 133p (e.g., each light emitting pattern 133p) may be positioned between the first electrode 131p and the second electrode 132p of a light emitting device E. The light emitting patterns 133p may emit light, for example, the light emitting patterns 133p may emit red light, green light, blue light, or white light. The material of the light emitting pattern 133p may include an organic light emitting material. It should be noted that, in this context, an orthographic projection of a pattern (e.g., a light-emitting pattern) on a substrate may have a closed outer contour.

The light emitting function layer 134 (e.g., each light emitting function layer 134) may be one of a hole injection layer, a hole transport layer, an electron blocking layer, an electron injection layer, an electron transport layer, and a hole blocking layer. When the light emitting function layer 134 is one of a hole injection layer, a hole transport layer, and an electron blocking layer, the light emitting function layer 134 may be positioned between the light emitting layer 133 and the first electrode layer 131. When the light emitting function layer 134 is one of an electron injection layer, an electron transport layer, and a hole blocking layer, the light emitting function layer 134 may be located between the light emitting layer 133 and the second electrode layer 132.

Exemplarily, referring to fig. 4, the display panel 10 includes two light emission function layers 134, i.e., a light emission function layer 134a and a light emission function layer 134 b. The light emitting function layer 134a is positioned between the first electrode layer 131 and the light emitting layer 133, and the light emitting function layer 134a may be a hole transport layer. The light emitting function layer 134b is located between the second electrode layer 132 and the light emitting layer 133, and the light emitting function layer 134b may be an electron transport layer.

Referring to the above description, the display panel 10 further includes a plurality of pixel driving circuits. With continued reference to fig. 4, the display panel 10 may include a semiconductor layer 140 and a plurality of conductor layers 150 disposed in a stack. The semiconductor layer 140 and the plurality of conductor layers 150 may form a plurality of pixel driving circuits in the display panel 10.

Specifically, the semiconductor layer 140 may be disposed on the substrate 110. Illustratively, the semiconductor layer 140 may be disposed on a side of the buffer layer 120 away from the substrate 110. Referring to the above description, a pixel driving circuit (e.g., each pixel driving circuit) in the display panel 10 may include a plurality of transistors T, and a transistor T (e.g., each transistor T) is, for example, a thin film transistor. A transistor T (e.g. each transistor T) may be implemented as shown in fig. 4. Specifically, the semiconductor layer 140 may include active layers Ta of a plurality of transistors T.

A plurality of conductor layers 150 may be stacked on the substrate 110. Illustratively, the plurality of conductor layers 150 may be disposed on a side of the semiconductor layer 140 away from the substrate 110 and on a side of the plurality of light emitting devices E close to the substrate 110.

The plurality of conductor layers 150 may include a first conductor layer 151, and the first conductor layer 151 may include gate electrodes Tg of the plurality of transistors T. The first conductor layer 151 may further include one plate of a capacitor in each pixel driving circuit. The first conductor layer 151 may further include one or more signal lines in each pixel driving circuit, for example, one or more signal lines extending in the Y-axis direction and coupled to the scan driving circuit.

The plurality of conductor layers 150 can also include a second conductor layer 152. The second conductor layer 152 may include another plate of the capacitor in each pixel driving circuit, and may further include one or more signal lines in each pixel driving circuit, for example, one or more signal lines extending in the Y-axis direction and coupled to the scan driving circuit.

Plurality of conductor layers 150 may also include third conductor layer 153 and/or fourth conductor layer 154. The third and fourth conductor layers 153 and 154 may include one or more signal lines in each pixel driving circuit, for example, one or more signal lines extending in the X-axis direction and coupled to the data driving circuit.

With continued reference to fig. 4, the display panel 10 further includes a plurality of insulating dielectric layers, which are stacked on the substrate 110 to form an insulating stack structure 160. It can also be said that the display panel 10 further includes an insulating stack structure 160, and the insulating stack structure 160 includes a plurality of insulating medium layers stacked on the substrate 110. For example, the insulating stack structure 160 may be disposed on the substrate 110 and on a side of the second electrode layer 132 close to the substrate 110.

In some embodiments, the plurality of insulating medium layers may include a plurality of inorganic insulating layers 161, each inorganic insulating layer 161 being an insulating medium layer. As described above, a plurality of conductor layers 150 may be stacked, and in order to separate adjacent two conductor layers 150, one inorganic insulating layer 161 may be disposed between the adjacent two conductor layers 150.

Illustratively, the plurality of inorganic insulating layers 161 may include a first inorganic insulating layer 161a, the first inorganic insulating layer 161a being disposed between the semiconductor layer 140 and the first conductor layer 151. The first inorganic insulating layer 161a may be configured as a gate insulating layer of the plurality of transistors T. The plurality of inorganic insulating layers 161 may further include a second inorganic insulating layer 161 b. The second inorganic insulating layer 161b is disposed between the first conductor layer 151 and the second conductor layer 152, and is configured to separate the first conductor layer 151 and the second conductor layer 152. The plurality of inorganic insulating layers 161 may further include a third inorganic insulating layer 161 c. The third inorganic insulating layer 161c is provided between the second conductor layer 152 and the third conductor layer 153, and is configured to separate the second conductor layer 152 and the third conductor layer 153. The plurality of inorganic insulating layers 161 may further include a fourth inorganic insulating layer 161 d. The fourth inorganic insulating layer 161d is provided between the third conductor layer 153 and the fourth conductor layer 154, and is configured to separate the third conductor layer 153 and the fourth conductor layer 154.

With continued reference to fig. 4, based on the above, the display panel 10 may include a plurality of conductor layers 150 and a plurality of inorganic insulating layers 161, and a plurality of light emitting devices E may be disposed on a side of the plurality of conductor layers 150 and the plurality of inorganic insulating layers 161 away from the substrate 110. In some embodiments, in order to improve the flatness of the plurality of light emitting devices E and thus improve the performance of the plurality of light emitting devices E, the plurality of insulating medium layers may further include at least one (e.g., one; as another example, a plurality of) organic insulating layers 162, each organic insulating layer 162 being an insulating medium layer. At least one (e.g., all) of the organic insulating layers 162 are positioned on a side of the plurality of (e.g., all) of the inorganic insulating layers 161 away from the substrate 110, and are disposed on a side of the plurality of light emitting devices E close to the substrate 110. An organic insulating layer 162 (e.g., each organic insulating layer 162) may be configured as a planarization layer, which may make the light emitting device E disposed on the side of the organic insulating layer 162 away from the substrate 110 relatively flat.

Exemplarily, the plurality of organic insulating layers 162 may include a first organic insulating layer 162a and a second organic insulating layer 162 b. The first organic insulating layer 162a may be disposed between the fourth inorganic insulating layer 161d and the fourth conductor layer 154, and may make the fourth conductor layer 154 flat. The second organic insulating layer 162b is disposed between the fourth conductor layer 154 and the plurality of light emitting devices E, and particularly, the second organic insulating layer 162b may be disposed between the fourth conductor layer 154 and the first electrode layer 131, so that the plurality of light emitting devices E may be relatively flat, thereby improving performance of the plurality of light emitting devices E.

In some embodiments, the plurality of insulating medium layers may include a pixel defining layer 163, and the pixel defining layer 163 is an insulating medium layer. The pixel defining layer 163 may be disposed on the substrate 110. Specifically, the pixel defining layer 163 may be disposed on a side of the first electrode layer 131 away from the substrate 110, and disposed on a side of the second electrode layer 132 close to the substrate 110.

The pixel defining layer 163 has a plurality of openings H. An opening H may be configured to define a sub-pixel region. Illustratively, a sub-pixel region (e.g., each sub-pixel region) may be directly opposite an opening H, e.g., at least a portion (e.g., part; e.g., all) of an orthographic projection of a sub-pixel region (e.g., each sub-pixel region) on the substrate 110 may overlap with an orthographic projection of an opening H on the substrate 110.

With continued reference to fig. 4, the display panel 10 further includes an encapsulation layer 170. The encapsulation layer 170 may be disposed on a side of the insulation stack 160 away from the substrate 110. The encapsulation layer 170 may also be disposed on a side of the plurality of light emitting devices E away from the substrate 110, for example, the encapsulation layer 170 may be disposed on a side of the second electrode layer 132 away from the substrate 110. The encapsulation layer 170 may cover the plurality of light emitting devices E to isolate the light emitting devices E from external moisture and oxygen, which may reduce damage of the external moisture and oxygen to the light emitting devices E.

In some embodiments, the encapsulation layer 170 may have a laminate structure. Illustratively, the encapsulation layer 170 may include an organic encapsulation layer 173. The encapsulation layer 170 may further include a first inorganic encapsulation layer 171 and a second inorganic encapsulation layer 172. The organic encapsulation layer 173 may be disposed between the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 172.

Among them, the material of the organic encapsulation layer 173 may include an organic material. The organic encapsulation layer 173 may be configured as a planarization layer, which may make the surface of the display panel 10 away from the substrate 110 relatively flat. The organic encapsulation layer 173 may also be configured to relieve stress of the first and second inorganic encapsulation layers 171 and 172.

The first and second inorganic encapsulation layers 171 and 172 may be configured to isolate the light emitting device E from external moisture and oxygen, and damage of the light emitting device E by the external moisture and oxygen may be reduced. In addition, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 172 may encapsulate the organic encapsulation layer 173, for example, an orthographic projection of the organic encapsulation layer 173 on the first inorganic encapsulation layer 171 may be located inside the first inorganic encapsulation layer 171, and/or an orthographic projection of the organic encapsulation layer 173 on the second inorganic encapsulation layer 172 may be located inside the second inorganic encapsulation layer 172. In this way, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 172 may be configured to isolate the organic encapsulation layer 173 from external moisture and oxygen, damage of the organic encapsulation layer 173 by the external moisture and oxygen may be reduced, and structural stability of the display panel may be improved.

Referring to fig. 2 and 4, the surface 160' of the insulation stack structure 160 away from the substrate 110 has a plurality of first isolation grooves S1.

At a first isolation trench S1 (e.g., each first isolation trench S1), the thickness of the insulation stack 160 (e.g., the dimension of the insulation stack in the Z-axis direction, which is perpendicular to the X-axis direction, and perpendicular to the Y-axis direction) is smaller than the thickness at other locations of the insulation stack 160. Illustratively, a portion of one or more insulating dielectric layers in the insulating stack structure 160 may be removed to form a first isolation trench S1 on a surface 160' of the insulating stack structure 160 away from the substrate 110.

With continued reference to fig. 4, a portion of the encapsulation layer 170 may be located in a plurality (e.g., all) of the first isolation trenches S1. Illustratively, the material of the organic encapsulation layer 173 includes an organic material, so the organic encapsulation layer 173 may be a film having a relatively flat surface and a non-uniform thickness. Based on this, the encapsulation layer 170 including the organic encapsulation layer 173 may fill a part or all of one first isolation groove S1 (e.g., each first isolation groove S1).

Based on the above, since the surface 160' of the insulation stack structure 160 away from the substrate 110 has the plurality of first isolation grooves S1, at the first isolation groove S1, the thickness of the insulation stack structure 160 is small compared to the thickness at other positions of the insulation stack structure 160, and therefore, the light transmittance of the display panel 10 at the first isolation groove S1 may be high, so that the transparency of the display panel may be improved. In addition, a first isolation groove S1 (e.g., each first isolation groove S1) may be filled with the encapsulation layer 170. The transparency of the encapsulation layer 170 may be better than that of the insulation stack structure 160, and therefore, the light transmittance of the first isolation groove S1 filled with the encapsulation layer 170 may be higher, so that the display panel 10 provided with the first isolation groove S1 may have higher transparency.

Fig. 5 is a partially enlarged view of a region Q1 in the display panel of fig. 2. FIG. 6 is a top view of a display panel according to some embodiments. Fig. 7 is a partially enlarged view of a region Q2 in the display panel of fig. 6. Fig. 8 is a top view of a display panel according to some embodiments, and fig. 9 is a partial enlarged view of a region Q3 in the display panel in fig. 8. Fig. 10 is a top view of a display panel according to some embodiments, and fig. 11 is a partial enlarged view of a region Q4 in the display panel of fig. 10. It should be noted that, compared to the display panel in fig. 2, the display panel in fig. 6 may have the same structure except that the shape of the first isolation groove is different. Similarly, compared to the display panel in fig. 8, the remaining structure of the display panel in fig. 10 may be the same except for the shape of the first isolation groove.

Referring to fig. 2, 5 to 11, among the plurality of first isolation grooves S1 of the display panel 10, at least one (e.g., one; e.g., a plurality of) first isolation grooves S1 are disposed in a circumferential direction of a sub-display region K. It can also be said that the periphery (including both sides in the X-axis direction and both sides in the Y-axis direction) of one sub-display section K (e.g., each sub-display section K) is provided with one or more first separation grooves S1.

It should be noted that, in this context, an isolation groove (e.g., a first isolation groove or a second isolation groove) may be a groove having two oppositely disposed sidewalls and extending in a certain direction. It can also be said that for an isolation trench, the isolation trench has two sidewalls disposed oppositely in a direction perpendicular to the extending direction of the isolation trench.

Based on the above, referring to fig. 2, 5, 8 and 9, in some embodiments, a plurality of first isolation grooves S1 are disposed around a sub display region K (e.g., each sub display region K). Illustratively, four first isolation grooves S1 are disposed around one sub-display region K, wherein each first isolation groove S1 may be an elongated groove extending along the X-axis direction or the Y-axis direction and disposed at one side of the sub-display region K (e.g., one side along the X-axis direction or one side along the Y-axis direction). In some possible implementations, referring to fig. 2 and 5, for a sub-display region K, a plurality of first isolation grooves S1 around the sub-display region K may be spaced apart from each other. In other possible implementations, referring to fig. 8 and 9, for a sub-display region K, a plurality of first isolation grooves S1 around the sub-display region K may be communicated with each other.

Referring to fig. 6, 7, 10 and 11, in other embodiments, a first isolation groove S1 is disposed around a sub display region K (e.g., each sub display region K), and the first isolation groove S1 surrounds the sub display region K.

With continued reference to fig. 2, 5 to 11, since at least one (e.g., one; and, for example, a plurality of) first isolation grooves S1 are disposed along the circumference of the sub-display regions K, that is, one or more first isolation grooves S1 may be disposed around one sub-display region K, the light transmittance of the display panel 10 may be high around the sub-display region K, so that the display panel 10 may have high transparency. Further, in the display panel 10, one or more first isolation grooves S1 may be disposed around each sub-display region K, so that the light transmittance of the display panel 10 may be further improved, and the transparency of the display panel 10 may be further improved.

Referring to fig. 4, in some embodiments, for an insulating dielectric layer in the insulating stack structure 160, the insulating dielectric layer may have a plurality of through slots ST. It should be noted that, in this context, a film layer having a through groove may mean that the through groove penetrates through the film layer in the thickness direction of the display panel 10.

A through groove ST may be used to form the first separating groove S1. Exemplarily, when the side of the insulating medium layer having the through trench ST away from the substrate 110 is further provided with another insulating medium layer, the sidewall of the through trench ST may be covered by the other insulating medium layer, and the first isolation trench S1 may be formed on the surface 160' of the insulating stack structure 160 away from the substrate 110. Further exemplarily, when there is no other insulating medium layer on the side of the insulating medium layer having the through trench ST away from the substrate 110, the through trench ST may be at least a part (e.g., a part; e.g., all) of the first isolation trench S1, or it may be said that the through trench ST forms the first isolation trench ST.

With continued reference to fig. 4, when the insulating medium layer has one or more through grooves ST, the light transmittance of the insulating medium layer at the through grooves ST is higher because the through grooves ST penetrate the insulating medium layer, as compared to when the insulating medium layer has grooves that do not penetrate the insulating medium layer. For this reason, the insulating medium layer having the plurality of through-grooves ST may be referred to as a transmittance enhancing medium layer. Based on the above, it can also be said that one transmittance enhancement medium layer (for example, each transmittance enhancement medium layer) has a plurality of through grooves ST, and the through grooves ST (for example, each through groove ST) penetrate the transmittance enhancement medium layer in the thickness direction of the display panel 10 (for example, in the direction parallel to the Z axis).

Referring to fig. 4 and based on the above description, in some embodiments, at least one (e.g., one; as another example, a plurality) of the plurality (e.g., all) of the insulating dielectric layers of the insulating stack structure 160 is a transmittance-enhancing dielectric layer. Thus, the light transmittance of the display panel 10 at the first separation grooves S1 may be further improved, and the transparency of the display panel 10 may be further improved.

With continued reference to fig. 4, in some embodiments, among the plurality (e.g., all) of insulating dielectric layers of the insulating stack 160, the insulating dielectric layer closest to the encapsulation layer 170 is a transmittance enhancing dielectric layer. Illustratively, referring to the above description, among a plurality (e.g., all) of the insulating dielectric layers of the insulating stack structure 160, the insulating dielectric layer closest to the encapsulation layer 170 may be the pixel defining layer 163, and the pixel defining layer 163 may be a transmittance enhancing dielectric layer.

When one of the insulating dielectric layers located in the middle of the insulating stacked structure 160 is a transmittance enhancing dielectric layer, the other insulating dielectric layers are disposed on the side of the transmittance enhancing dielectric layer away from the substrate 110, and the other insulating dielectric layers may be organic insulating layers. The material of the organic insulating layer may include an organic material, and thus, similar to the organic encapsulation layer, the organic insulating layer may also be a film having a relatively flat surface and a non-uniform thickness. Based on this, when the organic insulating layer is disposed on the side of the transmittance enhancing medium layer away from the substrate 110, the organic insulating layer may fill part or all of the through groove ST of the transmittance enhancing medium layer, so that the depth of the first isolation groove S1 formed by the through groove ST is smaller, and it can be said that the thickness of the display panel 10 at the first isolation groove S1 may be larger. In contrast, since the insulating medium layer closest to the encapsulation layer 170 is the transmittance enhancement medium layer, the first isolation groove S1 formed by the through groove ST of the transmittance enhancement medium layer may have no other insulating medium layer and only a portion of the encapsulation layer 170 is disposed. In this way, the thickness of the insulation stack structure 160 at the first isolation groove S1 may be smaller, and the light transmittance of the display panel 10 at the first isolation groove S1 may be improved, thereby improving the transparency of the display panel 10.

With continued reference to fig. 4, in other embodiments, of the plurality (e.g., all) of insulating dielectric layers of the insulating stack 160, each of the N consecutive insulating dielectric layers adjacent to the encapsulation layer 170 is a transmittance enhancing dielectric layer, where N is greater than or equal to 2 and less than or equal to the number of insulating dielectric layers in the insulating stack 160.

Furthermore, in the N transmittance enhancement medium layers, two adjacent transmittance enhancement medium layers are a first transmittance enhancement medium layer and a second transmittance enhancement medium layer, the second transmittance enhancement medium layer is located on the side of the first transmittance enhancement medium layer away from the substrate, and a through groove (for example, each through groove) on the first transmittance enhancement medium layer is communicated with a through groove on the second transmittance enhancement medium layer.

Specifically, referring to fig. 4, the second organic insulating layer 162b is taken as a first transmittance enhancing dielectric layer, and the pixel defining layer 163 is taken as a second transmittance enhancing dielectric layer for illustration, it is understood that the other two adjacent insulating dielectric layers may also be the first transmittance enhancing dielectric layer and the second transmittance enhancing dielectric layer. Since the through-groove ST (e.g., each through-groove ST) on the second organic insulating layer 162b is through-connected to the through-groove ST on the pixel defining layer 163, the depth of the first isolation groove S1 formed by the through-groove ST on the second organic insulating layer 162b and the through-groove ST on the pixel defining layer 163 may be large, that is, the thickness of the display panel 10 at the first isolation groove S1 may be small, and the light transmittance of the display panel 10 at the first isolation groove S1 may be improved, thereby improving the transparency of the display panel. In addition, a portion of the second organic insulating layer 162b and a portion of the pixel defining layer 163 may be removed through one etching process (i.e., a single exposure and development process), so that the through-groove ST on the second organic insulating layer 162b and the through-groove ST on the pixel defining layer 163 may be communicated with each other, and thus, compared to removing a portion of the second organic insulating layer 162b and a portion of the pixel defining layer 163, respectively, the manufacturing process of the display panel 10 is simpler, and the yield of the display panel 10 may be improved.

With continued reference to fig. 4, in some possible implementations, the consecutive N insulating medium layers adjacent to the encapsulation layer 170 may be consecutive N of the pixel defining layer 163, the second organic insulating layer 162b, and the first organic insulating layer 162 a. Since the material of each of the first organic insulating layer 162a, the second organic insulating layer 162b, and the pixel defining layer 163 may include PI (polyimide), PI easily causes a problem of yellowing of the film. Based on this, since the N consecutive insulating medium layers in the first organic insulating layer 162a, the second organic insulating layer 162b and the pixel defining layer 163 are transmittance enhancing medium layers, that is, one or more through grooves may be formed in the N consecutive insulating medium layers in the first organic insulating layer 162a, the second organic insulating layer 162b and the pixel defining layer 163, a problem of yellowing of the first organic insulating layer 162a, the second organic insulating layer 162b and the pixel defining layer 163 may be improved, and transparency of the display panel 10 may be improved.

With continued reference to fig. 4, in some embodiments, the orthographic projection of a through slot ST (e.g., each through slot ST) on the first transmittance enhancing dielectric layer onto the substrate 110 is within the orthographic projection of a through slot ST on the second transmittance enhancing dielectric layer onto the substrate 110. Still taking the second organic insulating layer 162b as the first transmittance enhancing medium layer and the pixel defining layer 163 as the second transmittance enhancing medium layer as an example, the orthographic projection of the through groove ST on the second organic insulating layer 162b on the substrate 110 may be located within the orthographic projection of the through groove ST on the pixel defining layer 163 on the substrate 110.

Since the orthographic projection of the through groove ST (for example, each through groove ST) on the first transmittance enhancement medium layer on the substrate 110 is located within the orthographic projection of the through groove ST on the second transmittance enhancement medium layer on the substrate 110, the through grooves ST of consecutive N (for example, all) insulating medium layers may be communicated with each other, and the first isolation groove S1 with the inverted trapezoidal cross section may be formed, and it can be said that, for one side wall of the first isolation groove S1, the side wall of the first isolation groove S1 may be gradually inclined in a direction away from the center of the first isolation groove S1 along the direction (for example, the positive direction of the Z axis) in which the substrate 110 points to the light-emitting device E. As such, the process of forming the first isolation trench S1 on the insulation stack structure 160 may be simple.

With continuing reference to fig. 4 and with reference to the above description, in some embodiments, a plurality of (e.g., all) of the insulating dielectric layers in the insulating stack structure 160 includes a plurality of inorganic insulating layers 161, e.g., including a first inorganic insulating layer 161a, a second inorganic insulating layer 161b, a third inorganic insulating layer 161c, and a fourth inorganic insulating layer 161d, each inorganic insulating layer 161 being an insulating dielectric layer. A plurality of (e.g., all) of the insulating dielectric layers in the insulating stack structure 160 further include at least one (e.g., one; as another example, a plurality of) organic insulating layers 162, including, for example, a first organic insulating layer 162a and a second organic insulating layer 162 b. At least one (e.g., all) of the organic insulating layers 162 are located on a side of the plurality of (e.g., all) of the inorganic insulating layers 161 away from the substrate 110. Each inorganic insulating layer 162 is an insulating dielectric layer. Moreover, a plurality of (e.g., all) insulating medium layers in the insulating stack structure 160 further include a pixel defining layer 163, the pixel defining layer 163 is located on a side of at least one (e.g., all) of the organic insulating layers 162 away from the substrate 110, and the pixel defining layer 163 is an insulating medium layer.

Further, at least one (e.g., one; and, for example, a plurality of) insulating medium layers among the plurality of (e.g., all) inorganic insulating layers 161, the at least one (e.g., all) organic insulating layers 162, and the pixel defining layer 163 described above are transmittance-enhancing medium layers.

Each of the insulating dielectric layers in the insulating stacked structure 160 is a transmittance enhancement dielectric layer, and further, a through groove in each transmittance enhancement dielectric layer may be communicated with through grooves of other respective transmittance enhancement dielectric layers. In this way, the first isolation grooves S1 formed by all the through-holes of the transmittance enhancement medium layer may penetrate through the insulation stack structure 160, and the thickness of the insulation stack structure 160 at the first isolation groove S1 may be smaller, which may further improve the light transmittance of the display panel 10 at the first isolation groove S1, and further improve the transparency of the display panel.

In addition, referring to fig. 2 and 4, since at least one (e.g., one; e.g., a plurality of) first isolation grooves S1 is disposed along the circumference of the sub-display region K, that is, one or more first isolation grooves S1 may be disposed around one sub-display region K, when the encapsulation layer 170 is manufactured, the encapsulation layer 170 may be wrapped along the sub-display region K, for example, the encapsulation layer 170 may cover two side surfaces of the light emitting device E disposed opposite to each other along the X-axis direction and two side surfaces of the light emitting device E disposed opposite to each other along the Y-axis direction, so that the encapsulation effect may be improved, and the lifetime of the display panel 10 may be further improved.

Further, referring to the above description, in some embodiments, the encapsulation layer 170 includes an organic encapsulation layer 173, and a portion of the organic encapsulation layer 173 may be located in the one or more first isolation trenches S1. In this way, in the process of manufacturing the organic encapsulation layer 173, a portion of the organic encapsulation layer material may flow into the one or more first isolation grooves S1, so that less organic encapsulation layer material may extend to the peripheral region SA, and the size of the bezel of the display panel 10 may be reduced.

Fig. 12 is a cross-sectional view of the display panel in fig. 8 along a section line BB'. Referring to fig. 8 to 12, in some embodiments, the insulation stack structure 160 further includes a plurality of first partition walls W1. At least one (e.g., one; as another example, a plurality of) first partition walls W1 are disposed along a circumferential direction of a sub-display section K. It can also be said that at least one (e.g., one; as another example, a plurality of) first partition walls W1 are provided around (including both sides in the X-axis direction and both sides in the Y-axis direction) a sub-display section K (e.g., each sub-display section K).

Further, for a sub-display section K (e.g., each sub-display section K), at least one (e.g., all) of the first partition walls W1 disposed in the circumferential direction of the sub-display section K are located on a side of at least one (e.g., all) of the first partition grooves S1 disposed in the circumferential direction of the sub-display section K away from the sub-display section K. Also, at least one (e.g., all) of the first partition walls W1 disposed in the circumferential direction of the sub display section K are used to form the sidewalls S1' of at least one (e.g., all) of the first partition grooves S1 disposed in the circumferential direction of the sub display section K.

Referring to fig. 9, in some embodiments, a plurality of first partition walls W1 are disposed around a sub-display section K (e.g., each sub-display section K). Illustratively, four first partition walls W1 are disposed around one sub-display region K, wherein each first partition wall W1 may be a long-strip-shaped wall extending in the X-axis direction or the Y-axis direction and disposed at one side of the sub-display region K (e.g., one side in the X-axis direction or one side in the Y-axis direction).

Referring to fig. 10 and 11, in other embodiments, a first partition wall W1 is disposed around a sub-display region K (e.g., each sub-display region K), and the first partition wall W1 surrounds the sub-display region K.

Based on the above, since the at least one first partition wall W1 is disposed along the circumferential direction of a sub-display region K, that is, for a sub-display region K (e.g., each sub-display region K), at least one first partition wall W1 is disposed around the sub-display region K, and the at least one first partition wall W1 around the sub-display region K may be used to form the side wall of the at least one first partition groove S1 around the sub-display region K. Based on this, by removing a portion of one or more insulating dielectric layers in the insulating stack structure 160, a plurality of first isolation trenches S1 and a plurality of first isolation walls W1 may be simultaneously formed. Thus, the manufacturing process of the display panel 10 can be simple.

In addition, referring to fig. 8 and 10, since at least one first partition wall W1 is disposed around one sub-display region K (e.g., each sub-display region K), two first partition walls W1 may be disposed between two adjacent sub-display regions K. The two first partition walls W1 may be formed by removing a portion of one or more insulating dielectric layers in the insulating stack structure 160. In view of the above, in addition to the formation of the two first partition walls W1, a groove may be formed between the two first partition walls W1, and a side wall of the groove may be formed by the two first partition walls W1. In this way, the surface of the insulating stack structure 160 away from the substrate 110 may have more grooves, which may further improve the transparency of the display panel. In addition, a portion of the organic encapsulation layer 173 may be located in the groove, that is, in the process of manufacturing the organic encapsulation layer, the organic encapsulation layer material may also flow into the groove, so that the encapsulation effect may be further improved, and the frame size of the display panel 10 may also be further reduced.

Referring to fig. 12, in some embodiments, the first partition wall W1 includes a first partition pattern W1a and a second partition pattern W1b sequentially arranged in a direction away from the substrate 110 (e.g., a positive Z-axis direction). Illustratively, the second isolation pattern W1b is located on a side of the first isolation pattern W1a away from the substrate 110, and the first isolation pattern W1a and the second isolation pattern W1b are in contact.

It should be noted that, herein, an orthographic projection of a pattern (e.g., the first isolation pattern W1a or the second isolation pattern W1b) on the substrate 110 may have a closed outer contour.

In some possible implementations, the first isolation patterns W1a may be included in an insulating medium layer (hereinafter referred to as a first insulating medium layer for distinction), that is, the material of the first isolation patterns W1a is the same as the material of the first insulating medium layer, and the thickness (e.g., a dimension in the Z-axis direction) of the first isolation patterns W1a is substantially the same as the thickness (e.g., a dimension in the Z-axis direction) of the first insulating medium layer. Similarly, the second isolation patterns W1b may be included in another insulating medium layer (hereinafter, referred to as a second insulating medium layer for distinction), that is, the material of the second isolation patterns W1b is the same as the material of the second insulating medium layer, and the thickness (e.g., a dimension in the Z-axis direction) of the second isolation patterns W1b is substantially the same as the thickness (e.g., a dimension in the Z-axis direction) of the second insulating medium layer. The second insulating dielectric layer may be located on a side of the first insulating dielectric layer away from the substrate 110, and the second insulating dielectric layer may be in contact with the first insulating dielectric layer.

Further, an orthographic projection of the second isolation pattern W1b on the substrate 110 is located inward of an orthographic projection of the first isolation pattern W1a on the substrate 110. Thus, the first partition wall W1 may have a relatively stable structure. Also, the manufacturing process of the first partition wall W1 may be relatively simple. For example, the first isolation pattern W1a and the second isolation pattern W1b may be formed by removing a portion of the first insulating medium layer and the second insulating medium layer through a single etching process (i.e., a single exposure and development process), so that the orthographic projection of the second isolation pattern W1b on the substrate 110 is located within the orthographic projection of the first isolation pattern W1a on the substrate 110, and thus, the manufacturing process of the first isolation wall W1 may be simpler.

Fig. 13 is a partially enlarged view of a region Q5 in the display panel of fig. 2. Fig. 14 is a sectional view of the display panel of fig. 13 taken along a sectional line CC'. Fig. 15 is a partially enlarged view of a region Q6 in the display panel of fig. 6.

Referring to fig. 13 to 15, in some embodiments, the insulation stack structure 160 includes a plurality of second partition walls W2. Each of the second partition walls W2 is positioned between adjacent two of the sub-display sections K. For example, a portion of the insulation stack structure 160 between two adjacent sub-display regions K may form a second partition wall W2. For example, for two adjacent sub-display sections K, a portion of the insulation stack structure 160 located between the two sub-display sections K may form a second partition wall W2, and the size of the second partition wall W2 is smaller than or equal to the size of each of the two sub-display sections K in a direction perpendicular to the arrangement direction of the two sub-display sections K.

Further, a plurality of (e.g., all) second partition walls W2 IN the insulation stack structure 160 extend to form an isolation mesh IN. Illustratively, each of a plurality of (e.g., all) second partition walls W2 IN the insulation stack structure 160 may extend IN the X-axis direction or the Y-axis direction, forming an isolation mesh IN. The isolation mesh IN may isolate all the first isolation grooves S1 surrounding different sub display regions K. For example, for a sub-display section K (e.g., each sub-display section K), the isolation mesh IN may form a sidewall of each of at least one (e.g., all) of the first isolation grooves S1 surrounding the sub-display section K.

With continued reference to fig. 13 to 15, since the display panel 10 includes the isolation mesh IN, the structural stability of the display panel 10 may be better, so that the display panel 10 may have better capability of resisting an external force.

FIG. 16 is a top view of a display panel according to some embodiments. It should be noted that, for simplicity of the drawings, fig. 16 only shows a plurality of sub-display regions and electrode layers, and other structures, for example, a plurality of first isolation trenches, are omitted.

Referring to fig. 4 and 16, and referring to the above description, the display panel 10 may include an electrode layer 132, which may be the second electrode layer described above. In some embodiments, the second electrode layer 132 may include a plurality of electrode patterns EP disposed to be spaced apart from each other. An electrode pattern EP (e.g., each electrode pattern EP) covers at least a partial (e.g., a portion; e.g., all) area of a sub-display region K.

It should be noted that, in this context, an orthographic projection of a pattern (e.g., an electrode pattern or a light-emitting functional pattern) on a substrate may have a closed outer contour.

In some possible implementations, an electrode pattern EP (e.g., each electrode pattern EP) covers a portion of a sub-display region K. Illustratively, an electrode pattern EP may cover a portion of the sub-pixel regions in a sub-display region K. For example, an electrode pattern EP may cover one sub-pixel region in one sub-display region K. For another example, an electrode pattern EP may cover a part of sub-pixel regions in a sub-display region K, the number of the part of sub-pixel regions being half of the number of all sub-pixel regions in the sub-display region K. In other possible implementations, an electrode pattern EP (e.g., each electrode pattern EP) may cover all of a sub-display area K, or an electrode pattern EP (e.g., each electrode pattern EP) may cover all of sub-pixel areas in a sub-display area K.

Based on the above, for a sub-display section K, the electrode patterns EP (e.g., each electrode pattern EP) covering the sub-display section K may include the second electrodes of at least one (e.g., one; and as another example, all) of the light emitting devices located in the sub-display section K. It can also be said that in one sub-display region K, the second electrodes of a plurality of (e.g., all) light emitting devices may be connected to each other to form one electrode pattern EP.

In the related art, the second electrode layer in the display panel may be a continuous film layer covering the display area of the display panel. The continuous film layer may cause a reduction in light transmittance of the display panel, affecting the transparency of the display panel. In contrast, referring to fig. 16, in the display panel 10, since the plurality of electrode patterns EP in the second electrode layer 132 are disposed at intervals from each other, the light transmittance of the display panel 10 may be high, and the transparency of the display panel 10 may be improved.

Referring to fig. 4 and 16, in some embodiments, the display panel 10 further includes a plurality of signal lines 180. A plurality of (e.g., all) signal lines 180 are disposed in the display area AA and on a side of the second electrode layer 132 close to the substrate 110. Illustratively, a plurality of (e.g., all) signal lines 180 may be included in one conductor layer 150. In some possible implementations, a signal line 180 (e.g., each signal line 180) may extend along the X-axis direction, in which case, the signal line 180 may be included in the third conductor layer 153 or the fourth conductor layer 154, and the signal line 180 may be parallel or substantially parallel to other signal lines in the third conductor layer 153 or the fourth conductor layer 154.

Further, referring to fig. 16, each electrode pattern EP is coupled to one signal line 180. Illustratively, a plurality of electrode patterns EP corresponding to a row of the sub-display sections K in the display panel 10 may be coupled to one signal line 180. In this way, an electric signal can be written to the second electrodes of a plurality of (e.g., all) light emitting devices corresponding to one row of the sub display region K through one signal line 180.

Fig. 17 is a structural view of an electrode pattern and a signal line, showing a coupling manner of the electrode pattern and the signal line. Referring to fig. 17, the display panel may further include a plurality of connection patterns CP, and a plurality of (e.g., all) connection patterns CP may be included in the first electrode layer 131, or it can be said that the plurality of (e.g., all) connection patterns CP are disposed in the same layer as the first electrodes of the plurality of light emitting devices. An electrode pattern EP (e.g., each electrode pattern EP) may be in contact with the connection pattern CP, and the connection pattern CP may be in contact with the signal line 180, so that the electrode pattern EP may be coupled to the signal line 180.

With continued reference to fig. 16, in some possible implementations, a plurality of (e.g., all) signal lines 180 in the display panel 10 may be coupled to each other, for example, the display panel 10 further includes a connection line 190 disposed in the peripheral region SA, the connection line 190 may be coupled to the plurality of (e.g., all) signal lines 180 in the display panel 10, and the plurality of (e.g., all) signal lines 180 in the display panel 10 may be coupled to each other. The electrical signals may be transmitted to the plurality of signal lines 180 through the connection line 190, so that the second electrodes of a plurality of (e.g., all) light emitting devices in the display panel 10 may write the same electrical signal.

With continued reference to fig. 16, in some possible implementations, the data driving circuit 210 may be disposed at a side of the display panel 10, for example, a side of the display panel 10 along the X-axis direction. The connecting lines 190 may be located in the peripheral region SA of the display panel 10 and located at a side of the display area AA close to the data driving circuit 210.

In addition, in the related art, the second electrodes of all the light emitting devices in the display panel may be connected to each other to form a continuous film layer. In addition, in order to write the electrical signals into the continuous film, connecting lines may be disposed around the display area (i.e., the peripheral area) of the display panel, and the continuous film may contact the connecting lines in the peripheral area, so as to write the electrical signals into the continuous film through the connecting lines. In order to ensure the stability of the electrical connection between the continuous film and the connection lines, the width of the connection lines coupled to the continuous film may be large, which may result in a large bezel size of the display panel. In contrast, referring to fig. 16, in the display panel 10, since the display panel 10 includes the plurality of signal lines 180, the plurality of electrode patterns EP may be coupled to the plurality of signal lines 180 in the display area AA, so that the connection line having a large width may not be disposed in the peripheral area SA of the display panel 10, and the bezel size of the display panel 10 may be reduced.

Fig. 18A is a top view of a display panel according to some embodiments. Fig. 18B is a cross-sectional view of the display panel in fig. 18A along a section line DD'. It should be noted that, for simplicity of the drawings, only a plurality of sub-display regions and a light emitting function layer are shown in fig. 18A, and other structures, such as other light emitting function layers and a plurality of first isolation grooves, are omitted.

Referring to fig. 18A and 18B, and referring to the above description, the display panel 10 may include one or more light emitting functional layers 134. One or more light emitting functional layers 134 may be located on a side of the insulating stack 160 away from the substrate 110. In some embodiments, a light-emitting function layer 134 (e.g., each light-emitting function layer 134) includes a plurality of light-emitting function patterns FP disposed at intervals, and a light-emitting function pattern FP (e.g., each light-emitting function pattern FP) covers at least a partial (e.g., a portion; e.g., all) area of a sub-display region K.

The relationship between a light-emitting functional pattern FP and a sub-display region K can refer to the above description about the relationship between an electrode pattern and a sub-display region, and is not repeated herein. Further, referring to the above description, the pixel defining layer 163 may have a plurality of openings H, and an opening H may be opposite to a sub-pixel region. Based on this, it can also be said that a light emitting function pattern FP can cover one or more openings H.

Similarly to the second electrode layer, since the plurality of light emitting function patterns FP in the light emitting function layer 134 are disposed at intervals from each other, the light transmittance of the display panel 10 may be high, and the transparency of the display panel 10 may be improved.

Fig. 19 is a top view of a display panel according to some embodiments, and fig. 20 is a cross-sectional view of the display panel in fig. 19 along a section line EE'. It should be noted that, for simplicity of the drawings, only one second isolation trench is shown in fig. 19, and one or more insulating dielectric layers in the insulating stack structure are omitted in fig. 20.

Referring to fig. 19 and 20, in some embodiments, in the display panel 10, the surface of the insulation stack structure 160 away from the substrate 110 further has at least one (e.g., one; e.g., a plurality of) second isolation grooves S2. At least one (e.g., all) of the second separating grooves S2 are disposed along the circumferential direction of the display area AA. It can also be said that at least one second separating groove S2 is provided around the display area AA (including, for example, both sides in the X-axis direction and both sides in the Y-axis direction). In some possible implementations, a second isolation groove S2 (e.g., each second isolation groove S2) surrounds the display area AA.

Further, the encapsulation layer 170 may extend to the second isolation groove S2, and a portion of the encapsulation layer 170 is located in at least one (e.g., one; as another example, a plurality) of the second isolation grooves S2.

Based on the above, in the process of fabricating the organic encapsulation layer 173, the organic encapsulation layer material may flow into the second isolation groove S2. Thus, the packaging effect can be improved, and the frame size of the display panel 10 can be further reduced.

With continued reference to fig. 19 and 20, in some embodiments, the display panel 10 further includes a retaining wall BW. The retaining wall BW may be disposed on a side of the insulation stack structure 160 away from the substrate 110, and on a side of at least one (e.g., all) of the second isolation trenches S2 away from the display area AA. The retaining wall BW may surround the display area AA. The material of the retaining wall BW may include Polystyrene (which may be referred to as PS for short).

Further, the encapsulating layer 170 may extend to the retaining wall BW, and the encapsulating layer 170 may cover the retaining wall BW.

Based on the above, the retaining wall BW may be configured to block the organic encapsulation layer 173 in the region enclosed by the retaining wall BW, and further extension of the organic encapsulation layer 173 towards the direction of the retaining wall BW away from the display area AA may be reduced. Thus, the packaging effect can be improved, and the frame size of the display panel 10 can be further reduced.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A display panel is characterized in that a plurality of pixels are arranged in a matrix,

the display device comprises a display area, a plurality of display sub-areas and a plurality of pixel sub-areas, wherein the display sub-areas are distributed at intervals;

the display panel includes:

a substrate;

the insulating stacked structure comprises a plurality of insulating medium layers which are stacked on the substrate, a plurality of first isolation grooves are formed in the surface, far away from the substrate, of the insulating stacked structure, and at least one first isolation groove is arranged along the circumferential direction of the sub-display area;

and the packaging layer is arranged on one side of the insulation stacking structure far away from the substrate, and a part of the packaging layer is positioned in the first isolation grooves.

2. The display panel according to claim 1,

at least one of the plurality of insulating medium layers is a transmittance enhancement medium layer;

the transmittance enhancement medium layer is provided with a plurality of through grooves, a through groove penetrates through the transmittance enhancement medium layer along the thickness direction of the display panel, and the through grooves are used for forming a first isolation groove.

3. The display panel according to claim 2,

among the plurality of insulating medium layers, the insulating medium layer closest to the packaging layer is the transmittance enhancement medium layer;

or,

in the plurality of insulating medium layers, each of the N continuous insulating medium layers close to the packaging layer is the transmittance enhancement medium layer; the two adjacent transmittance enhancement medium layers are a first transmittance enhancement medium layer and a second transmittance enhancement medium layer, and the second transmittance enhancement medium layer is positioned on one side, far away from the substrate, of the first transmittance enhancement medium layer; a through groove on the first transmittance enhancement medium layer is communicated with a through groove on the second transmittance enhancement medium layer; and N is greater than or equal to 2 and less than or equal to the number of insulating medium layers in the insulating stacked structure.

4. The display panel according to claim 3,

the orthographic projection of a through groove on the first transmittance enhancement medium layer on the substrate is positioned within the orthographic projection of a through groove on the second transmittance enhancement medium layer on the substrate.

5. The display panel according to any one of claims 2 to 4,

the plurality of insulating dielectric layers include:

a plurality of inorganic insulating layers, each inorganic insulating layer being an insulating dielectric layer;

the organic insulating layers are positioned on one sides of the inorganic insulating layers far away from the substrate, and each organic insulating layer is an insulating medium layer;

the pixel defining layer is positioned on one side, far away from the substrate, of the at least one organic insulating layer, and is an insulating medium layer;

at least one of the plurality of inorganic insulating layers, the at least one organic insulating layer and the pixel defining layer is a transmittance enhancing dielectric layer.

6. The display panel according to claim 1,

the insulating stacked structure further comprises a plurality of first isolation walls, at least one first isolation wall is arranged along the circumferential direction of the sub-display area, is positioned on one side of the at least one first isolation groove far away from the sub-display area, and is used for forming a side wall of the at least one first isolation groove; or,

the insulating stacked structure further comprises a plurality of second isolation walls, each second isolation wall is located between two adjacent sub-display areas, the second isolation walls extend to form an isolation net, and the isolation nets separate the first isolation grooves surrounding different sub-display areas.

7. The display panel according to claim 6,

the first isolation wall comprises a first isolation pattern and a second isolation pattern which are sequentially arranged along the direction far away from the substrate, and the orthographic projection of the second isolation pattern on the substrate is positioned within the orthographic projection of the first isolation pattern on the substrate.

8. The display panel according to claim 1, further comprising:

and the electrode layer is positioned on one side of the insulating stacked structure far away from the substrate and comprises a plurality of electrode patterns which are arranged at intervals, and one electrode pattern covers at least partial area of one sub-display area.

9. The display panel according to claim 8, characterized by further comprising:

and the plurality of signal lines are arranged in the display area and arranged on one side of the electrode layer close to the substrate, and each electrode pattern is coupled with one signal line.

10. The display panel according to claim 1, further comprising:

the light-emitting functional layer is positioned on one side, far away from the substrate, of the insulating stacked structure and comprises a plurality of light-emitting functional patterns which are arranged at intervals, and the light-emitting functional patterns cover at least partial area of a sub-display area.

11. The display panel according to claim 1,

the encapsulation layer includes an organic encapsulation layer, and a portion of the organic encapsulation layer is located in the first isolation groove.

12. The display panel according to claim 1,

the surface of the insulation stacking structure far away from the substrate is also provided with at least one second isolation groove which is arranged along the circumferential direction of the display area;

a portion of the encapsulation layer is located in the at least one second isolation trench.

13. The display panel according to claim 12, further comprising:

the retaining wall is arranged on one side, far away from the substrate, of the insulation stacking structure and is arranged on one side, far away from the display area, of the at least one second isolation groove, and the retaining wall surrounds the display area;

the packaging layer covers the retaining wall.

14. A display device comprising the display panel according to any one of claims 1 to 13.