CN216905094U - 8K ultra-high definition video encoder with multiple output preview interfaces - Google Patents
8K ultra-high definition video encoder with multiple output preview interfaces Download PDFInfo
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Abstract
The utility model relates to the technical field of coding systems, in particular to an 8K ultra-high definition video coder with multiple output preview interfaces, which supports SDI-12Gx4 input, HDMI2.0x4 input and HDMI2.1x1 input, can convert signals into HDMI2.1, SDI-12G or HDMI2.0 signals, has multiple 8K video interface outputs, can simultaneously support the three 8K video preview output interfaces, can output one of the converted signals from HDMI2.1x1, HDMI2.0x4 or SDI-12Gx4 transmission modules in three ways, does not need additional converters and wires, reduces the cost, and has the input and output image resolution ratio reaching 8kP 60; the device can also reduce the output resolution through the image resolution reduction module to adapt to a 4K screen, and an additional instrument is not needed to reduce the resolution.
Description
Technical Field
The utility model relates to the technical field of coding systems, in particular to an 8K ultra-high definition video coder with a multi-output preview interface.
Background
Currently, a mainstream 8K ultra-high definition video interface has SDI-12G and needs four sets of SDIs; the other is HDMI2.0, which requires four groups; plus HDMI2.1, only one set is needed. However, there is no 8K ultra high definition video encoder in the market that can simultaneously support the three 8K video preview output interfaces, and if the preview screen does not support the preview output interface of the encoder or the encoder does not support the preview output, an additional converter and wires are required, which increases the additional cost. Also, in the case where the 8K screen is not popular at present, if the encoder can output only 8K resolution, in this case, an additional instrument is required to reduce the resolution so that the input signal can be smoothly monitored.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problems, the present invention provides an 8K ultra high definition video encoder with multiple output preview interfaces.
The technical scheme adopted by the utility model for solving the technical problem is as follows: an 8K ultra-high definition video encoder with a multi-output preview interface comprises a signal receiver, an image processor, an image converter and a video encoder which are connected in sequence;
the signal receiver can receive SDI-12G and HDMI signals and transmit the received signals to the image processor;
the image processor is used for processing and converting the SDI-12G signal and the HDMI signal transmitted by the receiving signal receiver, realizing the mutual conversion of the SDI-12G signal and the HDMI signal, and forming and outputting the SDI-12G signal, the HDMI2.0 signal and a plurality of SDI-3G signals according to the needs of users; the image processor can output the SDI-3G signal obtained after the processing and conversion to the image converter;
the image converter is used for processing and converting the multiple SDI-3G signals transmitted by the image processor to form compatible signals compatible with the video encoder and transmitting the compatible signals to the video encoder;
the video encoder is used for receiving and processing the compatible signal provided by the image converter, and performing video encoding according to the HEVC specification to output through a GbE interface.
Further, the image processor is a first FPGA processor.
Further, the image converter is a second FPGA processor.
Further, the video encoder is an ASIC processor.
Further, the signal receiver comprises an SDI-12Gx4 connector, an HDMI2.0x4 connector and an HDMI2.1x1 connector; the SDI-12G x4 connector is used for receiving signals of 8K camera input or other video input sources of SDI-12G; the HDMI2.1x1 connector and the HDMI2.0x4 connector are both used to receive video input sources for HDMI.
Further, the first FPGA processor has a receiving module thereon, the receiving module SDI-12G x4 receiving module, HDMI2.1x1 receiving module and HAMI2.0 x4 receiving module; the SDI-12G x4 receiving module is used for receiving an SDI-12G video input signal transmitted by the SDI-12Gx4 connector; the HDMI2.1x1 receiving module is used for receiving an HDMI video input signal transmitted by the HDMI2.1x1 connector; the HDMI2.0x4 receiving module is used for receiving an HDMI video input signal transmitted by the HDMI2.0x4 connector.
Further, a transmission module is also arranged on the first FPGA processor; the transmission modules comprise an SDI-12G x4 transmission module, an HDMI2.1x1 transmission module, an HDMI2.0x4 transmission module and an SDI-3G x16 output module; the SDI-12G signal formed after being processed or converted by the first FPGA processor can be output through the SDI-12G x4 transmission module; the HDMI2.1 signal formed after the processing or conversion by the first FPGA processor can be output through the HDMI2.1x1 transmission module; the HDMI2.0x4 signal processed or converted by the first FPGA processor can be output through the HDMI2.0x4 transmission module; the multi-channel SDI-3G signals formed after the processing and the conversion of the first FPGA processor can be transmitted to the image converter through the SDI-3G x16 output module.
Further, the first FPGA processor is further provided with an image resolution reduction module, and the image resolution reduction module is used for reducing resolution, so that the SDI-12G signal can be converted into an HDMI2.0 signal.
Further, the first FPGA processor further comprises a DDR4 buffer module, wherein the DDR4 buffer module is capable of buffering SDI-12G signals and HDMI signals transmitted by the receiver.
The utility model has the beneficial effects that:
1. compared with the prior art, the 8K ultra-high definition video encoder with the multi-output preview interface provided by the utility model supports SDI-12Gx4 input, HDMI2.0x4 input and HDMI2.1x1 input, can convert signals into HDMI2.1, SDI-12G or HDMI2.0 signals, has various 8K video interface outputs, can simultaneously support the three 8K video preview output interfaces, can output one of the converted signals from HDMI2.1x1, HDMI2.0x4 or SDI-12Gx4 transmission modules, and can achieve the input and output image resolution of 8kP 60.
2. When video coding is executed, if a local picture is needed at the same time, the technology can provide diversified output interfaces to match with the equipment and the requirements of users. For example, the user only has 8K screen of hdmi2.0x4 input interface, or the actual requirement is to display 8K screen at the same time and to let the user monitor the input signal status.
3. If the user only has a 4K screen, the device can also reduce the output resolution through the image resolution reduction module.
4. Through diversified output preview interface, can directly solve encoder output interface and preview the different unable connection of screen, or the encoder does not support to preview the output interface and causes the problem that can't monitor the input signal, simple and practical need not to be equipped with extra device or wire rod.
Drawings
FIG. 1 is a schematic diagram of an overall structure of an encoder according to the present invention;
FIG. 2 is a schematic diagram of a first FPGA processor;
FIG. 3 is a schematic diagram of a signal receiver;
FIG. 4 is a schematic diagram of a signal processing structure in the prior art;
FIG. 5 is a schematic diagram of the signal processing structure of the present apparatus;
FIG. 6 is a schematic diagram of a signal processing structure in the prior art;
FIG. 7 is a schematic diagram of the signal processing structure of the present apparatus;
FIG. 8 is a diagram illustrating a signal processing structure in the prior art;
FIG. 9 is a schematic diagram of the signal processing structure of the present apparatus;
FIG. 10 is a diagram illustrating a signal processing structure in the prior art;
FIG. 11 is a schematic diagram of the signal processing structure of the present device.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
The utility model provides an 8K ultra-high definition video encoder with a multi-output preview interface, which comprises a signal receiver, an image processor, an image converter and a video encoder which are sequentially connected.
The signal receiver can receive external SDI-12G and HDMI signals and output the signals to the image processor for processing. The signal receiver comprises an SDI-12Gx4 connector, an HDMI2.0x4 connector and an HDMI2.1x1 connector. The SDI-12Gx4 connector is used to receive signals from 8K camera input or other SDI-12G video input source, and the HDMI2.1x1 and HDMI2.0x4 connectors are used to receive HDMI video input source.
The image processor is a first FPGA (Field Programmable Gate Array) capable of receiving SDI-12G and HDMI signals transmitted from the signal receiver and processing and converting the received SDI-12G and HDMI signals.
The first FPGA processor is provided with a receiving module and a transmitting module. The receiving module is used for receiving the signal transmitted by the signal receiver. The receiving module comprises an SDI-12G x4 receiving module, an HDMI2.1x1 receiving module and a HAMI2.0 x4 receiving module. The SDI-12G x4 receiving module is used for receiving an SDI-12G video input signal transmitted by the SDI-12G x4 connector; the HDMI2.1x1 receiving module is used for receiving an HDMI video input signal transmitted by the HDMI2.1x1 connector; the HDMI2.0x4 receiving module is used for receiving an HDMI video input signal transmitted by the HDMI2.0x4 connector.
The transmission module comprises an SDI-12G x4 transmission module, an HDMI2.1x1 transmission module, an HDMI2.0x4 transmission module and an SDI-3G x16 output module to form diversified signal output interfaces, so that the processed or converted SDI-12G signal, HDMI2.1 signal, HDMI2.0 signal or SDI-3G signal are output through the corresponding interfaces respectively.
The first FPGA processor can realize mutual conversion of the SDI-12G signal and the HDMI signal received by the receiving module so as to convert the SDI-12G signal and the HDMI signal into a required HDMI2.1 signal, a required HDMI2.0 signal, a required SDI-12G signal or a plurality of paths of SDI-3G signals according to user requirements. The HDMI2.1 signal formed after processing or conversion can be output through the HDMI2.1x1 transmission module; the processed or converted HDMI2.0x4 signal can be output through the HDMI2.0x4 transmission module; the processed or converted SDI-12G signal can be output through the SDI-12G x4 transmission module; the processed and converted multiple SDI-3G signals can be transmitted to the image converter through the SDI-3G x16 output module.
The image converter is a second FPGA processor, which is used for receiving the multi-path SDI-3G signal provided by the SDI-3G x16 output module in the first FPGA processor, converting the multi-path SDI-3G signal into a compatible signal compatible with the video encoder, and transmitting the compatible signal to the video encoder.
The video encoder is an ASIC processor and is used for receiving the compatible signal provided by the second FPGA processor, performing video encoding according to the HEVC specification and outputting through a GbE interface.
The SDI-12G receiving module is in transmission connection with the first FPGA processor through a Cable Equalizer (Adaptive Cable Equalizer), and the Cable Equalizer can equalize and amplify an SDI-12G signal transmitted by the SDI-12G x4 receiving module.
The first FPGA processor further comprises a DDR4 cache module, and the DDR4 cache module can cache the video input signals received by the receiving module. Therefore, the video input signal received by the first FPGA processor can buffer a copy of image data in the DDR4 buffer module, and then can be output through the SDI-12G x4 transmitter module, the HDMI2.1x1 transmitter module, or the HDMI2.0x4 transmitter module.
The first FPGA processor further includes an image resolution reduction module, and the image resolution reduction module is used when the external preview screen does not support 8K resolution, for example, when only 4K resolution is supported, so that after the first FPGA processor converts the SDI-12G signal into HDMI2.1, the HDMI2.0 signal can be formed through processing by the image resolution reduction module, and the formed HDMI2.0 signal is output by the HDMI2.0x4 transmission module. If the resolution is required to be reduced, the module is turned on, and if the resolution is not required, the module is turned off.
In the prior art, when the external 8K video input source interface is HDMI2.1, a local screen is needed, and a converter is needed to copy another signal source to output to the 8K screen, that is, the state shown in fig. 3 is presented. The video encoder provided by the present invention can directly output to the 8K screen by using the HDMI2.1x1 transmission module of the encoder system itself, as shown in fig. 4.
In the prior art, when the external 8K video input source interface is SDI-12G, a local screen is required, but the preview screen is HDMI2.1 interface, so a converter (converter) is required to copy and change the output interface to output another signal source to the 8K screen, that is, the state shown in fig. 5 is presented. The video encoder provided by the present invention can directly convert the SDI-12G signal into the HDMI2.1 signal as shown in fig. 6, and then directly output the HDMI2.1x1 signal to the 8K screen by using the HDMI2.1x1 transmission module of the encoder itself.
In the prior art, when the external 8K video input source interface is SDI-12G, a local screen is required, but the preview screen only supports the HDMI2.0 interface and cannot support an 8K resolution image, so a converter and an image size reducer (converter/Scaler) are required to copy/change the output interface and reduce the image resolution to output another signal source to the 4K screen, which is shown in fig. 7. As shown in fig. 8, the video encoder of the present invention can convert the SDI-12G signal into an HDMI2.0 signal by the video resolution reduction module, and then output the HDMI2.0x4 signal to the 4K screen by the HDMI2.0x4 transmission module of the encoder itself.
In the prior art, the external 8K video input source interface is SDI-12G, which requires a local preview screen and also needs to display 8K pictures on site, so a converter \ copier and a reducer are needed to output two signal sources to the 8K screen and the 4K screen, respectively, and the state shown in fig. 9 is presented. As shown in fig. 8, the video encoder of the present invention can convert SDI-12G signals into HDMI2.1 signals and HDMI2.0 signals, and then directly output the HDMI2.0 signals to the 4K screen by using the HDMI2.0x4 transmission module of the encoder itself, and output the HDMI2.1 signals to the 8K screen by using the HDMI2.1x1 transmission module.
The above embodiments are only specific examples of the present invention, and the protection scope of the present invention includes but is not limited to the product forms and styles of the above embodiments, and any suitable changes or modifications made by those skilled in the art according to the claims of the present invention shall fall within the protection scope of the present invention.
Claims (9)
1. An 8K ultra high definition video encoder with multiple output preview interfaces, comprising: comprises a signal receiver, an image processor, an image converter and a video encoder which are connected in sequence;
the signal receiver can receive SDI-12G and HDMI signals and transmit the received signals to the image processor;
the image processor is used for processing and converting the SDI-12G signal and the HDMI signal transmitted by the receiving signal receiver, realizing the mutual conversion of the SDI-12G signal and the HDMI signal, and forming and outputting the SDI-12G signal, the HDMI2.0 signal, the HDMI2.1 signal and a plurality of SDI-3G signals according to the needs of users; the image processor can output the SDI-3G signal obtained after the processing and conversion to the image converter;
the image converter is used for processing and converting the multiple SDI-3G signals transmitted by the image processor to form compatible signals compatible with the video encoder and transmitting the compatible signals to the video encoder;
the video encoder is used for receiving and processing the compatible signal provided by the image converter, performing video encoding according to the HEVC specification and outputting the video encoded through a GbE interface.
2. The 8K ultra high definition video encoder of a multi-output preview interface of claim 1, wherein: the image processor is a first FPGA processor.
3. The 8K ultra high definition video encoder of a multi-output preview interface of claim 1, wherein: the image converter is a second FPGA processor.
4. The 8K ultra high definition video encoder of a multi-output preview interface of claim 1, wherein: the video encoder is an ASIC processor.
5. The 8K ultra high definition video encoder of a multi-output preview interface of claim 1, wherein: the signal receiver comprises an SDI-12Gx4 connector, an HDMI2.0x4 connector and an HDMI2.1x1 connector; the SDI-12G x4 connector is used for receiving signals of 8K camera input or other video input sources of SDI-12G; the HDMI2.1x1 connector and the HDMI2.0x4 connector are both used to receive video input sources for HDMI.
6. The 8K ultra high definition video encoder of a multi-output preview interface of claim 2, wherein: the first FPGA processor is provided with receiving modules, and the receiving modules comprise an SDI-12G x4 receiving module, an HDMI2.1x1 receiving module and a HAMI2.0 x4 receiving module; the SDI-12G x4 receiving module is used for receiving an SDI-12G video input signal transmitted by the SDI-12G x4 connector; the HDMI2.1x1 receiving module is used for receiving an HDMI video input signal transmitted by the HDMI2.1x1 connector; the HDMI2.0x4 receiving module is used for receiving an HDMI video input signal transmitted by the HDMI2.0x4 connector.
7. The 8K ultra high definition video encoder of a multi-output preview interface of claim 6, wherein: the first FPGA processor is also provided with a transmission module; the transmission modules comprise an SDI-12G x4 transmission module, an HDMI2.1x1 transmission module, an HDMI2.0x4 transmission module and an SDI-3G x16 output module; the SDI-12G signal formed after being processed by the first FPGA processor can be output through the SDI-12G x4 transmission module; the HDMI2.1 signal formed after being processed by the first FPGA processor can be output through the HDMI2.1x1 transmission module; the HDMI2.0x4 signal processed by the first FPGA processor can be output through the HDMI2.0x4 transmission module; the multi-channel SDI-3G signals formed after the processing and the conversion of the first FPGA processor can be transmitted to the image converter through the SDI-3G x16 output module.
8. The 8K ultra high definition video encoder of a multi-output preview interface of claim 2, wherein: the first FPGA processor is also provided with an image resolution reduction module, and the image resolution reduction module is used for reducing the resolution, so that the SDI-12G signal can be converted into an HDMI2.0 signal.
9. The 8K ultra high definition video encoder of a multi-output preview interface of claim 7, wherein: the first FPGA processor further comprises a DDR4 cache module, wherein the DDR4 cache module is capable of caching the SDI-12G signal and the HDMI signal transmitted by the receiving signal receiver.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116132615A (en) * | 2023-01-14 | 2023-05-16 | 北京流金岁月传媒科技股份有限公司 | Conversion method and device for ultrahigh-definition 8K HDMI2.1 to 4x12G-SDI |
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2021
- 2021-11-17 CN CN202122820079.0U patent/CN216905094U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116132615A (en) * | 2023-01-14 | 2023-05-16 | 北京流金岁月传媒科技股份有限公司 | Conversion method and device for ultrahigh-definition 8K HDMI2.1 to 4x12G-SDI |
| CN116132615B (en) * | 2023-01-14 | 2023-10-20 | 北京流金岁月传媒科技股份有限公司 | Conversion method and device for ultrahigh-definition 8K HDMI2.1 to 4x12G-SDI |
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