CN215934724U - True turn-off circuit of synchronous boosting DC-DC converter - Google Patents
True turn-off circuit of synchronous boosting DC-DC converter Download PDFInfo
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- CN215934724U CN215934724U CN202120780316.2U CN202120780316U CN215934724U CN 215934724 U CN215934724 U CN 215934724U CN 202120780316 U CN202120780316 U CN 202120780316U CN 215934724 U CN215934724 U CN 215934724U
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Abstract
The invention provides a true turn-off circuit of a synchronous boosting DC-DC converter, when the circuit is powered on and enabled to work, and the input voltage is higher than the output voltage, a substrate switching circuit outputs high potential, the switching of a PMOS power tube is not allowed, and the power tube can be normally turned on and turned off; when the circuit is turned off, the potential of the grid end and the substrate of the power PMOS tube is always equal to the highest potential in the circuit, so that the circuit is turned off really. The invention realizes the power supply high potential selection and the substrate switching of the synchronous boosting DC-DC converter circuit by using the same circuit, namely the substrate switching circuit, thereby simplifying the design of the whole circuit; the circuit is ensured not to be latched, and the working reliability of the chip is improved; the circuit can not oscillate due to interference and the like when the input and the output are switched back and forth, and can provide a relatively fixed substrate potential compared with a traditional synchronous boost DC-DC converter circuit.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a synchronous boost DC-DC circuit.
Background
With the rapid development of consumer electronics, the performance requirements of chips in the products are higher and higher. The synchronous boost DC-DC converter circuit is used as a power management product applied to a plurality of products and has the characteristics of high efficiency, high integration level and the like. However, because of the parasitic diode between the substrate of the synchronous rectification PMOS transistor and the source electrode and the drain electrode, the synchronous boost DC-DC converter still has a current path from input to output when the circuit is enabled to be turned off, the circuit cannot be turned off really, and when a load still exists, power consumption always exists; when the output is short-circuited, due to the existence of the parasitic diode of the power PMOS tube, the risk of burning the PMOS power tube and even a chip exists, so that a true turn-off circuit needs to be designed to improve the reliability of the circuit.
Although some true turn-off circuits exist, the design thereof is relatively complex, and the substrate switching circuit and the high potential selection circuit need to be designed separately; if the load changes during the switching process of the high-potential selection circuit, the output voltage is lower than the input voltage, the risk of switching back and forth exists, even the circuit output oscillates, and the reliability of the circuit application is seriously influenced.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a true shutdown circuit of a synchronous boost DC-DC converter.
The technical scheme adopted by the invention for solving the technical problems is as follows:
as shown in fig. 1, the true shutdown circuit of the synchronous boost DC-DC converter includes a substrate switching circuit (back switch), a power transistor driving circuit (Driver), a power stage and peripheral devices; the peripheral device comprises an inductor L, an input capacitor CIN, an output capacitor COUT and a load RL, wherein one end of the inductor L is connected to a chip input end VBAT and is connected to the ground through the input decoupling capacitor CIN; the other end of the inductor L is connected to the drains of the NMOS power tube MN1 and the PMOS power tube MP1, the gates of the NMOS power tube MN1 and the PMOS power tube MP1 are connected to the output of the Driver, the source and the substrate of the NMOS power tube MN1 are grounded, the substrate of the PMOS power tube MP1 is connected to the output VH of the substrate switching circuit through a resistor R1, the drain of the PMOS power tube MP1 is connected to the output VOUT of the chip and is connected to the ground through an output capacitor, one input end of the Driver circuit is connected to the output ENPFET of the substrate switching circuit, the other input end of the Driver circuit is connected to the switch control signal PWM, and the input end of the substrate switching circuit is connected to the input end VBAT and the output end VOUT of the chip.
The substrate switching circuit comprises a hysteresis comparator I0, NOT gates I1, I2, I3, I4 and I5, PMOS tubes MP2 and MP3, a voltage stabilizing capacitor CH and a current limiting resistor R1; a positive input end of the hysteresis comparator I0 is connected to a chip input voltage VBAT and a drain of a PMOS transistor MP2, a negative input end is connected to an output end VOUT of the chip and a drain of a PMOS transistor MP3, an output end of the hysteresis comparator I0 is connected to an input end of a not gate I1, an output end of the not gate I1 is connected to input ends of a not gate I2 and a not gate I5, an output end of the not gate I2 is connected to an input end X of a not gate I3, an output end of the not gate I3 is connected to an input end of a not gate I4 and a gate of a PMOS transistor MP2, an output end of the not gate I4 is connected to a gate of the PMOS transistor MP3, an output end of the not gate I5 is a control signal ENPFET, a source and a substrate of the PMOS transistor MP2 and a source and a substrate of the PMOS transistor MP3 are connected to ground through a capacitor CH and output VH;
the existence of the current-limiting resistor R1 ensures that the electric loop formed by the MP1 parasitic diode and the current-limiting resistors R1 and R2, the inductor L or MP1 parasitic diode and the current-limiting resistors R1, MP2 and MP3 does not generate large current, thereby preventing the circuit from latching; the voltage VH selected by the MP2 and the MP3 is simultaneously used as the power supply of the power tube driving circuit and the substrate switching circuit; the on-resistance of the PMOS tubes MP2 and MP3 enables the voltage drop of MP1 or MP2 to be less than 200mV when the transistors are switched on, so that VH has stronger load carrying capacity, and the PMOS power tube MP1 cannot be switched on by mistake when the drive circuit works.
The hysteresis comparator I0 compares the magnitude of the whole circuit input voltage VBAT and the whole circuit output voltage VOUT, when VBAT is higher than VOUT by about 100mV, the output of the hysteresis comparator controls inverters I1 and I2 to enable MP2 to be turned on and MP3 to be turned off, the internal high power supply VH is equal to VBAT, the substrate of MP1 is also connected to VBAT through R1 and MP2, when the whole circuit output voltage VOUT is higher than the whole circuit input voltage VBAT by about 100mV, the output of the hysteresis comparator I0 controls NOT gates I3 and I4 to enable MP2 to be turned off and MP3 to be turned on, the internal high power supply VH is equal to VOUT, and the substrate VBODY of MP1 is connected to the VOUT port through R1 and MP 3; when the circuit is turned off, the potential of the gate end and the substrate of the power PMOS transistor MP1 is always equal to the highest potential in the circuit, so that the circuit is turned off truly.
As shown in fig. 4, the current limiting resistor R1 may also be composed of several PMOS transistors connected in series in several different ways, and the size of the PMOS transistor in series is determined by the required resistance. The gate terminal G of the PMOS transistor shown in fig. 4 is connected to ground, the a terminal is connected to the source terminals of PM2 and PM3 shown in fig. 1, and the B terminal is connected to the substrate of the power PMOS transistor MP 1.
When the circuit is powered on and enabled to work, and the input voltage VIN is higher than the output voltage VOUT by more than 100mV, the substrate switching circuit outputs ENPFET with high potential, the PMOS power tube is not allowed to be switched, the grid PDRV of the PMOS power tube is fixedly connected to VH, the substrate VBODY of the PMOS power tube MP1 is connected to VBAT through MP2 and R1, and the NMOS power tube can be normally switched on and off; when the output voltage VOUT is higher than the input voltage VIN by more than 100mV, the substrate switching circuit outputs ENPFET at a low level, the PMOS power transistor and the NMOS power transistor operate in a switching mode, and the substrate of the PMOS power transistor MP1 is connected to VOUT through MP3 and R1.
The invention has the advantages that the high potential selection of the power supply of the synchronous boost DC-DC converter circuit and the substrate switching are realized by the same circuit, namely the substrate switching circuit, wherein the selected high potential is used as the power supply of the power tube driving circuit Driver and the substrate switching circuit, except the substrate of the bias power PMOS tube MP1, thereby simplifying the design of the whole circuit; due to the existence of the current limiting resistor R1, the parasitic diode path current of the power PMOS tube MP1 is limited, the circuit is ensured not to be latched, and the working reliability of the chip is improved; in the invention, a certain hysteresis (about 200mV) is designed in the high-voltage selection circuit, so that the circuit can not oscillate due to the switching between input and output caused by factors such as interference and the like; the substrate switching circuit biases the substrate VBODY of the power PMOS transistor MP1 at the higher end of the fixed potential VBAT and VOUT, so that the potential of the substrate end VBODY of the MP1 is basically unchanged, and the substrate switching circuit can provide a relatively fixed substrate potential compared with a traditional synchronous boost DC-DC converter circuit.
Drawings
Fig. 1 is a diagram of a substrate switching circuit and a true shutdown circuit applied to a synchronous boost DC-DC converter of the present invention.
Fig. 2 is a circuit diagram of an embodiment of the substrate switching circuit of the present invention.
FIG. 3 is a current path formed by the substrate parasitic diodes of the synchronous rectification PMOS power tube of the invention.
Fig. 4 is a diagram illustrating an implementation of the current limiting resistor R1 according to the present invention, where fig. 4(a) is a diagram illustrating a first PMOS transistor series connection mode, and fig. 4(b) is a diagram illustrating a second PMOS transistor series connection mode.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
In order to solve the problems that a true turn-off circuit of a synchronous boosting DC-DC converter circuit is too complex and has the risk of switching back and forth, the invention provides the true turn-off circuit of the synchronous boosting DC-DC converter circuit, which realizes the simplified design of the true turn-off circuit, avoids the risk of switching back and forth during the work of the true turn-off circuit, can realize the true turn-off function when the circuit does not work, can realize short-circuit current-limiting protection, and improves the reliability of a chip during the use.
As shown in fig. 1, the true shutdown circuit of the present invention includes a substrate switch circuit (back gate switch), a power transistor Driver circuit (Driver), a power stage and peripheral devices. The peripheral devices include an inductor L, an input capacitor CIN, an output capacitor COUT and a load RL. One end of the inductor L is connected to the input end VBAT of the chip and is connected to the ground through the input decoupling capacitor CIN; the other end of the inductor is connected to the drains of an NMOS power tube MN1 and a PMOS power tube MP1, the gates of the NMOS power tube MN1 and the PMOS power tube MP1 are connected to the output of a Driver, the source of the NMOS power tube MN1 and the substrate are grounded, the substrate of the PMOS power tube MP1 is connected to the output VH of the substrate switching circuit through a resistor R1, the drain of the PMOS power tube MP1 is connected to the output VOUT of the chip and is connected to the ground through an output capacitor, one input end of the Driver is connected to the output ENPFET of the substrate switching circuit, the other input end of the Driver is connected to a switch control signal PWM, and the input end of the substrate switching circuit is connected to the input end VBAT and the output end VOUT of the chip.
As shown in fig. 2, the substrate switching circuit includes a hysteresis comparator I0, not gates I1, I2, I3, I4, I5, PMOS transistors MP2 and MP3, a voltage stabilizing capacitor CH, and a current limiting resistor R1; the positive input end of the hysteresis comparator I0 is connected to the chip input voltage VBAT and the drain of the PMOS transistor MP2, the negative input end is connected to the output end VOUT of the chip and the drain of the PMOS transistor MP3, the output end of the hysteresis comparator I0 is connected to the input end of the not gate I1, the output end of the not gate I1 is connected to the input ends of the not gate I2 and the not gate I5, the output end of the not gate I2 is connected to the input end X of the not gate I3, the output end of the not gate I3 is connected to the input end of the not gate I4 and the gate of the PMOS transistor MP2, the output end of the not gate I4 is connected to the gate of the PMOS transistor MP3, the output end of the not gate I5 is the control signal ENPFET, the source and the substrate of the PMOS transistor MP2 and the source and the substrate of the PMOS transistor MP 35 3 are connected to the ground through the capacitor CH and output VH. The hysteresis comparator I0 compares the magnitude of the whole circuit input voltage VBAT and the whole circuit output voltage VOUT, when VBAT is higher than VOUT by about 100mV, the output of the hysteresis comparator controls inverters I1 and I2 to enable MP2 to be turned on and MP3 to be turned off, the internal high power supply VH is equal to VBAT, the substrate of MP1 is also connected to VBAT through R1 and MP2, when the whole circuit output voltage VOUT is higher than the whole circuit input voltage VBAT by about 100mV, the output of the hysteresis comparator I0 controls NOT gates I3 and I4 to enable MP2 to be turned off and MP3 to be turned on, the internal high power supply VH is equal to VOUT, and the substrate VBODY of MP1 is connected to the VOUT port through R1 and MP 3; therefore, when the circuit is turned off, the potential of the gate end and the substrate of the power PMOS transistor MP1 is always equal to the highest potential in the circuit, so that the circuit is turned off really. The existence of the current-limiting resistor R1 ensures that the electric loop formed by the MP1 parasitic diode and the current-limiting resistors R1 and R2, the inductor L or MP1 parasitic diode and the current-limiting resistors R1, MP2 and MP3 does not generate large current, thereby preventing the circuit from latching; the voltage VH selected by MP2 and MP3 is used as the power source of the power tube driving circuit and the substrate switching circuit. The on-resistance of the PMOS tubes MP2 and MP3 needs to be small, so that the voltage drop is less than 200mV when MP1 or MP2 are switched on, VH has strong loading capacity, and the PMOS power tube MP1 cannot be switched on by mistake when the drive circuit works.
As shown in fig. 3, two current paths ILoop1, ILoop2 may occur in operation due to the presence of a parasitic diode (shown within the dashed box of fig. 3) in the power PMOS transistor MP 1. The current of the current path is limited by the connection of the current limiting resistor R1, and the current of the power PMOS transistor MP1 is ensured to flow through the channel of the power PMOS transistor MP 1.
As shown in fig. 4, the current limiting resistor R1 may also be composed of several PMOS transistors connected in series in several different ways, and the size of the PMOS transistor in series is determined by the required resistance. The gate terminal G of the PMOS transistor shown in fig. 4 is connected to ground, the a terminal is connected to the source terminals of PM2 and PM3 shown in fig. 1, and the B terminal is connected to the substrate of the power PMOS transistor MP 1.
In summary, the present invention provides a true shutdown circuit applied to a synchronous boost DC-DC converter, which finally achieves true shutdown of the synchronous boost converter circuit. Compared with the prior true turn-off circuit, the circuit of the invention is simpler, the current-limiting resistor is added, and the hysteresis function of the high-voltage selection circuit is added, so that the chip has higher reliability in practical application.
Claims (3)
1. A true turn-off circuit of a synchronous boost DC-DC converter comprises a substrate switching circuit, a power tube driving circuit, a power stage and peripheral devices, and is characterized in that:
the peripheral device comprises an inductor L, an input capacitor CIN, an output capacitor COUT and a load RL, wherein one end of the inductor L is connected to a chip input end VBAT and is connected to the ground through the input decoupling capacitor CIN; the other end of the inductor L is connected to the drains of the NMOS power tube MN1 and the PMOS power tube MP1, the gates of the NMOS power tube MN1 and the PMOS power tube MP1 are connected to the output of the Driver, the source of the NMOS power tube MN1 and the substrate are grounded, the substrate of the PMOS power tube MP1 is connected to the output VH of the substrate switching circuit through a current-limiting resistor R1, the drain of the PMOS power tube MP1 is connected to the output VOUT of the chip and is connected to the ground through an output capacitor, one input end of the Driver circuit is connected to the output ENPFET of the substrate switching circuit, the other input end of the Driver circuit is connected to the switch control signal PWM, and the input of the substrate switching circuit is connected to the input end VBAT and the output end VOUT of the chip.
2. True shutdown circuit of a synchronous boost DC-DC converter according to claim 1, characterized in that:
the substrate switching circuit comprises a hysteresis comparator I0, NOT gates I1, I2, I3, I4 and I5, PMOS tubes MP2 and MP3, a voltage stabilizing capacitor CH and a current limiting resistor R1; a positive input end of the hysteresis comparator I0 is connected to a chip input voltage VBAT and a drain of a PMOS transistor MP2, a negative input end is connected to an output end VOUT of the chip and a drain of a PMOS transistor MP3, an output end of the hysteresis comparator I0 is connected to an input end of a not gate I1, an output end of the not gate I1 is connected to input ends of a not gate I2 and a not gate I5, an output end of the not gate I2 is connected to an input end X of a not gate I3, an output end of the not gate I3 is connected to an input end of a not gate I4 and a gate of a PMOS transistor MP2, an output end of the not gate I4 is connected to a gate of the PMOS transistor MP3, an output end of the not gate I5 is a control signal ENPFET, a source and a substrate of the PMOS transistor MP2 and a source and a substrate of the PMOS transistor MP3 are connected to ground through a capacitor CH and output VH;
due to the existence of the current-limiting resistor R1, an electric loop formed by the parasitic diode of the PMOS power tube MP1 and the current-limiting resistor R1, the PMOS tube MP2, the inductor L or the parasitic diode of the PMOS power tube MP1 and the current-limiting resistor R1, the PMOS tube MP2 and the PMOS tube MP3 cannot generate large current, and the circuit is prevented from being latched; the voltage VH selected by the PMOS tube MP2 and the PMOS tube MP3 is simultaneously used as the power supply of the power tube driving circuit and the substrate switching circuit; the on-resistance of the PMOS tube MP2 and the PMOS tube MP3 enables the voltage drop of the PMOS power tube MP1 or the PMOS tube MP2 to be less than 200mV when the PMOS power tube MP1 or the PMOS tube MP2 is switched on, so that VH has stronger load carrying capacity, and the PMOS power tube MP1 cannot be switched on by mistake when the driving circuit works;
the hysteresis comparator I0 compares the magnitude of the whole circuit input voltage VBAT and the whole circuit output voltage VOUT, when VBAT is higher than VOUT by about 100mV, the output of the hysteresis comparator controls the inverter I1 and I2 to enable the PMOS tube MP2 to be conducted and the PMOS tube MP3 to be turned off, the internal high power supply VH is equal to VBAT, the substrate of the PMOS power tube MP1 is also connected to VBAT through the current limiting resistor R1 and the PMOS tube MP2, when the whole circuit output voltage VOUT is higher than the whole circuit input voltage VBAT by about 100mV, the output of the hysteresis comparator I0 controls the NOT gate I3 and the I4 to enable the PMOS tube MP2 to be turned off and the PMOS tube MP3 to be conducted, the internal high power supply VH is equal to VOUT, and the substrate VBODY of the PMOS power tube MP1 is connected to the VOUT port through the current limiting resistor R1 and the PMOS tube MP 3; when the circuit is turned off, the potential of the gate end and the substrate of the power PMOS transistor MP1 is always equal to the highest potential in the circuit, so that the circuit is turned off truly.
3. True shutdown circuit of a synchronous boost DC-DC converter according to claim 2, characterized in that:
the current limiting resistor R1 is composed of a plurality of PMOS tubes connected in series, the size of the PMOS tubes connected in series is determined by the required resistance value, the grid end G of the PMOS tubes connected in series is connected with the ground, the A end is connected with the source ends of the PM2 and the PM3, and the B end is connected with the substrate of the power PMOS tube MP 1.
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CN202120780316.2U CN215934724U (en) | 2021-04-16 | 2021-04-16 | True turn-off circuit of synchronous boosting DC-DC converter |
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