CN214152897U - Wafer level embedded silicon wafer supporting fan-out packaging structure - Google Patents
Wafer level embedded silicon wafer supporting fan-out packaging structure Download PDFInfo
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- CN214152897U CN214152897U CN202120373978.8U CN202120373978U CN214152897U CN 214152897 U CN214152897 U CN 214152897U CN 202120373978 U CN202120373978 U CN 202120373978U CN 214152897 U CN214152897 U CN 214152897U
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 59
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 59
- 239000010703 silicon Substances 0.000 title claims abstract description 59
- 230000008093 supporting effect Effects 0.000 title claims abstract description 41
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 229910000679 solder Inorganic materials 0.000 claims abstract description 14
- 239000002313 adhesive film Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 76
- 239000010408 film Substances 0.000 claims description 26
- 239000010409 thin film Substances 0.000 claims description 10
- 239000002356 single layer Substances 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 claims description 3
- 239000000843 powder Substances 0.000 claims description 3
- 238000000748 compression moulding Methods 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 abstract description 8
- 238000004544 sputter deposition Methods 0.000 abstract description 8
- 238000011161 development Methods 0.000 abstract description 7
- 230000017525 heat dissipation Effects 0.000 abstract description 5
- 239000012528 membrane Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 3
- 238000010030 laminating Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- NGVDGCNFYWLIFO-UHFFFAOYSA-N pyridoxal 5'-phosphate Chemical compound CC1=NC=C(COP(O)(O)=O)C(C=O)=C1O NGVDGCNFYWLIFO-UHFFFAOYSA-N 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses an embedded silicon chip wafer of wafer level supports fan-out packaging structure, this structure includes the chip, and the laminating of chip back has the ABF membrane, has the support silicon layer of certain thickness at the back bonding of ABF membrane, supports the silicon layer and does not handle through the abrasive disc, and the chip openly has first nip and second nip openly can form metal routing layer, film dielectric layer, metal electrode and solder ball bump through technologies such as photoetching, development, sputtering, electroplating. The wafer-level embedded silicon wafer supporting fan-out packaging structure of the utility model has the advantages that the insulating medium adhesive film and the supporting layer are arranged outside the chip, the warping degree of the chip can be greatly reduced, and the supporting silicon layer is arranged outside the chip, so that the supporting silicon layer can effectively dissipate heat of the chip, better heat dissipation requirements are provided, and the novel packaging structure of the packaging thickness can be flexibly customized according to the packaging requirements of customers; customized chip package thickness requirements are provided according to customer requirements.
Description
Technical Field
The utility model relates to an embedded silicon chip wafer of wafer level supports fan-out packaging structure belongs to the semiconductor field.
Background
Wafer level chip packages wlp (wafer level package) and panel level chip packages plp (panel level package) have the advantages of high yield, dense pins, Rewirable (RDL) externally-extended pins, miniaturization, thinness, high reliability and the like.
The chip has a circuit surface called as a front surface, and the connection and protection functions are realized through technologies such as Rewiring (RDL) and Bumping; the corresponding non-containing line is called the back side. In some structures of WLP and PLP, in order to avoid the problems of mechanical scratch, collision defect, interference of photoelectric effect, etc. of bare chips and to perform laser coding more clearly, a layer of glue layer, referred to as a back glue layer for short, needs to be added on the back of the chip, i.e. the bare chip surface, so as to replace the effect of a plastic package material in the conventional package. However, the protective structure of this layer has insufficient mechanical strength, and cannot play a role in protecting the packaging structure, and meanwhile, WLP and PLP packaging structures often have a heat dissipation problem.
SUMMERY OF THE UTILITY MODEL
The purpose of the invention is as follows: in order to overcome the not enough that exists among the prior art, the utility model provides a fan-out packaging structure is supported to embedded silicon chip wafer of wafer level effectively solves the disk angularity problem among the operation process, provides the encapsulation technology method that better mechanical strength supported, provides back protection in single chip packaging structure, provides better heat dissipation demand to can customize the novel packaging structure of encapsulation thickness according to customer's encapsulation demand is nimble.
The technical scheme is as follows: for solving above-mentioned technical problem, the utility model discloses an embedded silicon chip wafer of wafer level supports fan-out packaging structure, including the chip, the chip openly is equipped with first nip and second nip, the laminating of the chip back has insulating medium glued membrane, and it has the supporting layer to adhere outside insulating medium glued membrane, uses the warping degree that the supporting layer can effectively reduce the reconsitution wafer.
Preferably, a metal wiring layer, a thin film dielectric layer, a metal electrode and a solder ball bump are formed on the front surface of the chip, and the back surface of the chip is completely wrapped by an insulating dielectric adhesive film.
Preferably, the support layer is a support silicon layer.
Preferably, the first pressure area and the second pressure area are provided with a positive electrode and a negative electrode, the positive electrode and the negative electrode are connected through metal wiring layers respectively, the two metal wiring layers are connected with the solder ball salient points respectively, and the metal wiring layers and the positive electrode and the negative electrode are supported through thin film dielectric layers.
Preferably, the thickness of the support layer is 0-40 mm.
Preferably, the insulating medium adhesive film comprises a bottom and a side surface, the chip is positioned in a groove formed in the bottom and the side surface, and the thickness of the bottom is 0-20 mm.
Preferably, a metal layer is arranged outside the support layer.
Preferably, the metal layer is a single-layer or multi-layer structure of a plurality of metals of Cu, Al, Ti, Ni and Ag, or a Ti/Ni/Ag laminated structure.
Preferably, a back glue layer is arranged outside the metal layer.
Preferably, the back adhesive layer is a liquid epoxy resin coating, a liquid or powder epoxy resin molding or a single-layer epoxy resin film.
Has the advantages that: the wafer-level embedded silicon wafer supporting fan-out packaging structure of the utility model has the advantages that the insulating medium adhesive film and the supporting layer are arranged outside the chip, the warping degree of the chip can be greatly reduced, and the supporting silicon layer is arranged outside the chip, so that the supporting silicon layer can effectively dissipate heat of the chip, better heat dissipation requirements are provided, and the novel packaging structure of the packaging thickness can be flexibly customized according to the packaging requirements of customers; providing customized chip packaging thickness requirements according to customer requirements; the back of the product is protected by supporting silicon, so that a better heat dissipation effect, a higher mechanical supporting effect and a better protection main chip can be provided.
Drawings
Fig. 1 is a schematic structural diagram of a wafer.
FIG. 2 is a schematic structural diagram of a wafer after a wafer is scribed.
Fig. 3 is a schematic structural diagram of a single chip.
Fig. 4 is a schematic illustration of a flip chip on a carrier wafer.
Fig. 5 is a schematic view of a reconstituted wafer.
Fig. 6 is a schematic view of a reconstituted wafer provided with a support layer.
Fig. 7 is a schematic illustration of the carrier wafer and temporary bonding film after being peeled from the reconstituted wafer.
Fig. 8 is a schematic diagram of the package structure after printing the electrodes.
FIG. 9 is a schematic diagram of a fan-out chip structure with supporting silicon.
FIG. 10 is a schematic diagram of a fan-out chip structure with a portion of supporting silicon ground away.
FIG. 11 is a schematic diagram of a fan-out chip structure with all supporting silicon ground away.
FIG. 12 is a schematic of a fan-out chip structure with all supporting silicon and part of the ABF film ground away.
FIG. 13 is a schematic of a fan-out chip structure with all supporting silicon and all ABF films ground away.
Fig. 14 is a schematic diagram of a fan-out chip structure with all supporting silicon, all ABF film 4 and part of the back silicon of chip 11 ground away.
FIG. 15 is a schematic diagram of a backside supported silicon fan-out multi-chip package structure.
Fig. 16 is a schematic diagram of a structure having a metal layer.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
As shown in fig. 11, the wafer level embedded silicon wafer supporting fan-out package structure of the present invention includes a chip, an ABF film 4 is attached to a back surface of the chip, a supporting silicon layer 5 with a certain thickness is attached to a back surface of the ABF film 4, the supporting silicon layer 5 is not subjected to a grinding process, a first pressure region 111 and a second pressure region 112 are disposed on a front surface of the chip 11, a metal routing layer 61, a thin film dielectric layer 62, a metal electrode 63 and a solder bump 64 are formed on the front surfaces of the first pressure region 111 and the second pressure region 112 through processes such as photolithography, development, sputtering, electroplating, etc., the supporting layer is externally provided with a metal layer, and the metal layer is a single-layer or multi-layer structure of Cu, Al, Ti, Ni, Ag, or a Ti/Ni/Ag stacked layer structure. The metal layer is externally provided with a back adhesive layer, and the back adhesive layer is formed by coating liquid epoxy resin, performing compression molding on liquid or powder epoxy resin or forming a single-layer epoxy resin film, as shown in fig. 16.
Referring to fig. 10, the fan-out structure 71 supported by a silicon wafer according to the present invention includes a chip 11, an ABF film 4 is attached to a back surface of the chip, a supporting silicon layer 5 having a certain thickness is adhered to a back surface of the ABF film 4, the supporting silicon layer 5 is subjected to partial lapping treatment, a first nip 111 and a second nip 112 are provided on a front surface of the chip 11, and a metal routing layer 61, a thin film dielectric layer 62, a metal electrode 63, and a solder ball bump 64 are formed on front surfaces of the first nip 111 and the second nip 112 through photolithography, development, sputtering, electroplating, and other processes.
Referring to fig. 11, the fan-out structure 72 supported by a silicon wafer according to the present invention includes a chip 11, an ABF film 4 is attached to the back surface of the chip, an original supporting silicon layer 5 on the back surface of the ABF film is completely removed, a first pressure region 111 and a second pressure region 112 are disposed on the front surface of the chip 11, and a metal routing layer 61, a thin film dielectric layer 62, a metal electrode 63, and solder ball bumps 64 are formed on the front surfaces of the first pressure region 111 and the second pressure region 112 by photolithography, development, sputtering, electroplating, and other processes.
Referring to fig. 12, the fan-out structure 73 supported by a silicon wafer of the present invention includes a chip 11, an ABF film 4 is attached to a back surface of the chip, the ABF film 4 is subjected to lapping, a first pressing area 111 and a second pressing area 112 are provided on a front surface of the chip 11, and a metal routing layer 61, a thin film dielectric layer 62, a metal electrode 63 and a solder bump 64 are formed on the front surfaces of the first pressing area 111 and the second pressing area 112 through processes such as photolithography, development, sputtering, electroplating, etc.
Referring to fig. 13, the fan-out structure 74 supported by a silicon wafer according to the present invention includes a chip 11, an ABF film and supporting silicon originally attached to the back surface of the chip 11 are completely removed, a pressure region 111 and a pressure region 112 are disposed on the front surface of the chip 11, and a metal routing layer 61, a thin film dielectric layer 62, a metal electrode 63 and a solder bump 64 are formed on the front surfaces of the pressure region 111 and the pressure region 112 by photolithography, development, sputtering, electroplating, and the like.
Referring to fig. 14, the fan-out structure 74 supported by a silicon wafer according to the present invention includes a chip 11, the ABF film and the supporting silicon originally attached to the back surface of the chip 11 are completely removed, the back surface of the chip 11 is thinned by lapping, the front surface of the chip 11 has a pressure region 111 and a pressure region 112, and the metal routing layer 61, the thin film dielectric layer 62, the metal electrode 63 and the solder bump 64 are formed on the front surfaces of the first pressure region 111 and the second pressure region 112 by photolithography, development, sputtering, electroplating, and the like.
The silicon wafer supporting fan-out structure provided by the invention is realized by the following process:
the method comprises the following steps: as shown in fig. 1-2, a material wafer 1 is lapped to a specified thickness;
step two: as shown in fig. 3, the incoming wafer 1 ground to a specified thickness is cut into individual pieces, such as chips 11 and 12, along the scribe line 10;
step three: attaching a temporary bonding film 2 on the carrier wafer 3, and using a flip-chip device to flip chips on a coming wafer one by one on the carrier wafer 3, as shown in fig. 4; it is also possible to flip-chip one or more chips onto the carrier wafer 3 to achieve a multi-chip tape supported silicon fan-out structure (as shown in fig. 16);
step four: pressing an ABF film 4 on the inverted chip on the carrier wafer 3 by using a film pressing machine to form a reconstituted wafer 31, as shown in FIG. 5;
step five: a support wafer 5 is disposed on the reconstituted wafer 31 to provide mechanical support for the entire structure, which facilitates subsequent processing, as shown in fig. 6;
step six: peeling the carrier wafer 3 and the temporary bonding film 2 off the reconstituted wafer 31, as shown in fig. 7;
step seven: coating photoresist on the chip 11 of the reconstituted wafer 31, and performing photoetching or laser process by using a mask to form a pattern opening to form a re-passivation layer;
step eight: coating a photoresist layer again, and performing photoetching or laser process by using a mask to form a metal layer pattern opening;
step nine: electroplating in the metal layer pattern opening to form a rewiring metal layer 61 or a metal electrode 63;
repeating the seven and eight steps to realize a multilayer metal structure until a final metal electrode 63 is formed as an input and an output;
step ten: solder ball bumps 64 can be formed on the metal electrodes 63 and reflowed (optionally), and the solder ball bumps 64 can be tin-based alloy or pure tin solder, as shown in fig. 8;
step eleven: back lapping the reconstituted wafer 31 to a specified thickness (multiple lapping thicknesses can be selected and different packaging materials can be lapped);
step twelve: sputtering or evaporating the reconstructed wafer 31 to grow a metal layer 82, wherein the metal layer is a single-layer or multi-layer structure of various metals such as Cu, Al, Ti, Ni, Ag and the like, and can be a laminated structure of Ti/Ni/Ag;
step thirteen: after the metal layer is finished, the back adhesive can be coated on the surface of the metal layer in a spin coating or film pasting mode, so that the protection effect is achieved.
Fourteen steps: the reconstructed wafer after the grinding piece is finished is cut into a single piece, a back-gold fan-out chip structure with supporting silicon, a back-adhesive fan-out chip structure with supporting silicon, an early back-gold fan-out chip structure on an ABF film and then a back-adhesive fan-out chip structure, a back-gold fan-out chip structure on a main body chip and an early back-gold fan-out chip structure on the main body chip can be formed.
In step eleven, the reconstituted wafer after lapping is cut into individual pieces, and a fan-out chip structure 7 with supporting silicon (as shown in fig. 9), a fan-out chip structure 71 with part of supporting silicon (as shown in fig. 10), a fan-out chip structure 72 with all of supporting silicon (as shown in fig. 11), a fan-out chip structure 73 with all of supporting silicon and part of ABF film 4 (as shown in fig. 12), a fan-out chip structure 74 with all of supporting silicon and all of ABF film 4 (as shown in fig. 13), and a fan-out chip structure 75 with all of supporting silicon, all of ABF film 4, and part of back silicon of chip 11 (as shown in fig. 14) can be formed.
The above description is only a preferred embodiment of the present invention, and it should be noted that: for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be considered as the protection scope of the present invention.
Claims (10)
1. The utility model provides a wafer level embedded silicon chip wafer supports fan-out packaging structure, includes the chip, the chip front side is equipped with first nip and second nip, its characterized in that: the back of the chip is attached with an insulating medium adhesive film, and a supporting layer is adhered outside the insulating medium adhesive film.
2. The wafer level embedded silicon wafer support fan out package structure of claim 1, in which: the front surface of the chip is provided with a metal wiring layer, a thin film dielectric layer, a metal electrode and a solder ball salient point, and the back surface of the chip is completely wrapped by an insulating dielectric adhesive film.
3. The wafer level embedded silicon wafer support fan out package structure of claim 2, wherein: the support layer is a support silicon layer.
4. The wafer level embedded silicon wafer support fan out package structure of claim 2, wherein: and the first pressure area and the second pressure area are provided with a positive electrode and a negative electrode, the positive electrode and the negative electrode are connected through metal wiring layers respectively, the two metal wiring layers are connected with the solder ball salient points respectively, and the metal wiring layers and the positive electrode and the negative electrode are supported through thin film dielectric layers.
5. The wafer level embedded silicon wafer support fan out package structure of claim 3 or 4, wherein: the thickness of the supporting layer is 0-40 mm.
6. The wafer level embedded silicon wafer support fan out package structure of claim 2, wherein: the insulating medium adhesive film comprises a bottom and a side face, the chip is located in a groove formed in the bottom and the side face, and the thickness of the bottom is 0-20 mm.
7. The wafer level embedded silicon wafer support fan out package structure of claim 5, in which: and a metal layer is arranged outside the supporting layer.
8. The wafer level embedded silicon wafer support fan out package structure of claim 7, in which: the metal layer is a single-layer or multi-layer structure of Cu, Al, Ti, Ni and Ag, or a Ti/Ni/Ag laminated structure.
9. The wafer level embedded silicon wafer support fan out package structure of claim 7 or 8, wherein: and a back glue layer is arranged outside the metal layer.
10. The wafer level embedded silicon wafer support fan out package structure of claim 9, wherein: the back glue layer is made of liquid epoxy resin coating, liquid or powder epoxy resin compression molding or a single-layer epoxy resin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120373978.8U CN214152897U (en) | 2021-02-10 | 2021-02-10 | Wafer level embedded silicon wafer supporting fan-out packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120373978.8U CN214152897U (en) | 2021-02-10 | 2021-02-10 | Wafer level embedded silicon wafer supporting fan-out packaging structure |
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| CN214152897U true CN214152897U (en) | 2021-09-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115360166A (en) * | 2022-10-19 | 2022-11-18 | 江苏长晶科技股份有限公司 | Chip packaging structure and chip packaging method |
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2021
- 2021-02-10 CN CN202120373978.8U patent/CN214152897U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115360166A (en) * | 2022-10-19 | 2022-11-18 | 江苏长晶科技股份有限公司 | Chip packaging structure and chip packaging method |
| CN115360166B (en) * | 2022-10-19 | 2023-03-24 | 江苏长晶科技股份有限公司 | Chip packaging structure and chip packaging method |
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Address after: 210000 No. 8, Linchun Road, Pukou Economic Development Zone, Pukou District, Nanjing, Jiangsu Province Patentee after: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Country or region after: China Address before: 211800 a-11, 69 Shuangfeng Road, Pukou Economic Development Zone, Pukou District, Nanjing City, Jiangsu Province Patentee before: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Country or region before: China |