CN211044059U - Novel CMOS technology overcurrent protection structure - Google Patents
Novel CMOS technology overcurrent protection structure Download PDFInfo
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- CN211044059U CN211044059U CN201922281294.0U CN201922281294U CN211044059U CN 211044059 U CN211044059 U CN 211044059U CN 201922281294 U CN201922281294 U CN 201922281294U CN 211044059 U CN211044059 U CN 211044059U
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Abstract
The utility model relates to a novel CMOS process overcurrent protection structure, which comprises a first-stage current mirror, a second-stage current mirror, a first-stage current mirror, a second-stage current mirror and a second-stage current mirror, wherein the first-stage current mirror comprises a reference current source and is used for generating a first-stage mirror current; the second-stage current mirror takes the first-stage mirror image current as a reference current and generates a second mirror image current; the gate of the protection transistor is connected with the gate of the protected transistor, and the second mirror current is used as a protection transistor of a current source; the current mirror overcurrent protection structure is simple and easy to integrate.
Description
Technical Field
The utility model belongs to the microelectronics field, in particular to improvement of transistor circuit mechanism.
Background
With the development of semiconductor technology, the integrated circuit has higher integration level, and in order to improve the stability of the integrated circuit and make it less prone to damage, it is necessary to apply over-current protection to the critical transistors, such as the output stage transistor. In order to prevent the transistors inside the integrated circuit from being damaged due to excessive current, a special overcurrent protection circuit needs to be designed. When the current of the protected transistor exceeds a threshold value, the overcurrent protection circuit starts to work so that the current of the protected transistor does not increase continuously, and therefore the effect of the protection transistor is achieved.
At present, a common overcurrent protection circuit is complex in circuit or uses an operational amplifier, so that the circuit is not easy to integrate in a chip.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a transistor overcurrent protection circuit of simplified structure. The utility model discloses an use the current mirror to realize the overcurrent protection function, very easy integration. The maximum current which can flow by the protected transistor can be adjusted by only adjusting the size of one reference current source.
Specifically, the method comprises the steps of setting a first-stage current mirror by using confidence, wherein the first-stage current mirror comprises a reference current source and is used for generating a first-stage mirror image current; the second-stage current mirror takes the first-stage image current as a reference current and generates a second-stage image current; and the gate of the protection transistor is connected with the gate of the protected transistor, and the second-stage mirror current is used as a protection transistor of a current source.
The reference current source is mirrored to the second-stage current mirror through the first-stage current mirror and then is mirrored to the drain electrode of the protection transistor through the second-stage current mirror, and the maximum current of the protected transistor keeps the current of the reference current source again due to the connection of the grid electrode of the protection transistor and the grid electrode of the protected transistor, so that the maximum current cannot be increased continuously.
In a preferred aspect, the first stage current mirror includes: the source transistor is connected with the grid electrode of the mirror image transistor, and the grid electrode of the source transistor is connected with the drain electrode.
In a preferred aspect, the second stage current mirror comprises: the transistor comprises a source transistor and a mirror image transistor, wherein the source transistor is connected with the grid electrode of the mirror image transistor, and the grid electrode of the mirror image transistor is connected with the drain electrode; the drain of the source transistor is connected with the drain of the mirror transistor of the first stage current mirror.
In a preferred scheme, the overcurrent protection circuit further comprises an overcurrent indicator connected to the output end of the first-stage current mirror, and the overcurrent indicator comprises a first inverter and a second inverter which are connected in series.
In a preferred scheme, a source transistor and a mirror transistor of the first-stage current mirror are NMOS transistors; the source transistor and the mirror transistor of the second-stage current mirror are PMOS tubes; the protected transistor and the protection transistor are both NMOS tubes.
In a preferred scheme, the source electrodes of the source transistor and the mirror transistor of the first-stage current mirror are grounded; the source electrodes of the source transistor and the mirror transistor of the second-stage current mirror are connected with a power supply; the source electrodes of the protected transistor and the protecting transistor are grounded and connected with a resistor in series, and the resistor is grounded; the drain electrode of the protected transistor is connected with a power supply.
Compared with the prior art, the current mirror of the utility model is used as a transistor protection device, has simple circuit structure, realizes the overcurrent protection function by using the current mirror, and is suitable for CMOS integrated circuit technology; and the maximum current which can flow by the protected transistor can be adjusted by only adjusting the size of one current source.
Drawings
Fig. 1 is a schematic diagram of an overcurrent protection circuit.
Detailed Description
Referring to fig. 1, the circuit structure provided by the present invention is suitable for CMOS integrated circuit process, and it is obvious that those skilled in the art can easily extend it to integrated circuits of other processes.
The overcurrent protection circuit shown in fig. 1 includes a first-stage current mirror M1, a second-stage current mirror M2, a protection transistor Q3, and a protected transistor Q1. The first stage current mirror M1 maps current to the second stage current mirror M2, the second stage current mirror M2 maps current to the protection transistor Q3, the current of the protection transistor Q3 is limited to the reference current l1, and the protection transistor Q3 is connected with the gate of the protected transistor Q1, so that the current of the protected transistor Q1 does not exceed the reference current l 1.
The first stage current mirror M1 comprises a reference current source i, and a first stage current mirror M1 is used for generating a first stage mirror current; a second stage current mirror M2, which takes the first stage mirror current l1 as a reference current and generates a second mirror current (equal to l1 in magnitude); the protection transistor Q3 takes the second mirror current as a current.
The first current mirror M1 includes: the transistor comprises a source transistor Q5 and a mirror image transistor Q4, wherein the source transistor Q5 is connected with the grid electrode of the mirror image transistor Q4, the grid electrode of the source transistor is connected with the drain electrode of the source transistor, and the mirror image transistor Q4 and the source transistor Q5 are both NMOS transistors. The drain Q5 of the source transistor is connected with the output end of a reference current source l1, the reference current source i is connected with a power supply VCC, the gate of the source transistor Q5 is grounded, and the gate and the drain of the source transistor Q5 are connected. The mirror transistor Q4 is the same size as the source transistor so that the current flowing through the source transistor Q5 and the gate transistor is the same; the drain of the mirror transistor Q4 is used as the output terminal of the first stage current mirror M1, and the source of the mirror transistor Q7 is grounded.
The second current mirror M2 includes: the transistor comprises a source transistor Q4 and a mirror transistor Q2, wherein the mirror transistor Q2 and the source transistor Q4 are both PMOS transistors. The source transistor Q4 is connected to the gate of the mirror transistor Q2 and the source transistor Q4 is of the same size as the mirror transistor Q2 so that the source transistor Q4 and the mirror transistor Q2 have the same gate current, and the mirror transistor Q2 has its gate connected to the drain. The drain of the source transistor Q4 is connected to the drain of the mirror transistor Q2 of the first current mirror M1, and the source of the source transistor Q $ is connected to the power supply VCC. The drain electrode of the mirror image transistor Q2 is connected with the drain electrode of the mirror image transistor Q2 of the protection transistor Q3 as the output end of the second-stage mirror image circuit M2, and the source electrode of the mirror image transistor Q2 is connected with a power supply VCC.
An overcurrent indicator W is also arranged at the drain end of the mirror transistor Q5 of the first stage current mirror M1 and the source transistor Q4 of the second stage current mirror M2. The over-current indicator W includes a first inverter U1A and a second inverter U2A connected in series. The drain output of the mirror transistor Q6 of the first-stage current mirror M1 passes through two stages of inverters, the output is an overcurrent indication, when the circuit is in overcurrent protection, the input of U1A is low, the output is high, the input of U2A is high, the output is low, and the current mirror can be used as an overcurrent indication signal.
The drain of the mirror transistor Q2 of the second-stage current mirror M2 is used as the output end of the second-stage current mirror, the drain is connected with the drain of the protection transistor Q3, and the protection transistor Q3 is an NMOS transistor.
The protection transistor Q3 is connected to the gate of the protected transistor Q1, and the gate of the protected transistor Q is also connected to the logic control terminal logic, which outputs a control level to control the current magnitude of the protected transistor Q1.
The source of the source transistor Q4 and the source of the mirror transistor Q2 of the second current mirror M2 are connected with a power supply, the sources of the protected transistor Q1 and the protection transistor Q3 are grounded and connected with a resistor R L in series, the resistor R L is grounded, and the drain of the protected transistor Q1 is connected with the power supply.
When the circuit works, the current source I1 is mapped to the second-stage current mirror through the first-stage current mirror, the second-stage current mirror is mapped to the drain of the Q3NMOS, the Q1 is connected with the grid of the Q3, when logic is in a safety range, the Q1 works normally, and at the moment, the current flowing through the Q1 is smaller than I1; when logic is increased to a critical value and is increased continuously, the current of the Q3 is kept at the maximum I1 due to the action of the current mirror, and the Q1 is connected with the grid electrode of the Q3, so that the current of the Q1 is kept at the maximum I1, and the current cannot be increased continuously, and therefore overcurrent protection of the Q1 is achieved.
Claims (6)
1. A novel CMOS technology overcurrent protection structure is characterized by comprising:
the first-stage current mirror comprises a reference current source and is used for generating a first-stage mirror image current;
the second-stage current mirror takes the first-stage mirror image current as a reference current and generates a second mirror image current;
and the gate of the protection transistor is connected with the gate of the protected transistor, and the second mirror current is used as a protection transistor of a current source.
2. The novel CMOS process overcurrent protection structure of claim 1, wherein the first stage current mirror comprises: the source transistor is connected with the grid electrode of the mirror image transistor, and the grid electrode of the source transistor is connected with the drain electrode.
3. The novel CMOS process overcurrent protection structure of claim 2, wherein the second stage current mirror comprises: the transistor comprises a source transistor and a mirror image transistor, wherein the source transistor is connected with the grid electrode of the mirror image transistor, and the grid electrode of the mirror image transistor is connected with the drain electrode; the drain of the source transistor is connected with the drain of the mirror transistor of the first stage current mirror.
4. The novel CMOS process over-current protection structure as claimed in claim 1, further comprising an over-current indicator connected to an output of said first stage current mirror, said over-current indicator comprising a first inverter and a second inverter connected in series.
5. A novel CMOS process over-current protection structure as claimed in any one of claims 1 to 4, wherein the source transistor and the mirror transistor of said first stage current mirror are NMOS transistors; the source transistor and the mirror transistor of the second-stage current mirror are PMOS tubes; the protected transistor and the protection transistor are both NMOS tubes.
6. The novel CMOS process over-current protection structure of claim 5, wherein the sources of the source transistor and the mirror transistor of said first stage current mirror are grounded; the source electrodes of the source transistor and the mirror transistor of the second-stage current mirror are connected with a power supply; the source electrodes of the protected transistor and the protecting transistor are grounded and connected with a resistor in series, and the resistor is grounded; the drain electrode of the protected transistor is connected with a power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922281294.0U CN211044059U (en) | 2019-12-18 | 2019-12-18 | Novel CMOS technology overcurrent protection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922281294.0U CN211044059U (en) | 2019-12-18 | 2019-12-18 | Novel CMOS technology overcurrent protection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211044059U true CN211044059U (en) | 2020-07-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201922281294.0U Active CN211044059U (en) | 2019-12-18 | 2019-12-18 | Novel CMOS technology overcurrent protection structure |
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| CN (1) | CN211044059U (en) |
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2019
- 2019-12-18 CN CN201922281294.0U patent/CN211044059U/en active Active
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