CN208923095U - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- CN208923095U CN208923095U CN201821959367.6U CN201821959367U CN208923095U CN 208923095 U CN208923095 U CN 208923095U CN 201821959367 U CN201821959367 U CN 201821959367U CN 208923095 U CN208923095 U CN 208923095U
- Authority
- CN
- China
- Prior art keywords
- chip
- bonding pad
- heat dissipation
- deep gouge
- dissipation bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Credit Cards Or The Like (AREA)
Abstract
The utility model discloses a kind of semiconductor package, including heat dissipation bonding pad, chip and the conductive welding disk being located in epoxy insulator, the chip is located on heat dissipation bonding pad, several conductive welding disks are equipped with positioned at heat dissipation bonding pad periphery, the conductive welding disk is connected with chip by a lead, the central area of the heat dissipation bonding pad is provided with the deep gouge for chip insertion, the card slot of connection deep gouge is provided on the heat dissipation bonding pad, it is equipped with to push against in the card slot and is equipped with heat conductive insulating elastic layer between the elastic slice of chip side wall, the deep gouge cell wall and chip.The utility model passes through the cooperation of elastic slice in the heat conductive insulating elastic layer and card slot being arranged in deep gouge, realizes that chip is detachable chimeric in deep gouge, facilitates staff's disassembly, assembling chip and heat dissipation bonding pad, avoid the occurrence of waste product.
Description
Technical field
The utility model relates to a kind of semiconductor packages, belong to leadless packages technical field.
Background technique
In semiconductor production process, integrated antenna package (IC package) is one of important step, to protect IC
Chip simultaneously provides exposed electrical connection.
The encapsulation kenel of integrated circuit it is many kinds of, wherein a kind of fairly common encapsulation kenel is first to provide heatsink welding
Chip is then attached on chip carrier by disk, and the conductive welding disk of periphery is electrically connected by lead line.Then, envelope is utilized
In a part of glue material coating chip, heat dissipation bonding pad and conductive welding disk, and at least fill up the sky near chip and conducting wire
Between, the encapsulation of chip is completed, the chip after the completion of encapsulating can pass through conductive welding disk and be electrically connected with extraneous component.
However, existing chip is to be adhered on heat dissipation bonding pad using silver paste, and need to solidify silver paste by baking procedure,
With fixed chip in the use cost on heat dissipation bonding pad, thus with silver paste, and time and manpower are expended, and after solidification,
Chip is difficult to separate heat dissipation bonding pad, when failure of chip occurs the problems such as, can only scrap chip and heat dissipation bonding pad.
Summary of the invention
The purpose of the utility model is to provide a kind of semiconductor packages, pass through the heat conductive insulating elasticity being arranged in deep gouge
The cooperation of elastic slice in layer and card slot realizes that chip is detachable chimeric in deep gouge, facilitates staff's disassembly, assembling chip
And heat dissipation bonding pad, avoid the occurrence of waste product.
In order to achieve the above objectives, the technical solution adopted in the utility model is: a kind of semiconductor package, including is located at
Heat dissipation bonding pad, chip and conductive welding disk in epoxy insulator, the chip are located on heat dissipation bonding pad, are located at heat dissipation bonding pad periphery
Equipped with several conductive welding disks, the conductive welding disk is connected with chip by a lead, and the central area of the heat dissipation bonding pad is provided with
For the deep gouge of chip insertion, it is provided with the card slot of connection deep gouge on the heat dissipation bonding pad, is equipped with and is pushed against in chip side in the card slot
The elastic slice of wall is equipped with heat conductive insulating elastic layer between the deep gouge cell wall and chip.
Further improved scheme is as follows in above-mentioned technical proposal:
1. in above scheme, the deep gouge depth is not more than chip thickness.
2. in above scheme, the heat conductive insulating elastic layer is with a thickness of 0.1-0.2mm.
3. in above scheme, annular groove is provided on the chip side wall, the heat conductive insulating elastic layer is equipped with and is connected in
Annular relief in annular groove.
4. being at least provided with a through hole in above scheme, on the elastic slice.
Due to the application of the above technical scheme, the utility model has the advantage that compared with prior art
1, a kind of semiconductor package of the utility model opens up upper deep gouge by the central area in heat dissipation bonding pad, and
Upper heat conductive insulating elastic layer is set on deep gouge cell wall, meanwhile, the card slot with elastic slice is opened in the side of deep gouge, is pacified by chip
When putting into deep gouge, chip extrusion elastic compression, to enable the chip to, at this point, elastic slice has trend of rebound, push away in insertion deep gouge
Dynamic chip is displaced to the side far from elastic slice, and cooperation heat conductive insulating elastic layer clamps chip, that is, is able to achieve the fixation of chip, and energy
Staff is facilitated to dismantle recombination, it is very convenient to reduce scrappage；In addition, heat conductive insulating elastic layer can also fill deep gouge slot
Gap between wall and chip, to guarantee the heat conduction efficiency between chip and heat dissipation bonding pad.
2, a kind of semiconductor package of the utility model, by being provided with annular groove on chip side wall, in heat conductive insulating
Annular relief engaged therewith is provided on elastic layer, after chip is embedded in deep gouge, annular relief can be caught in annular groove,
Chip embedded location can not only be accurately positioned, moreover it is possible to prevent chip from being detached from deep gouge easily, stablize chip position.
3, a kind of semiconductor package of the utility model, it is exhausted in subsequent epoxy after opening up through hole on elastic slice
Edge resin is molded to form epoxy insulator during, epoxy insulation resin can fill up card slot, avoid epoxy by through hole
Insulating resin presses elastic slice in injection moulding process, and influences the stability of chip.
Detailed description of the invention
Attached drawing 1 is a kind of structural schematic diagram of semiconductor package of the utility model embodiment 1；
Attached drawing 2 is the enlarged drawing of part A in Fig. 1；
Attached drawing 3 is the enlarged drawing of part B in Fig. 1；
Attached drawing 4 is a kind of structural schematic diagram of semiconductor package of the utility model embodiment 2；
Attached drawing 5 is the enlarged drawing of C portion in Fig. 4.
In the figures above: 1, heat dissipation bonding pad；11, deep gouge；12, card slot；13, elastic slice；131, through hole；14, annular groove；2,
Heat conductive insulating elastic layer；21, annular relief；3, chip；4, conductive welding disk；5, lead；6, epoxy insulator.
Specific embodiment
Embodiment 1: a kind of semiconductor package, referring to attached drawing 1-3, including the heatsink welding being located in epoxy insulator 6
Disk 1, chip 3 and conductive welding disk 4, the chip 3 are located on heat dissipation bonding pad 1, are located at 1 periphery of heat dissipation bonding pad and are equipped with several conductions
Pad 4, the conductive welding disk 4 and chip 3 are connected by a lead 5, and the central area of the heat dissipation bonding pad 1 is provided with embedding for chip 3
The deep gouge 11 entered is provided with the card slot 12 of connection deep gouge 11 on the heat dissipation bonding pad 1, is equipped with and is pushed against in chip 3 in the card slot 12
The elastic slice 13 of side wall is equipped with heat conductive insulating elastic layer 2 between 11 cell wall of deep gouge and chip 3.
Above-mentioned 11 depth of deep gouge is not more than 3 thickness of chip；
Above-mentioned heat conductive insulating elastic layer 2 is with a thickness of 0.1-0.2mm, preferably 0.15mm；
Annular groove 14 is provided on 3 side wall of said chip, above-mentioned heat conductive insulating elastic layer 2 is equipped with and is connected in annular groove 14
Annular relief 21；
A through hole 131 is at least provided on above-mentioned elastic slice 13.
Embodiment 2: a kind of semiconductor package, referring to attached drawing 4-5, including the heatsink welding being located in epoxy insulator 6
Disk 1, chip 3 and conductive welding disk 4, the chip 3 are located on heat dissipation bonding pad 1, are located at 1 periphery of heat dissipation bonding pad and are equipped with several conductions
Pad 4, the conductive welding disk 4 and chip 3 are connected by a lead 5, and the central area of the heat dissipation bonding pad 1 is provided with embedding for chip 3
The deep gouge 11 entered is provided with the card slot 12 of connection deep gouge 11 on the heat dissipation bonding pad 1, is equipped with and is pushed against in chip 3 in the card slot 12
The elastic slice 13 of side wall is equipped with heat conductive insulating elastic layer 2 between 11 cell wall of deep gouge and chip 3.
Above-mentioned 11 depth of deep gouge is not more than 3 thickness of chip；
Above-mentioned heat conductive insulating elastic layer 2 is with a thickness of 0.1-0.2mm, preferably 0.15mm；
A through hole 131 is at least provided on above-mentioned elastic slice 13.
When using above-mentioned semiconductor package, by opening up for deep gouge 11, can not only 3 installation site of positioning chip,
Facilitate staff's assembling chip 3 and heat dissipation bonding pad 1, moreover it is possible to using in the heat conductive insulating elastic layer 2 and card slot 12 in deep gouge 11
The extrusion fit of elastic slice 13 fix 3 position of chip, to realize the detachable assembled of chip 3 and heat dissipation bonding pad 1, reduce
Scrappage；Meanwhile heat conductive insulating elastic layer 2 can also be eliminated between 11 cell wall of deep gouge and chip 3 using the deformation effect of itself
Gap guarantees the heat transfer efficiency between chip 3 and heat dissipation bonding pad 1.
In addition, upper 21 He of annular relief being mutually clamped is respectively set on 3 side wall of heat conductive insulating elastic layer 2 and chip
Annular groove 14 stablizes the installation of chip 3 to further block the chip 3 of insertion deep gouge 11.
The above embodiments are only for explaining the technical ideas and features of the present invention, and its object is to allow be familiar with technique
Personage can understand the content of the utility model and implement accordingly, do not limit the protection scope of the present invention.
All equivalent change or modifications according to made by the spirit of the present invention essence, should all cover the protection scope of the utility model it
It is interior.
Claims (5)
1. a kind of semiconductor package, including the heat dissipation bonding pad (1), chip (3) and conductive weldering being located in epoxy insulator (6)
Disk (4), the chip (3) are located on heat dissipation bonding pad (1), are located at heat dissipation bonding pad (1) periphery and are equipped with several conductive welding disks (4),
The conductive welding disk (4) and chip (3) are connected by a lead (5), it is characterised in that: the central area of the heat dissipation bonding pad (1)
It is provided with the deep gouge (11) for chip (3) insertion, the card slot (12) of connection deep gouge (11) is provided on the heat dissipation bonding pad (1), it is described
It is equipped with to push against to be equipped between the elastic slice (13) of chip (3) side wall, deep gouge (11) cell wall and chip (3) in card slot (12) and lead
Thermal insulation elastic layer (2).
2. semiconductor package according to claim 1, it is characterised in that: deep gouge (11) depth is not more than chip
(3) thickness.
3. semiconductor package according to claim 2, it is characterised in that: heat conductive insulating elastic layer (2) thickness
For 0.1-0.2mm.
4. semiconductor package according to claim 3, it is characterised in that: be provided with annular on chip (3) side wall
Slot (14), the heat conductive insulating elastic layer (2) are equipped with the annular relief (21) being connected in annular groove (14).
5. semiconductor package according to claim 1, it is characterised in that: be at least provided with one on the elastic slice (13)
Through hole (131).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821959367.6U CN208923095U (en) | 2018-11-27 | 2018-11-27 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821959367.6U CN208923095U (en) | 2018-11-27 | 2018-11-27 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208923095U true CN208923095U (en) | 2019-05-31 |
Family
ID=66712401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821959367.6U Active CN208923095U (en) | 2018-11-27 | 2018-11-27 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208923095U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110379784A (en) * | 2019-07-23 | 2019-10-25 | 王欣 | A kind of semiconductor package |
-
2018
- 2018-11-27 CN CN201821959367.6U patent/CN208923095U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110379784A (en) * | 2019-07-23 | 2019-10-25 | 王欣 | A kind of semiconductor package |
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|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |