CN207603788U - The multi-functional TV for being charged and discharged management system - Google Patents
The multi-functional TV for being charged and discharged management system Download PDFInfo
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- CN207603788U CN207603788U CN201721723408.7U CN201721723408U CN207603788U CN 207603788 U CN207603788 U CN 207603788U CN 201721723408 U CN201721723408 U CN 201721723408U CN 207603788 U CN207603788 U CN 207603788U
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Abstract
The utility model is related to a kind of multi-functional TVs for being charged and discharged management system, TV driving plate is provided in the TV, the TV driving plate manages circuit drives LED light by LED illumination and illuminates, it is charged by mobile phone charge management circuit to mobile phone, it is charged by battery charging management circuit to 18650 battery packs, circuit drives liquid crystal display module and loudspeaker is managed by DC power supply.The utility model has the advantages that：It is not influenced and limitation by mains-supplied, power failure or mains-supplied it is unstable, it is in short supply in the case of, product can use solar energy, wind-power electricity generation group, it charges Deng external DC power supply to electrical appliance, so as to maintain normal work certain time using electrical appliance internal battery.
Description
Technical field
The utility model is related to a kind of multi-functional TVs for being charged and discharged management system.
Background technology
The electrical appliances such as traditional TV only have television set basic function, do not contain external power supply charge the battery, LED shine
Bright, mobile phone quick charge (QC3.0 fast charge agreements）Etc. functions.Function is single, it is impossible to meet the actual demand of people.
Invention content
The defects of to overcome the prior art, the utility model provide a kind of multi-functional electricity for being charged and discharged management system
Depending on the technical solution of the utility model is：
The multi-functional TV for being charged and discharged management system, which is characterized in that TV driving is provided in the TV
Plate, the TV driving plate manage circuit drives LED light by LED illumination and illuminate, mobile phone is filled by mobile phone charge management circuit
Electricity charges to 18650 battery packs by battery charging management circuit, and circuit drives liquid crystal display module and loudspeaker are managed by DC power supply
.
The LED illumination management circuit is filtered including power management chip UM1,12V normal DC voltages by capacitance CM7
It is input to the 1st foot of power management chip UM1, the 2nd foot of one end access power management chip UM1 of capacitance CM8, the other end afterwards
The 3rd foot of access power management chip UM1, one end of capacitance CM7 and ground connection, the 5th foot of power management chip UM1 pass through series connection
It is grounded after resistance RM10；After resistance RM9, resistance RM18, resistance RM11 and capacitance CM9 parallel connections, one end access power supply of resistance RM9
The 4th foot of managing chip UM1, the other end access the STB ports of circuit board, collector and the resistance RM18 of NPN transistor QM1
One end connection, emitter connect and is grounded with one end of capacitance CM9, and ground level is connect with one end of resistance RM11, in resistance RM9
The other end and the resistance RM18 other ends between connect resistance a RM12, the capacitance CM9 the other end access button
PWR_ON/OFF_A;The 6th foot output voltage of power management chip UM1 is filtered over the ground by capacitance CM6 and capacitance CM51 parallel connections
After be output to socket CN2；
12V normal DC voltages are input to the 1st foot of power management chip UM2, capacitance CM12 after being filtered by capacitance CM11
One end access power management chip UM2 the 2nd foot, the 3rd foot of other end access power management chip UM2, capacitance CM11
One end is simultaneously grounded, and the 5th foot of power management chip UM2 after series resistance RM14 by being grounded；Resistance RM13, resistance RM19, electricity
After hindering RM15 and capacitance CM13 parallel connections, the 4th foot of one end access power management chip UM2 of resistance RM13, other end access electricity
The STB ports of road plate, the collector of NPN transistor QM2 are connect with one end of resistance RM19, emitter and the one of capacitance CM13
End connects and is grounded, and ground level is connect with one end of resistance RM15, between the other end of resistance RM13 and the resistance RM19 other ends
Connect the other end access button PWR_ON/OFF_B of resistance a RM17, the capacitance CM13;Power management chip UM2's
6th foot output voltage is output to socket CN2 after being filtered over the ground by capacitance CM6 and capacitance CM51 parallel connections.
The mobile phone charge management circuit passes through capacitance including voltage management chip UD4, SYS_VCC normal DC voltage
CD2 and capacitance CD59 capacitance parallel connections are input to the 3rd feet of voltage management chip UD4, one end access of resistance RD27 after filtering over the ground
The 3rd foot of voltage management chip UD4, the other end are connect with the 5th foot of voltage management chip UD4 and one end of resistance RD28,
The other end of resistance RD28 is connect, and be grounded simultaneously with the 1st foot of voltage management chip UD4；Capacitance CD32 and voltage management
The 6th foot connection of chip UD4, the other end are connect with the 2nd foot of voltage management chip UD4 and one end of resonant inductance L4, should
The other end of resonant inductance L4 is connect with one end of capacitance CD38 and one end of resistance RD26, the other end and the electricity of capacitance CD38
Press one end connection of the 4th foot of managing chip UD4, one end of resistance RD29 and resistance RD30, the other end of resistance RD29 with
The other end connection of resistance RD26, the 2nd foot output voltage of voltage management chip UD4, voltage pass through capacitance CD33, capacitance CD34
And 12V/USB voltages are exported after polar capacitor ED4 parallel filterings, 12V/USB voltages are connected by socket CN1A with electric wire
The anode of socket CN1B, polar capacitor ED4 are connect with socket CN1A, and cathode ground connection, 12V/USB voltages are inputted by socket CN1B
To fuse F1,12V/USB voltages pass through inline fuse F1, then are filtered over the ground by polar capacitor CE1 and capacitance C1 parallel connections
It is input to the 4th foot of power management chip U3, the anode access fuse F1 and power management chip U3 of polar capacitor CE1 again afterwards
The 4th foot between, cathode ground connection；The 1st foot of power management chip U3 is connect with the 3rd foot of protocol chip U1, resonant inductance L2
One end connect with one end of the 5th foot of power management chip U3, the 6th foot and capacitance C7, the other end passes through resistance in parallel
It is being connected between the 2nd foot of power management chip U3 and the 3rd foot after R2 and resistance R7, the other end and the resistance R11 of capacitance C7
One end connection, the other end of resistance R11 is connected and is grounded with the 7th foot, the 3rd foot of power management chip U3, power management core
The voltage of piece U3 outputs is output to socket USB1, resistance R8 again after polar capacitor CE3 and capacitance C5 in parallel are filtered over the ground
One end connect with the anode of one end of resistance R2 and polar capacitor CE3, the other end passes through the resistance R9 of series connection ground connection, polarity
The cathode ground connection of capacitance CE3, one end of resistance R1 are connect with the anode of polar capacitor CE3 and socket USB1, other end access
The 5th foot of power management chip U3, one end ground connection of capacitance C6, the 5th foot and resistance of other end access power management chip U3
Between R1, the 1st foot, the 2nd foot and the 6th foot of power management chip U3 are connect with socket USB1, power management chip U3's
2nd foot is grounded simultaneously.
The battery charging management includes charging chip UD10, and DC power supply accesses P1 ports outside charging chip UD10,
The P1 ports access the drain electrode of metal-oxide-semiconductor QD7 by switching CN7, are grounded after the gate series resistance RD44 of metal-oxide-semiconductor QD7, source electrode
By the way that filtering exports DC_IN voltages over the ground after capacitance CD62, capacitance CD66 and capacitance CD47 in parallel；DC_IN voltage outputs are steady
Constant voltage is to metal-oxide-semiconductor QD4, and PDONOFF networks after series resistance RD52 with the base stage of triode QD6 by connecting, the triode
The collector of QD6 is connect by series resistance RD49 with one end of resistance RD40, one end of resistance RD42, the hair of triode QD6
Emitter grounding, one end of resistance RD42 are connect with the grid of one end of capacitance CD37 and metal-oxide-semiconductor QD4, the drain electrode of metal-oxide-semiconductor QD4
VCC_IN voltages, the other end of resistance RD40 and the other end of capacitance CD37 are exported after being filtered over the ground by shunt capacitance CD35
The source electrode of access metal-oxide-semiconductor QD4；After VCC_IN voltages access to the drain electrode of metal-oxide-semiconductor QD11, metal-oxide-semiconductor QD10, metal-oxide-semiconductor QD11,
The grid of metal-oxide-semiconductor QD10 accesses the 4th foot of charging chip UD10 by series resistance RD55, and the 3rd foot of charging chip UD10 leads to
Cross the source electrode and metal-oxide-semiconductor QD10 source electrodes of series resistance RD53 access metal-oxide-semiconductors QD11, drain electrode and the capacitance CD6 of metal-oxide-semiconductor QD11
One end connection, the other end ground connection of capacitance CD6, the 1st foot of charging chip UD10 and one end of capacitance CD84 and resistance
One end connection of RD81, the other end of resistance RD81 and the drain electrode of metal-oxide-semiconductor QD10, one end of capacitance CD83 and charging chip
The 2nd foot of UD10 is connected, the other end of capacitance CD83 and the other end ground connection of capacitance CD84, polar capacitor ED5 and capacitance
CD65 is in parallel, and the anode of polar capacitor and one end of resistance RD81, cathode ground connection, one end of capacitance CD65 is with metal-oxide-semiconductor QD12's
Drain electrode connection, the grid of metal-oxide-semiconductor QD12 access the 18th foot of charging chip UD10 by series resistance RD56, metal-oxide-semiconductor QD12's
Source electrode is connect with the drain electrode of metal-oxide-semiconductor QD13, and the grid of metal-oxide-semiconductor QD13 accesses charging chip UD10's by series resistance RD77
15th foot, the source electrode of metal-oxide-semiconductor QD13 and one end of one end of capacitance CD69, the 14th foot of charging chip UD10, capacitance CD68 connect
It connects and is grounded, the other end of capacitance CD68 is connect with resistance RD4, one end of the other end resonant inductance LD5 of resistance RD4, charging
One end connection of the 19th foot and capacitance CD64 of chip UD10, the 17th of the other end access charging chip UD10 of capacitance CD64 the
Foot；The other end of resonant inductance LD5 is connect with one end of resistance RD102, one end of resistance RD73, the other end of resistance RD102
It is connect with one end of capacitance CD86 and the 13rd foot of charging chip UD10,
It is grounded behind one end of the other end access capacitance CD87 of capacitance CD86, the other end and charging chip of capacitance CD87
One end connection of the 12nd foot and resistance RD103 of UD10, the other end of resistance RD103 are connect with the other end of resistance RD73,
Polar capacitor ED62, capacitance CD67 and capacitance CD57 are in parallel, the cathode ground connection of polar capacitor ED62, anode and resistance RD73
Other end connection, capacitance CD57 access BARRERY_OUT power supplys and give after mechanical switch CN61 and socket CNB1 successively
18650 battery packs charge；STB ports are accessed after the 10th foot series resistance RD71 of charging chip UD10；Charging chip
The 8th foot of UD10 by accessing SDA ports after series resistance RD50, the 9th foot by accessing SCL ports after series resistance RD86,
Capacitance CD49 is in parallel with capacitance CD70, between the 8th foot of one end access charging chip UD10 and resistance RD50 of capacitance CD49,
Between the 9th feet of one end access charging chip UD10 and resistance RD86 of capacitance CD70, capacitance CD49 and capacitance CD70's is another
End ground connection；The 6th foot of charging chip UD10 and one end of one end of capacitance CD85, one end of resistance RD66 and resistance RD78 connect
It connects, the other end of capacitance CD85 and the other end of resistance RD66 are grounded after being connect with one end of capacitance CD71, capacitance CD71's
The other end is connect with the 20th foot of power supply chip UD10, one end of resistance RD82, the other end and diode of resistance RD82
The cathode connection of DD61, wherein the anode access VCC_IN voltages of a diode DD61, the anode access of another diode DD61
18650 battery packs, the other end access VCC_IN voltages of resistance RD78.
5th, the multi-functional TV for being charged and discharged management system according to claim 1, which is characterized in that described
DC power supply management circuit include power management chip UD1, VCC_IN power supply accessed after CD42 capacitor filterings diode DD3 with
The anode of diode DD7 by diode DD3 and the cathode of diode DD7, and is output to SYS_ after passing through electrolytic capacitor ED2
VCC electric power networks, BARRERY_OUT power supplys by capacitance CD76 filter, by BARRERY_OUT power supplys connection diode DD4 and
The anode of diode DD8, BARRERY_OUT power supplys are output to SYS_VCC electric power networks by electrolytic capacitor ED2 filtering；SYS_
VCC voltages filter over the ground after in parallel capacitance CD4, capacitance CD8 and capacitance CD9, are input to the of power management chip UD1
4th, 5,6 foot, the 1st foot of power management chip UD1 and the 10th foot ground connection, one end of resistance RD2 is with power management chip UD1's
4th, 5, one end connection of 6 feet and resistance RD1, the other end and one end of resistance RD23, one end of resistance RD25, capacitance CD30
One end, power management chip UD1 the 10th, one end connections of 12 feet, one end of resistance RD18 and RD3, resistance RD23
Other end access EN ports, the other end of resistance RD3 connect and is grounded with one end of capacitance CD31, the other end of capacitance CD31
Access the 8th foot of power management chip UD1 and the other end of electronics RD18, the other end access power management chip of resistance RD1
The 11st foot of UD1, the 7th foot of one end access power management chip UD1 of capacitance CD3, the one of other end access resonant inductance LD6
End and the 2nd foot of power management chip UD1, the other end of resonant inductance LD6 and one end of capacitance CD27, the one of resistance RD11
End connection, the 9th foot of the other end access power management chip UD1 of capacitance CD27, the other end and resistance of resistance RD11
One end connection of RD24, the other end ground connection of resistance RD24, SYS_VCC voltages pass through shunt capacitance CD18, capacitance CD19, capacitance
The 12V voltages of CD20 and electrolytic capacitor ED3 filtering outputting standards.
The utility model has the advantages that：It is not influenced and limitation by mains-supplied, it is unstable, tight in power failure or mains-supplied
In the case of lacking, product can use solar energy, and wind-power electricity generation group waits external DC power supply to charge to electrical appliance, so as to
To maintain normal work certain time using electrical appliance internal battery.This product can be in mains-supplied, automatically to electricity simultaneously
The charging of side working edge, and meeting automatic cut-off battery discharge are supported in pond group charging, can also to ensure the service life of battery
Support standby charging.In the case where not influencing electrical appliance normal operation, by LED illumination System, mobile phone quick charging system, battery
Three kinds of functions of group charging are integrated, and are integrated into inside television set, allow client that can enjoy multi-functional charging on a television set
With the function of discharge system.
Description of the drawings
Fig. 1 is the agent structure block diagram of the utility model.
Fig. 2 is LED illumination management circuit diagram.
Fig. 3 is mobile phone charge management circuit figure.
Fig. 4 is battery charging management circuit figure.
Fig. 5 is DC power supply management circuit diagram.
Specific embodiment
The utility model is further described with reference to specific embodiment, and the advantages of the utility model and feature will be with
Description and it is apparent.But these embodiments are only exemplary, do not form any restrictions to the scope of the utility model.
It it will be understood by those skilled in the art that can be to the utility model skill under the spirit and scope without departing from the utility model
The details and form of art scheme are modified or are replaced, but these modifications and replacement each fall within the scope of protection of the utility model
It is interior.
It is described the utility model is related to a kind of multi-functional TV for being charged and discharged management system referring to Fig. 1 to Fig. 5
TV driving plate is provided in TV, which manages circuit drives LED light by LED illumination and illuminate, and passes through mobile phone
Charge management circuit charges to mobile phone, is charged by battery charging management circuit to 18650 battery packs, and electricity is managed by DC power supply
Road drives liquid crystal display module and loudspeaker.
The LED illumination management circuit is filtered including power management chip UM1,12V normal DC voltages by capacitance CM7
It is input to the 1st foot of power management chip UM1, the 2nd foot of one end access power management chip UM1 of capacitance CM8, the other end afterwards
The 3rd foot of access power management chip UM1, one end of capacitance CM7 and ground connection, the 5th foot of power management chip UM1 pass through series connection
It is grounded after resistance RM10；After resistance RM9, resistance RM18, resistance RM11 and capacitance CM9 parallel connections, one end access power supply of resistance RM9
The 4th foot of managing chip UM1, the other end access the STB ports of circuit board, collector and the resistance RM18 of NPN transistor QM1
One end connection, emitter connect and is grounded with one end of capacitance CM9, and ground level is connect with one end of resistance RM11, in resistance RM9
The other end and the resistance RM18 other ends between connect resistance a RM12, the capacitance CM9 the other end access button
PWR_ON/OFF_A;The 6th foot output voltage of power management chip UM1 is filtered over the ground by capacitance CM6 and capacitance CM51 parallel connections
After be output to socket CN2；
12V normal DC voltages are input to the 1st foot of power management chip UM2, capacitance CM12 after being filtered by capacitance CM11
One end access power management chip UM2 the 2nd foot, the 3rd foot of other end access power management chip UM2, capacitance CM11
One end is simultaneously grounded, and the 5th foot of power management chip UM2 after series resistance RM14 by being grounded；Resistance RM13, resistance RM19, electricity
After hindering RM15 and capacitance CM13 parallel connections, the 4th foot of one end access power management chip UM2 of resistance RM13, other end access electricity
The STB ports of road plate, the collector of NPN transistor QM2 are connect with one end of resistance RM19, emitter and the one of capacitance CM13
End connects and is grounded, and ground level is connect with one end of resistance RM15, between the other end of resistance RM13 and the resistance RM19 other ends
Connect the other end access button PWR_ON/OFF_B of resistance a RM17, the capacitance CM13;Power management chip UM2's
6th foot output voltage is output to socket CN2 after being filtered over the ground by capacitance CM6 and capacitance CM51 parallel connections.
The mobile phone charge management circuit passes through capacitance including voltage management chip UD4, SYS_VCC normal DC voltage
CD2 and capacitance CD59 capacitance parallel connections are input to the 3rd feet of voltage management chip UD4, one end access of resistance RD27 after filtering over the ground
The 3rd foot of voltage management chip UD4, the other end are connect with the 5th foot of voltage management chip UD4 and one end of resistance RD28,
The other end of resistance RD28 is connect, and be grounded simultaneously with the 1st foot of voltage management chip UD4；Capacitance CD32 and voltage management
The 6th foot connection of chip UD4, the other end are connect with the 2nd foot of voltage management chip UD4 and one end of resonant inductance L4, should
The other end of resonant inductance L4 is connect with one end of capacitance CD38 and one end of resistance RD26, the other end and the electricity of capacitance CD38
Press one end connection of the 4th foot of managing chip UD4, one end of resistance RD29 and resistance RD30, the other end of resistance RD29 with
The other end connection of resistance RD26, the 2nd foot output voltage of voltage management chip UD4, voltage pass through capacitance CD33, capacitance CD34
And 12V/USB voltages are exported after polar capacitor ED4 parallel filterings, 12V/USB voltages are connected by socket CN1A with electric wire
The anode of socket CN1B, polar capacitor ED4 are connect with socket CN1A, and cathode ground connection, 12V/USB voltages are inputted by socket CN1B
To fuse F1,12V/USB voltages pass through inline fuse F1, then are filtered over the ground by polar capacitor CE1 and capacitance C1 parallel connections
It is input to the 4th foot of power management chip U3, the anode access fuse F1 and power management chip U3 of polar capacitor CE1 again afterwards
The 4th foot between, cathode ground connection；The 1st foot of power management chip U3 is connect with the 3rd foot of protocol chip U1, resonant inductance L2
One end connect with one end of the 5th foot of power management chip U3, the 6th foot and capacitance C7, the other end passes through resistance in parallel
It is being connected between the 2nd foot of power management chip U3 and the 3rd foot after R2 and resistance R7, the other end and the resistance R11 of capacitance C7
One end connection, the other end of resistance R11 is connected and is grounded with the 7th foot, the 3rd foot of power management chip U3, power management core
The voltage of piece U3 outputs is output to socket USB1, resistance R8 again after polar capacitor CE3 and capacitance C5 in parallel are filtered over the ground
One end connect with the anode of one end of resistance R2 and polar capacitor CE3, the other end passes through the resistance R9 of series connection ground connection, polarity
The cathode ground connection of capacitance CE3, one end of resistance R1 are connect with the anode of polar capacitor CE3 and socket USB1, other end access
The 5th foot of power management chip U3, one end ground connection of capacitance C6, the 5th foot and resistance of other end access power management chip U3
Between R1, the 1st foot, the 2nd foot and the 6th foot of power management chip U3 are connect with socket USB1, power management chip U3's
2nd foot is grounded simultaneously.
12V/USB voltages pass through inline fuse, after being filtered over the ground by polar capacitor CE1 and capacitance C1 capacitance parallel connections again
The 4th feet of power management chip U3 are input to, by by being connected on power management after resonant inductance L2, parallel resistance R2 and resistance R7
Between the 2nd foot of chip UM2 and the 3rd foot, output current is detected by sampling between the 2nd foot and the 3rd foot pressure difference, capacitance C7 and
The electric power management circuit that resistance R11 is formed by resistance R8 series resistance R9, forms voltage feedback circuit, feedback voltage is by agreement
(QC3.0 protocol chips provide chip U1）, after protocol chip U1 provides feedback voltage, the voltage warp of power management chip U3 outputs
It crosses after CE3 and C5 capacitance parallel connections filter over the ground and is output to USB1 again, mobile phone is charged by USB1 sockets.There are QC3.0 agreements
Mobile phone charging will export Q3.0 voltage protocols;No QC3.0 agreements mobile phone charging, by outputting standard 5V voltages.
The battery charging management includes charging chip UD10, and DC power supply accesses P1 ports outside charging chip UD10,
The P1 ports access the drain electrode of metal-oxide-semiconductor QD7 by switching CN7, are grounded after the gate series resistance RD44 of metal-oxide-semiconductor QD7, source electrode
By the way that filtering exports DC_IN voltages over the ground after capacitance CD62, capacitance CD66 and capacitance CD47 in parallel；DC_IN voltage outputs are steady
Constant voltage is to metal-oxide-semiconductor QD4, and PDONOFF networks after series resistance RD52 with the base stage of triode QD6 by connecting, the triode
The collector of QD6 is connect by series resistance RD49 with one end of resistance RD40, one end of resistance RD42, the hair of triode QD6
Emitter grounding, one end of resistance RD42 are connect with the grid of one end of capacitance CD37 and metal-oxide-semiconductor QD4, the drain electrode of metal-oxide-semiconductor QD4
VCC_IN voltages, the other end of resistance RD40 and the other end of capacitance CD37 are exported after being filtered over the ground by shunt capacitance CD35
The source electrode of access metal-oxide-semiconductor QD4；After VCC_IN voltages access to the drain electrode of metal-oxide-semiconductor QD11, metal-oxide-semiconductor QD10, metal-oxide-semiconductor QD11,
The grid of metal-oxide-semiconductor QD10 accesses the 4th foot of charging chip UD10 by series resistance RD55, and the 3rd foot of charging chip UD10 leads to
Cross the source electrode and metal-oxide-semiconductor QD10 source electrodes of series resistance RD53 access metal-oxide-semiconductors QD11, drain electrode and the capacitance CD6 of metal-oxide-semiconductor QD11
One end connection, the other end ground connection of capacitance CD6, the 1st foot of charging chip UD10 and one end of capacitance CD84 and resistance
One end connection of RD81, the other end of resistance RD81 and the drain electrode of metal-oxide-semiconductor QD10, one end of capacitance CD83 and charging chip
The 2nd foot of UD10 is connected, the other end of capacitance CD83 and the other end ground connection of capacitance CD84, polar capacitor ED5 and capacitance
CD65 is in parallel, and the anode of polar capacitor and one end of resistance RD81, cathode ground connection, one end of capacitance CD65 is with metal-oxide-semiconductor QD12's
Drain electrode connection, the grid of metal-oxide-semiconductor QD12 access the 18th foot of charging chip UD10 by series resistance RD56, metal-oxide-semiconductor QD12's
Source electrode is connect with the drain electrode of metal-oxide-semiconductor QD13, and the grid of metal-oxide-semiconductor QD13 accesses charging chip UD10's by series resistance RD77
15th foot, the source electrode of metal-oxide-semiconductor QD13 and one end of one end of capacitance CD69, the 14th foot of charging chip UD10, capacitance CD68 connect
It connects and is grounded, the other end of capacitance CD68 is connect with resistance RD4, one end of the other end resonant inductance LD5 of resistance RD4, charging
One end connection of the 19th foot and capacitance CD64 of chip UD10, the 17th of the other end access charging chip UD10 of capacitance CD64 the
Foot；The other end of resonant inductance LD5 is connect with one end of resistance RD102, one end of resistance RD73, the other end of resistance RD102
It is connect with one end of capacitance CD86 and the 13rd foot of charging chip UD10,
It is grounded behind one end of the other end access capacitance CD87 of capacitance CD86, the other end and charging chip of capacitance CD87
One end connection of the 12nd foot and resistance RD103 of UD10, the other end of resistance RD103 are connect with the other end of resistance RD73,
Polar capacitor ED62, capacitance CD67 and capacitance CD57 are in parallel, the cathode ground connection of polar capacitor ED62, anode and resistance RD73
Other end connection, capacitance CD57 access BARRERY_OUT power supplys and give after mechanical switch CN61 and socket CNB1 successively
18650 battery packs charge；STB ports are accessed after the 10th foot series resistance RD71 of charging chip UD10；Charging chip
The 8th foot of UD10 by accessing SDA ports after series resistance RD50, the 9th foot by accessing SCL ports after series resistance RD86,
Capacitance CD49 is in parallel with capacitance CD70, between the 8th foot of one end access charging chip UD10 and resistance RD50 of capacitance CD49,
Between the 9th feet of one end access charging chip UD10 and resistance RD86 of capacitance CD70, capacitance CD49 and capacitance CD70's is another
End ground connection；The 6th foot of charging chip UD10 and one end of one end of capacitance CD85, one end of resistance RD66 and resistance RD78 connect
It connects, the other end of capacitance CD85 and the other end of resistance RD66 are grounded after being connect with one end of capacitance CD71, capacitance CD71's
The other end is connect with the 20th foot of power supply chip UD10, one end of resistance RD82, the other end and diode of resistance RD82
The cathode connection of DD61, wherein the anode access VCC_IN voltages of a diode DD61, the anode access of another diode DD61
18650 battery packs, the other end access VCC_IN voltages of resistance RD78.
PDONOFF networks provide high level and form switching circuit by RD52 resistance, triode QD6, reversely export low level,
Series resistance RD49, resistance RD42 Current limited Control metal-oxide-semiconductor QD4, by resistance RD40 and capacitance CD37 Parallel Control sequential so that
Metal-oxide-semiconductor QD4 conducting output VCC_IN voltages.VCC_IN control sources metal-oxide-semiconductor QD11, metal-oxide-semiconductor QD11 are by UD10 charging chip controls
System, the circuit output that battery charging voltage is passed through by resistance RD4, capacitance CD68 and resonant inductance LD5 is formed, battery charging voltage
By series limiting resistor RD73 and electrolytic capacitor ED62, capacitance CD67 and capacitance CD57 form electric source filter circuit output,
Mechanical switch CN61 is connected, is charged by socket CNB1 to 18650 battery packs.Occur filling under two states in charging process
Electricity instruction prompting, state 1:Electrical appliance is opened, will appear the lightning icon prompting of charging on the screen, charging saturation equally also can
There is the icon prompting of charging saturation.State 2:Electrical appliance is closed, the LED light that charging is will appear in electrical appliance shell carries
Show, charge saturation charge closing indicator light, opens saturation indicator light.
The DC power supply management circuit includes power management chip UD1, VCC_IN power supply after CD42 capacitor filterings
The anode of diode DD3 and diode DD7 is accessed, by diode DD3 and the cathode of diode DD7, and passes through electrolytic capacitor
SYS_VCC electric power networks are output to after ED2, BARRERY_OUT power supplys are filtered by capacitance CD76, by BARRERY_OUT power supplys
The anode of diode DD4 and diode DD8 is connected, BARRERY_OUT power supplys are output to SYS_ by electrolytic capacitor ED2 filtering
VCC electric power networks；SYS_VCC voltages filter over the ground after capacitance CD4, capacitance CD8 and capacitance CD9 in parallel, are input to electricity
Source control chip UD1 the 4th, 5,6 feet, the 1st foot of power management chip UD1 and the 10th foot ground connection, one end of resistance RD2 with
Power management chip UD1 the 4th, 5, one end connection of 6 feet and resistance RD1, one end with resistance RD23 of the other end, resistance
One end of RD25, one end of capacitance CD30, the 10th of power management chip UD1 the, 12 feet, one end of resistance RD18 and RD3
One end connects, and the other end access EN ports of resistance RD23, the other end of resistance RD3 connect and connects with one end of capacitance CD31
Ground, the 8th foot of other end access power management chip UD1 of capacitance CD31 and the other end of electronics RD18, resistance RD1's is another
Terminate the 11st foot into power management chip UD1, the 7th foot of one end access power management chip UD1 of capacitance CD3, the other end
Access one end of resonant inductance LD6 and the 2nd foot of power management chip UD1, the other end and the capacitance CD27 of resonant inductance LD6
One end, resistance RD11 one end connection, the 9th foot, the resistance RD11 of the other end access power management chip UD1 of capacitance CD27
The other end and resistance RD24 one end connection, the other end ground connection of resistance RD24, SYS_VCC voltages pass through shunt capacitance
CD18, capacitance CD19, capacitance CD20 and electrolytic capacitor ED3 filter the 12V voltages of outputting standard.
SYS_VCC electric power networks are made of the partial pressure of power management chip UD1 switch control feet resistance RD2, resistance RD25
Circuit, electronics R23 and capacitance CD30 respectively constitute power management chip UD1 switches control foot current-limiting resistance and filter circuit.Electricity
Resistance RD3, resistance RD18 and capacitance CD31 form power management chip UD1 management accountings and sequence circuit, SYS_VCC voltages pass through
Power management chip UD1 carries out processing output voltage, and voltage passes through capacitance CD18, capacitance CD19, capacitance CD20 and electrolytic capacitor
The 12V voltages of ED3 parallel filtering outputting standards.
Claims (5)
1. the multi-functional TV for being charged and discharged management system, which is characterized in that TV driving plate is provided in the TV,
The TV driving plate manages circuit drives LED light by LED illumination and illuminates, and is charged by mobile phone charge management circuit to mobile phone,
It is charged by battery charging management circuit to 18650 battery packs, circuit drives liquid crystal display module and loudspeaker is managed by DC power supply.
2. the multi-functional TV for being charged and discharged management system according to claim 1, which is characterized in that the LED
Illumination supervision circuit includes being input to power management after power management chip UM1,12V normal DC voltages are filtered by capacitance CM7
The 1st foot of chip UM1, the 2nd foot of one end access power management chip UM1 of capacitance CM8, other end access power management chip
The 3rd foot of UM1, one end of capacitance CM7 and ground connection, the 5th foot of power management chip UM1 after series resistance RM10 by being grounded；
After resistance RM9, resistance RM18, resistance RM11 and capacitance CM9 parallel connections, the of one end of resistance RM9 access power management chip UM1
4 feet, the other end access the STB ports of circuit board, and the collector of NPN transistor QM1 is connect with one end of resistance RM18, emit
Pole connect and is grounded with one end of capacitance CM9, and ground level is connect with one end of resistance RM11, in the other end and resistance of resistance RM9
Connect the other end access button PWR_ON/OFF_A of resistance a RM12, the capacitance CM9 between the RM18 other ends;Power supply
The 6th foot output voltage of managing chip UM1 is output to socket CN2 after being filtered over the ground by capacitance CM6 and capacitance CM51 parallel connections；
12V normal DC voltages are input to the 1st foot of power management chip UM2 after being filtered by capacitance CM11, and the one of capacitance CM12
Terminate the 2nd foot into power management chip UM2, the 3rd foot of other end access power management chip UM2, one end of capacitance CM11
And be grounded, the 5th foot of power management chip UM2 after series resistance RM14 by being grounded；Resistance RM13, resistance RM19, resistance
After RM15 and capacitance CM13 parallel connections, the 4th foot of one end access power management chip UM2 of resistance RM13, other end access circuit
The STB ports of plate, the collector of NPN transistor QM2 are connect with one end of resistance RM19, one end of emitter and capacitance CM13
It connects and is grounded, ground level is connect with one end of resistance RM15, is gone here and there between the other end of resistance RM13 and the resistance RM19 other ends
Join the other end access button PWR_ON/OFF_B of resistance a RM17, the capacitance CM13;The of power management chip UM2
6 foot output voltages are output to socket CN2 after being filtered over the ground by capacitance CM6 and capacitance CM51 parallel connections.
3. the multi-functional TV for being charged and discharged management system according to claim 1, which is characterized in that the mobile phone
Charge management circuit includes voltage management chip UD4, SYS_VCC normal DC voltage by capacitance CD2 and capacitance CD59 capacitances simultaneously
Connection is input to the 3rd feet of voltage management chip UD4 after filtering over the ground, one end of resistance RD27 accesses the 3rd of voltage management chip UD4 the
Foot, the other end are connect with the 5th foot of voltage management chip UD4 and one end of resistance RD28, the other end of resistance RD28 with
The 1st foot connection of voltage management chip UD4, and be grounded simultaneously；Capacitance CD32 is connect with the 6th foot of voltage management chip UD4, separately
One end is connect with the 2nd foot of voltage management chip UD4 and one end of resonant inductance L4, the other end and the electricity of resonant inductance L4
One end of appearance CD38 and one end connection of resistance RD26, the other end of capacitance CD38 and the 4th foot of voltage management chip UD4,
One end of resistance RD29 and one end connection of resistance RD30, the other end of resistance RD29 are connect with the other end of resistance RD26,
The 2nd foot output voltage of voltage management chip UD4, voltage are in parallel by capacitance CD33, capacitance CD34 and polar capacitor ED4
12V/USB voltages are exported after filtering, 12V/USB voltages connect socket CN1B, polar capacitor ED4 by socket CN1A electric wires
Anode connect with socket CN1A, cathode ground connection, 12V/USB voltages by socket CN1B be input to fuse F1,12V/USB electricity
Pressure is by inline fuse F1, then is input to power management core again after being filtered over the ground by polar capacitor CE1 and capacitance C1 parallel connections
The 4th foot of piece U3, the anode of polar capacitor CE1 are accessed between the 4th foot of fuse F1 and power management chip U3, and cathode connects
Ground；The 1st foot of power management chip U3 is connect with the 3rd foot of protocol chip U1, one end and the power management core of resonant inductance L2
One end connection of the 5th foot of piece U3, the 6th foot and capacitance C7, the other end after resistance R2 and resistance R7 in parallel by connecting
Between the 2nd foot of power management chip U3 and the 3rd foot, the other end of capacitance C7 is connect with one end of resistance R11, resistance R11
The other end be connected and be grounded with the 7th foot, the 3rd foot of power management chip U3, power management chip U3 output voltage pass through
Polar capacitor CE3 and capacitance C5 in parallel is output to socket USB1, one end of resistance R8 and the one of resistance R2 again after filtering over the ground
The connection of the anode of end and polar capacitor CE3, the other end are grounded by the resistance R9 of series connection, the cathode ground connection of polar capacitor CE3,
One end of resistance R1 is connect with the anode and socket USB1 of polar capacitor CE3, and the 5th of other end access power management chip U3 the
Foot, one end ground connection of capacitance C6, between the 5th foot of other end access power management chip U3 and resistance R1, power management chip
The 1st foot, the 2nd foot and the 6th foot of U3 is connect with socket USB1, and the 2nd foot of power management chip U3 is grounded simultaneously.
4. the multi-functional TV for being charged and discharged management system according to claim 1, which is characterized in that the battery
Charge Management includes charging chip UD10, and DC power supply accesses P1 ports outside charging chip UD10, and the P1 ports are by switching CN7
Access the drain electrode of metal-oxide-semiconductor QD7, be grounded after the gate series resistance RD44 of metal-oxide-semiconductor QD7, source electrode by capacitance CD62 in parallel,
Filtering exports DC_IN voltages over the ground after capacitance CD66 and capacitance CD47；DC_IN voltage outputs burning voltage to metal-oxide-semiconductor QD4,
For PDONOFF networks by being connect after series resistance RD52 with the base stage of triode QD6, the collector of triode QD6 passes through string
Connection resistance RD49 is connect with one end of resistance RD40, one end of resistance RD42, the emitter ground connection of triode QD6, resistance RD42
One end connect with the grid of one end of capacitance CD37 and metal-oxide-semiconductor QD4, the drain electrode of metal-oxide-semiconductor QD4 passes through CD35 pairs of shunt capacitance
VCC_IN voltages are exported after ground filtering, the other end of resistance RD40 and the other end of capacitance CD37 access the source of metal-oxide-semiconductor QD4
Pole；After VCC_IN voltages access to the drain electrode of metal-oxide-semiconductor QD11, metal-oxide-semiconductor QD10, metal-oxide-semiconductor QD11, metal-oxide-semiconductor QD10 grid pass through
The 4th foot of series resistance RD55 access charging chips UD10, the 3rd foot of charging chip UD10 are accessed by series resistance RD53
The source electrode of metal-oxide-semiconductor QD11 and metal-oxide-semiconductor QD10 source electrodes, the drain electrode of metal-oxide-semiconductor QD11 are connect with one end of capacitance CD6, capacitance CD6
Other end ground connection, the 1st foot of charging chip UD10 connect with one end of capacitance CD84 and one end of resistance RD81, resistance
The other end of RD81 is connected with the 2nd foot of the drain electrode of metal-oxide-semiconductor QD10, one end of capacitance CD83 and charging chip UD10, capacitance
The other end of CD83 and the other end ground connection of capacitance CD84, polar capacitor ED5 is in parallel with capacitance CD65, the anode of polar capacitor
With one end of resistance RD81, cathode ground connection, one end of capacitance CD65 is connect with the drain electrode of metal-oxide-semiconductor QD12, the grid of metal-oxide-semiconductor QD12
The 18th foot of charging chip UD10 is accessed by series resistance RD56, the source electrode of metal-oxide-semiconductor QD12 connects with the drain electrode of metal-oxide-semiconductor QD13
It connects, the grid of metal-oxide-semiconductor QD13 accesses the 15th foot of charging chip UD10, the source electrode of metal-oxide-semiconductor QD13 by series resistance RD77
It connect and is grounded with one end of one end of capacitance CD69, the 14th foot of charging chip UD10, capacitance CD68, capacitance CD68's is another
End is connect with resistance RD4, one end of other end resonant inductance LD5, the 19th foot of charging chip UD10 and the capacitance of resistance RD4
One end connection of CD64, the 17th foot of the other end access charging chip UD10 of capacitance CD64；The other end of resonant inductance LD5 with
One end of resistance RD102, one end connection of resistance RD73, the other end of resistance RD102 and one end of capacitance CD86 and charging
The 13rd foot connection of chip UD10,
It is grounded behind one end of the other end access capacitance CD87 of capacitance CD86, the other end and the charging chip UD10 of capacitance CD87
The 12nd foot and resistance RD103 one end connection, the other end of resistance RD103 connect with the other end of resistance RD73, polarity
Capacitance ED62, capacitance CD67 and capacitance CD57 are in parallel, the cathode ground connection of polar capacitor ED62, and anode is another with resistance RD73's
One end connects, capacitance CD57 access BARRERY_OUT power supplys, and is given after mechanical switch CN61 and socket CNB1 successively
18650 battery packs charge；STB ports are accessed after the 10th foot series resistance RD71 of charging chip UD10；Charging chip
The 8th foot of UD10 by accessing SDA ports after series resistance RD50, the 9th foot by accessing SCL ports after series resistance RD86,
Capacitance CD49 is in parallel with capacitance CD70, between the 8th foot of one end access charging chip UD10 and resistance RD50 of capacitance CD49,
Between the 9th feet of one end access charging chip UD10 and resistance RD86 of capacitance CD70, capacitance CD49 and capacitance CD70's is another
End ground connection；The 6th foot of charging chip UD10 and one end of one end of capacitance CD85, one end of resistance RD66 and resistance RD78 connect
It connects, the other end of capacitance CD85 and the other end of resistance RD66 are grounded after being connect with one end of capacitance CD71, capacitance CD71's
The other end is connect with the 20th foot of power supply chip UD10, one end of resistance RD82, the other end and diode of resistance RD82
The cathode connection of DD61, wherein the anode access VCC_IN voltages of a diode DD61, the anode access of another diode DD61
18650 battery packs, the other end access VCC_IN voltages of resistance RD78.
5. the multi-functional TV for being charged and discharged management system according to claim 1, which is characterized in that the DC electricity
Power management circuits access diode DD3 and two poles including power management chip UD1, VCC_IN power supply after CD42 capacitor filterings
The anode of pipe DD7 by diode DD3 and the cathode of diode DD7, and is output to SYS_VCC electricity after passing through electrolytic capacitor ED2
Source network, BARRERY_OUT power supplys are filtered by capacitance CD76, and BARRERY_OUT power supplys are connected diode DD4 and diode
The anode of DD8, BARRERY_OUT power supplys are output to SYS_VCC electric power networks by electrolytic capacitor ED2 filtering；SYS_VCC voltages
It is filtered over the ground after capacitance CD4, capacitance CD8 and capacitance CD9 in parallel, is input to the 4th, 5, the 6 of power management chip UD1
Foot, the 1st foot of power management chip UD1 and the 10th foot ground connection, one end of resistance RD2 with the 4th of power management chip UD1 the,
5th, one end of 6 feet and resistance RD1 connect, the other end and one end of resistance RD23, one end of resistance RD25, capacitance CD30 one
End, the 10th of power management chip UD1 the, one end connections of 12 feet, one end of resistance RD18 and RD3, resistance RD23's is another
One end access EN ports, the other end of resistance RD3 connect and are grounded with one end of capacitance CD31, the other end access of capacitance CD31
The 8th foot of power management chip UD1 and the other end of electronics RD18, the other end access power management chip UD1's of resistance RD1
11st foot, the 7th foot of one end access power management chip UD1 of capacitance CD3, one end of other end access resonant inductance LD6 with
And the 2nd foot of power management chip UD1, the other end of resonant inductance LD6 and one end of one end of capacitance CD27, resistance RD11 connect
It connects, the other end of capacitance CD27 accesses the 9th foot of power management chip UD1, the other end of resistance RD11 and resistance RD24
One end connects, the other end of resistance RD24 ground connection, SYS_VCC voltages by shunt capacitance CD18, capacitance CD19, capacitance CD20 and
Electrolytic capacitor ED3 filters the 12V voltages of outputting standard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201721723408.7U CN207603788U (en) | 2017-12-12 | 2017-12-12 | The multi-functional TV for being charged and discharged management system |
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| CN201721723408.7U CN207603788U (en) | 2017-12-12 | 2017-12-12 | The multi-functional TV for being charged and discharged management system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107770464A (en) * | 2017-12-12 | 2018-03-06 | 铭薪电子（深圳）有限公司 | The multi-functional TV for being charged and discharged management system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107770464A (en) * | 2017-12-12 | 2018-03-06 | 铭薪电子（深圳）有限公司 | The multi-functional TV for being charged and discharged management system |
| CN107770464B (en) * | 2017-12-12 | 2024-02-06 | 惠州铭薪电子有限公司 | Television with multifunctional charge and discharge management system |
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