CN207369020U - A kind of radio frequency front end chip - Google Patents
A kind of radio frequency front end chip Download PDFInfo
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Abstract
The utility model embodiment discloses a kind of radio frequency front end chip.Wherein radio frequency front end chip includes：Variable gain amplifier, indicating circuit, analog demodulator and control circuit；Variable gain amplifier, for input radio frequency signal to be carried out signal amplification, and outgoing carrier signal according to current gain；Indicating circuit, is electrically connected with variable gain amplifier and control circuit respectively, generates indication signal for extracting the first voltage of carrier signal, and according to first voltage and internal reference voltage, and indication signal is sent to control circuit；Analog demodulator, is electrically connected with variable gain amplifier and control circuit；Control circuit, is electrically connected with variable gain amplifier, for generating gain-adjusted signal according to indication signal, and gain-adjusted signal is sent to variable gain amplifier.Improve receiving sensitivity and antijamming capability of the radio frequency front end chip to radiofrequency signal.
Description
Technical Field
The embodiment of the utility model provides a relate to wireless communication technology, especially relate to a radio frequency front end chip.
Background
With the continuous development of wireless Communication technology, the application of the payment mode of NFC (Near Field Communication) is more and more extensive, and an NFC front-end chip is integrated in an intelligent terminal such as a smart phone and a smart band, so that the intelligent terminal has functions of NFC payment and the like, and the convenience of user payment is improved.
However, when the rf front-end chip is disposed in the intelligent terminal, since the signal shielding in the intelligent terminal is more serious than that of a normal rf tag, and the antenna miniaturization problem in the terminal causes the current rf front-end chip to be integrated in the intelligent terminal, the sensitivity is low, and the requirements of users for payment and the like cannot be met.
SUMMERY OF THE UTILITY MODEL
The utility model provides a radio frequency front end chip to realize improving radio frequency front end chip's sensitivity.
In a first aspect, an embodiment of the present invention provides a radio frequency front end chip, the radio frequency front end chip includes a variable gain amplifier, an indication circuit, an analog demodulator and a control circuit: wherein,
the variable gain amplifier is used for amplifying an input radio frequency signal according to the current gain and outputting a carrier signal;
the indicating circuit is respectively electrically connected with the variable gain amplifier and the control circuit and is used for extracting a first voltage of the carrier signal, generating an indicating signal according to the first voltage and an internal reference voltage and sending the indicating signal to the control circuit;
the analog demodulator is electrically connected with the variable gain amplifier and the control circuit and used for analyzing the carrier signal and sending a generated analysis instruction to the control circuit;
the control circuit is electrically connected with the variable gain amplifier, and is used for generating a gain adjusting signal according to the indication signal and sending the gain adjusting signal to the variable gain amplifier so that the variable gain amplifier adjusts the current gain and performs signal amplification on the input radio frequency signal according to the adjusted current gain, and is also used for generating a return parameter according to a corresponding analysis instruction when the indication signal meets a preset condition.
Furthermore, the device also comprises an active amplifying circuit; wherein,
the control circuit is electrically connected with the active amplification circuit and is further used for generating a state control signal according to the indication signal, receiving a clock signal sent by the active amplification circuit and generating return data according to a return parameter and the clock signal when the indication signal meets a preset condition;
the active amplification circuit is electrically connected with the variable gain amplifier and used for switching working states according to the state control signal, amplifying a signal according to a clock signal corresponding to the carrier signal and a modulation signal generated by the return data in an enabling state, and generating an output radio frequency signal, wherein the working states comprise an enabling state and a suspending state.
Further, the active amplification circuit comprises a clock data recovery module, a data synchronization module and an amplifier, wherein,
the clock data recovery module is respectively electrically connected with the variable gain amplifier and the control circuit, and is used for receiving the state control signal, switching the working state according to the state control signal, extracting the clock signal of the carrier signal in the enabled state, sending the clock signal to the control circuit, and generating an amplifier control signal homologous to the clock signal;
the control circuit is specifically configured to generate the return data according to the clock signal and the return parameter;
the data synchronization module is respectively electrically connected with the clock data recovery module and the control circuit and is used for synchronizing the clock signal and the return data to generate the modulation signal;
the amplifier is respectively and electrically connected with the clock data recovery module and the data synchronization module, and is used for amplifying the modulation signal, generating the output radio frequency signal, and dissipating energy after the output radio frequency signal is output according to the amplifier control signal.
Further, the radio frequency front-end chip also comprises a private GPIO interface; wherein,
the private GPIO interface is respectively connected with the control circuit and the external security module and is used for transmitting the analysis instruction to the external security module so that the external security module can carry out security verification on the analysis instruction and transmit feedback information of the external security module to the control circuit;
the control circuit is further configured to generate a return parameter according to the corresponding analysis instruction when the feedback information of the external security module is successfully verified, and discard the analysis instruction when the feedback information of the external security module is unsuccessfully verified.
Furthermore, the coding mode of the private GPIO interface is an NRZ coding mode with a start/stop bit.
Further, the communication transmission between the private GPIO interface and the external security module employs a multi-channel transmission channel, and the communication protocol of the private GPIO interface employs a master-slave half-duplex communication mode, where the external security module is a host end of communication, and the radio frequency front-end chip is a slave end of communication.
Further, the baud rate of the private GPIO interface communication protocol is set to a preset frequency division, where the preset frequency division is less than or equal to 372 frequency division and greater than or equal to 7 frequency division.
The embodiment of the utility model provides a compare through indicating circuit with the internal reference voltage the first voltage of confirming the carrier signal after variable gain amplifier enlargies, generate the regulation pilot signal of variable gain amplifier's regulation for control circuit control variable gain amplifier control and the gain of amplifying of adjusting variable gain amplifier, the realization is to the suitable gain of amplifying of the input radio frequency signal determination of equidimension not, has improved radio frequency front end chip to radio frequency signal's receiving sensitivity and interference killing feature.
Drawings
Fig. 1 is a schematic structural diagram of a radio frequency front end chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a radio frequency front end chip according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an encoding manner of the private GPIO interface according to an embodiment of the present invention;
fig. 4 is a schematic transmission diagram of a radio frequency front-end chip and an external security module according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a transmission signal according to an embodiment of the present invention;
fig. 6 is a flowchart of a method for processing a radio frequency signal according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic structural diagram of a radio frequency front end chip provided in an embodiment of the present invention, which can be integrated in an intelligent terminal such as a smart phone, a bracelet or a smart watch, and as a radio frequency analog tag, implement a secure and reliable NFC (Near Field Communication) payment function.
Referring to fig. 1, the rf front-end chip specifically includes a variable gain amplifier 110, an indication circuit 120, an analog demodulator 130, and a control circuit 140; wherein,
a variable gain amplifier 110 for amplifying an input radio frequency signal according to a current gain and outputting a carrier signal;
an indication circuit 120 electrically connected to the variable gain amplifier 110 and the control circuit, respectively, for extracting a first voltage of the carrier signal, generating an indication signal according to the first voltage and the internal reference voltage, and sending the indication signal to the control circuit;
an analog demodulator 130 electrically connected to the variable gain amplifier 110 and the control circuit, for analyzing the carrier signal and sending the generated analysis command to the control circuit;
and the control circuit 140 is electrically connected to the variable gain amplifier 110, and is configured to generate a gain adjustment signal according to the indication signal, and send the gain adjustment signal to the variable gain amplifier 110, so that the variable gain amplifier 110 adjusts a current gain, and performs signal amplification on the input radio frequency signal according to the adjusted current gain, and is further configured to generate a return parameter according to a corresponding analysis instruction when the indication signal meets a preset condition.
In this embodiment, the variable gain amplifier 110 has a variable gain function, and can amplify the input rf signal to different degrees according to different amplification gains. The input radio frequency signal may be received through an antenna, and for example, the input radio frequency signal may be a radio frequency signal transmitted by a card reader and carrying an interactive instruction. Here, the current gain refers to a gain stored in the variable gain amplifier 110 when the input radio frequency signal is input to the variable gain amplifier 110.
When receiving the input radio frequency signal, the variable gain amplifier 110 amplifies the radio frequency signal according to the current gain to generate a carrier signal, where the carrier signal also carries the interactive instruction of the input radio frequency signal. The output of the variable gain amplifier 110 is connected to the input of the indication circuit 120, and transmits the carrier signal to the indication circuit 120, and the indication circuit 120 extracts a first voltage of the carrier signal, wherein the first voltage may be an envelope of the carrier signal. Optionally, the Indication circuit 120 may be an RSSI (Received Signal Strength Indication) indicator. The operation principle of the indicating circuit 120 is to compare the first voltage of the carrier signal with the internal reference voltage, and generate a 2-bit indicating signal according to the comparison result. For example, if the indication signal generated by the indication circuit 120 is 01 or 10, it indicates that the carrier signal is in a normal state, and further it is known that the input radio frequency signal is in a normal state, and the current gain of the variable gain amplifier 110 does not need to be adjusted; if the indication signal generated by the indication circuit 120 is 00, it indicates that the carrier signal becomes small, and further it is known that the input radio frequency signal becomes small and the current gain of the variable gain amplifier 110 needs to be increased; if the indication signal generated by the indication circuit 120 is 11, it indicates that the carrier signal is increased, and it is further known that the input rf signal is increased and the current gain of the variable gain amplifier 110 needs to be decreased.
The control circuit 140 receives the indication signal sent by the indication circuit 120, and generates a gain adjustment signal according to the indication signal, and sends the gain adjustment signal to the variable gain amplifier 110, wherein the gain adjustment signal comprises a gain increase signal, a gain decrease signal and a gain hold signal. If the gain adjustment signal is a gain increase signal or a gain decrease signal, the variable gain amplifier 110 adjusts the current gain according to the gain adjustment signal, re-amplifies the input rf signal according to the adjusted gain, and repeats the above steps until the indication circuit 120 generates an indication signal of 01 or 10.
In this embodiment, the gain adjustment of the variable gain amplifier is performed iteratively, different amplification gains are determined for different input radio frequency signals, the problem that the input radio frequency signals are too large or too small to be processed or the processing error is large is solved, the radio frequency signals sent by radio frequency devices at different distances can be received and processed, the receiving sensitivity and the anti-interference capability of the radio frequency signals are improved, and the size requirement of the terminal antenna can be reduced.
The input end of the analog demodulator 130 is connected to the input end of the variable gain amplifier 110, receives the carrier signal transmitted by the variable gain amplifier 110, analyzes the carrier signal, extracts an analysis instruction of the carrier signal, and transmits the analysis instruction to the control circuit 140.
The control circuit 140 may receive the analysis instruction sent by the analog demodulator 130 when the indication signal satisfies a preset condition, where the preset condition of the indication signal may be 01 or 10, that is, the indication signal corresponding to the gain holding signal satisfies the preset condition. The return parameter is a response parameter of the analysis instruction, and for example, if the analysis instruction is a card reading instruction, the return parameter is current card data information.
According to the technical scheme of the embodiment, the indication circuit compares the first voltage of the carrier signal amplified by the variable gain amplifier with the internal reference voltage to generate the adjustment indication signal of the variable gain amplifier, so that the control circuit controls the variable gain amplifier to adjust the amplification gain of the variable gain amplifier, the purpose of determining the appropriate amplification gain for the input radio-frequency signals with different sizes is achieved, and the receiving sensitivity and the anti-interference capability of the radio-frequency front-end chip on the radio-frequency signals are improved.
Optionally, the rf front-end chip further includes an active amplifying circuit 150; for example, referring to fig. 2, fig. 2 is a schematic structural diagram of a radio frequency front-end chip according to an embodiment of the present invention. Wherein,
the control circuit 140 is electrically connected to the active amplification circuit 150, and is further configured to generate a state control signal according to the indication signal, receive a clock signal sent by the active amplification circuit, and generate return data according to the return parameter and the clock signal when the indication signal satisfies a preset condition;
and an active amplification circuit 150, electrically connected to the variable gain amplifier 110, for switching an operating state according to the state control signal, and performing signal amplification on a modulation signal generated according to a clock signal and return data corresponding to the carrier signal in an enable state to generate an output radio frequency signal, wherein the operating state includes an enable state and a pause state.
In this embodiment, the control circuit 140 generates a state control signal for controlling the operating state of the active amplification circuit 150 according to the indication signal while receiving the indication signal. Illustratively, the state control signal may be composed of a logic "0" and a logic "1", for example, when the state control signal is set to "0", the active amplification circuit 150 may be in a halt state, and when the state control signal is set to "1", the active amplification circuit 150 may be in an enable state. Wherein, when the indication signal is 01 or 10, the state control signal may be set to "1", and when the indication signal is 11 or 00, the state control signal may be set to "0".
The active amplifier circuit 150 receives the state control signal, switches the operating state according to the state control signal, does not receive the carrier signal transmitted from the variable gain amplifier 110 if the state control signal is in the pause state, and receives the carrier signal and extracts the clock signal of the carrier signal if the state control signal is in the enable state.
The control circuit 140 receives the clock signal sent by the active amplification circuit 150, loads the return parameter on the clock signal, and generates return data, where the return data is a carrier signal carrying the return parameter.
In this embodiment, since the clock signal needs to pass through a multi-stage program in the process of generating the return data by the control circuit 140, the generated return data is prone to have a delay, and in order to avoid an error caused by a time delay, the return data and the clock signal are synchronized to generate a modulation signal having the same frequency as the clock signal. The amplified adjusted signal is determined to be an output radio frequency signal.
In this embodiment, the operating state of the active amplification circuit 150 is controlled by the state control signal, that is, the active amplification circuit enters the enable state only after the amplification gain adjustment of the variable gain amplifier is completed, so that the problem of signal confusion caused by the collection of the output radio frequency signal generated in the amplification gain adjustment process of the variable gain amplifier by the terminal antenna again is avoided, and the interference of irrelevant signals is reduced.
Optionally, the active amplification circuit 150 comprises a clock data recovery module 151, a data synchronization module 152 and an amplifier 153, see fig. 2, wherein,
a clock data recovery module 151, electrically connected to the variable gain amplifier 110 and the control circuit 140, respectively, for receiving the state control signal, switching the operating state according to the state control signal, extracting the clock signal of the carrier signal in the enabled state, sending the clock signal to the control circuit, and generating an amplifier control signal homologous to the clock signal;
a control circuit 140, specifically configured to generate return data according to the clock signal and the return parameter;
a data synchronization module 152 electrically connected to the clock data recovery module 151 and the control circuit 140, respectively, for synchronizing the clock signal and the return data to generate a modulation signal;
and the amplifier 153 is electrically connected to the clock data recovery module 151 and the data synchronization module 152, and configured to amplify the modulated signal to generate an output radio frequency signal, and dissipate energy after the output radio frequency signal is output according to an amplifier control signal.
In this embodiment, the Clock Data Recovery (CDR) module 151 may recover a clock signal of the carrier signal, and since the data synchronization module 152 and the amplifier 153 both require a clock signal, when the clock data recovery module 151 is in a suspended state, the data synchronization module 152 and the amplifier 153 are both in a suspended state, and no separate state control signal is required.
The clock data recovery module 151 is connected to the control circuit 140, and transmits a clock signal to the control circuit 140 and receives return data fed back by the control circuit 140.
The data synchronization module 152 synchronizes the clock signal with the return data, eliminates time delays in the return data, and makes the generated modulated signal have the same frequency as the clock signal.
In this embodiment, the amplifier control signal is homologous to the clock signal of the carrier signal and is used to control the amplifier 153, and when the amplifier 153 finishes transmitting the output radio frequency signal, the energy remaining in the amplifier 153 is dissipated, so as to avoid the influence of the remaining energy on the transmission of the subsequent output radio frequency signal.
In this embodiment, the gain of the amplifier 153 may be fixed, and is used to amplify the modulated signal, so that the generated output radio frequency signal has higher sensitivity, the output sensitivity of the radio frequency signal is improved, and the size requirement of the terminal antenna can be reduced.
Optionally, the rf front-end chip further includes a private GPIO interface 160; wherein,
a private GPIO (General Purpose Input/Output) interface 160, connected to the control circuit 140 and the external security module, respectively, for transmitting the parsing instruction to the external security module, so that the external security module performs security verification on the parsing instruction and transmits feedback information of the external security module to the control circuit;
the control circuit 140 is further configured to generate a return parameter according to the corresponding parsing instruction when the feedback information of the external security module is successfully verified, and discard the parsing instruction when the feedback information of the external security module is failed to be verified.
In this embodiment, in order to improve the security of communication between the radio frequency front-end chip and the external device, the analysis instruction needs to be securely verified, where the external security module is configured to securely verify the analysis instruction, is set in a preset position of a terminal outside the radio frequency front-end chip, and communicates with the radio frequency front-end chip through a private GPIO interface.
The external security module receives the analysis instruction sent by the control circuit 140, and feeds back the verification information after verification, wherein if the feedback information is successful, the control circuit 140 executes an operation of generating a return parameter according to the analysis instruction, and if the feedback information is failed, the control circuit 140 interrupts a response to the input radio frequency signal, and discards the analysis instruction.
In the embodiment, the safety of communication between the radio frequency front-end chip and the external equipment is improved through the safety verification of the analysis instruction.
Optionally, the coding mode of the private GPIO interface is a Non-Return to Zero (NRZ) coding mode with a start/stop bit.
Optionally, the unit of the NRZ coding scheme with start and stop bits is 8 byte. Specifically, the encoding mode of the private GPIO interface includes a start bit, a data bit, a parity bit, a stop bit, and an idle bit. The positions of the start bit, the data bit, the parity bit, the stop bit and the idle bit are determined by an interface protocol. For example, referring to fig. 3, fig. 3 is a schematic diagram of an encoding manner of the private GPIO interface according to an embodiment of the present invention. Where the start bit indicates the start of the transmission of the character by signaling a logic "0". The data bits are set after the start Bit, and data is transferred from the lowest data Bit, i.e., Bit0, using 8-Bit data bits, where the data bits are located based on the clock. The parity bits are disposed behind the data bits and include odd parity and even parity, wherein the number of bits of logic "1" is even parity and the number of bits of logic "1" is odd parity. Optionally, the method is used for even check in the embodiment. The stop bit is used to mark the end of the character data, and optionally, a 1-bit stop bit is used. When the idle bit is set to a logic "1," it indicates that no data is currently being transmitted on the line.
In the embodiment, the private GPIO interface with the NRZ coding mode with the start-stop bit is arranged, so that the safety and reliability of data transmission between the radio frequency front-end chip and the external safety module are improved, and the problems of data loss or leakage and the like in the data transmission process are avoided.
Optionally, the communication transmission between the private GPIO interface and the external security module uses a multi-channel transmission channel, and the communication protocol of the private GPIO interface uses a master-slave half-duplex communication mode, where the external security module is a host end of communication, and the radio frequency front end chip is a slave end of communication.
In this embodiment, the private GPIO interface includes the following pins: a DIO (Digital Input/Output) pin, an IRQ (Interrupt Request) pin, and a CLK (CLOCK) pin. For transmitting data signals, interrupt signals and clock signals, respectively. Illustratively, referring to table 1, table 1 is a definition of a private GPIO interface pin.
TABLE 1
In this embodiment, the communication transmission between the private GPIO interface and the external security module employs multiple transmission channels, and the data signal, the interrupt signal, and the clock signal are transmitted through different transmission channels, thereby improving the reliability of signal transmission. For example, referring to fig. 4, fig. 4 is a schematic transmission diagram of a radio frequency front-end chip and an external security module according to an embodiment of the present invention.
In this embodiment, a master-slave question-and-answer half-duplex communication mode is adopted, in which the external security module is a host end for communication, and the radio frequency front-end chip is a slave end for communication. The clock signal is always initiated by the host, when the host needs to initiate communication, the clock signal is sent out, data is sent out from a DIO pin, and the slave responds; when the slave end needs to initiate communication, an interrupt request signal is sent out through the IRQ pin, when the host end receives the interrupt request signal, an inquiry is sent out through the CLK pin and the DIO pin, and the slave responds.
Optionally, the baud rate of the private GPIO interface communication protocol is set to a preset frequency division, where the preset frequency division is less than or equal to 372 frequency division and greater than or equal to 7 frequency division.
In this embodiment, the preset frequency division refers to the number of data flipping times within the range of 1bit, for example, see fig. 5, and fig. 5 is a schematic diagram of a transmission signal provided by the first embodiment of the present invention, where the frequency division of 1bit in fig. 5 is 7. Through setting up the upset, can gather a plurality of data at 1bit within range, can carry out processes such as smoothness to a plurality of data in order to improve the transmission data rate of accuracy, reduce the influence of data error to transmission quality.
In this embodiment, the frequency division of the private GPIO interface communication protocol may be adjusted as needed, where the larger the frequency division number is, the higher the communication quality is, and the slower the transmission speed is, and conversely, the smaller the frequency division number is, the lower the communication quality is, and the faster the transmission speed is.
Optionally, it should be noted that the control circuit 140 may also be a digital baseband circuit. The digital baseband circuit has the function of automatic SDD (Single device detection), and can complete card selection operation. Data transmitted by the GPIO communication with the private protocol is activation and ISO _ DEP/NFC _ DEP data after an SDD stage, and data sensitive to transaction is above the layer, so that encrypted data is transmitted on the GPIO communication with the private protocol, side channel attack can be prevented, and communication safety at the stage is guaranteed.
In this embodiment, the rf front-end chip is designed and taped on a 0.18um EEPROM (Electrically erasable programmable read only memory) process. The actual receiving sensitivity reaches the level of 1mVrms at the radio frequency input port, and when the output antenna adopts a PCB (Printed Circuit Board) antenna of 1cmx1cm, the achieved output energy is about 50 times that of the traditional passive mode. The method realizes the connection with the Yingfei SLE97 and the Italian semiconductor ST33 safety encryption chip by the private instruction GPIO, and realizes reliable and stable data communication.
Example two
Fig. 6 is a flowchart of a processing method of radio frequency signals provided by the embodiment of the present invention, and this embodiment is applicable to the situation that the radio frequency front end chip processes the radio frequency signals in the intelligent terminal, and this method can be executed by the embodiment of the present invention provides a radio frequency front end chip. The method specifically comprises the following steps:
s210, acquiring an input radio frequency signal, and determining the amplification gain of the input radio frequency signal.
Wherein for each input radio frequency signal a corresponding amplification gain is determined, wherein the amplification gain may be determined by a plurality of iterative adjustments.
Optionally, step S210 includes: performing signal amplification on an input radio frequency signal according to the current gain to generate a carrier signal; extracting a first voltage of the carrier signal, comparing the first voltage with an internal reference voltage, and determining an indication signal according to a comparison result; and generating a gain adjusting signal according to the indicating signal, adjusting the current gain according to the gain adjusting signal, and determining the amplification gain.
Optionally, the determining the amplification gain includes determining a gain of the current gain according to the gain adjustment signal, where the gain adjustment signal includes a gain increase signal, a gain decrease signal, and a gain hold signal, and the determining the amplification gain includes: if the gain adjusting signal is a gain increasing signal, the amplification gain is the sum of the current gain and the reference gain, and the indicating signal is determined again; if the gain adjusting signal is a gain reducing signal, the amplification gain is the difference between the current gain and the reference gain, and the indicating signal is determined again; and if the gain adjusting signal is a gain maintaining signal, stopping adjusting the current gain.
The reference gain refers to a gain change amount per gain adjustment.
In this embodiment, when it is detected that the gain adjustment signal is the gain hold signal, it is determined that the gain adjustment is completed, and subsequent processing is performed on the carrier signal generated by the determined amplification gain processing.
And S220, performing signal amplification on the input radio frequency signal according to the amplification gain to generate a carrier signal.
And S230, extracting an analysis instruction carried by the carrier signal, and generating a return parameter according to the analysis instruction.
And S240, combining the return parameter with the clock signal of the carrier signal to generate an output radio frequency signal.
Optionally, step S240 includes: merging the return parameters with the clock signals of the carrier signals to generate return data; synchronizing the return data with a clock signal of the carrier signal to generate a modulation signal; and amplifying the modulation signal to generate and output a radio frequency signal.
In this embodiment, the modulation signal is signal-amplified, so that the generated output radio frequency signal has higher sensitivity, and the output sensitivity of the radio frequency signal is improved.
Optionally, before determining the radio frequency output signal according to the analysis instruction and outputting the radio frequency output signal, the method further includes: transmitting the analysis instruction to an external security module based on a private GPIO interface, performing security verification on the analysis instruction, and receiving feedback information of the external security module; if the feedback information is verified successfully, generating a return parameter according to the analysis instruction; and if the feedback information is verification failure, discarding the analysis instruction.
In the embodiment, the safety of communication between the radio frequency front-end chip and the external equipment is improved through the safety verification of the analysis instruction.
According to the technical scheme, the proper amplification gain is determined for the input radio frequency signals with different sizes by adjusting the amplification gain of the input radio frequency signals, the analysis instruction of the carrier signal is obtained, the return parameter is generated, the return parameter is loaded to the clock signal to generate the output radio frequency signal, and the receiving and transmitting sensitivity and the anti-interference capacity of the radio frequency signal are improved.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.
Claims (7)
1. A radio frequency front-end chip is characterized by comprising a variable gain amplifier, an indicating circuit, an analog demodulator and a control circuit; wherein,
the variable gain amplifier is used for amplifying an input radio frequency signal according to the current gain and outputting a carrier signal;
the indicating circuit is respectively electrically connected with the variable gain amplifier and the control circuit and is used for extracting a first voltage of the carrier signal, generating an indicating signal according to the first voltage and an internal reference voltage and sending the indicating signal to the control circuit;
the analog demodulator is electrically connected with the variable gain amplifier and the control circuit and used for analyzing the carrier signal and sending a generated analysis instruction to the control circuit;
the control circuit is electrically connected with the variable gain amplifier, and is used for generating a gain adjusting signal according to the indication signal and sending the gain adjusting signal to the variable gain amplifier so that the variable gain amplifier adjusts the current gain and performs signal amplification on the input radio frequency signal according to the adjusted current gain, and is also used for generating a return parameter according to a corresponding analysis instruction when the indication signal meets a preset condition.
2. The radio frequency front end chip of claim 1, further comprising an active amplification circuit; wherein,
the control circuit is electrically connected with the active amplification circuit and is further used for generating a state control signal according to the indication signal, receiving a clock signal sent by the active amplification circuit and generating return data according to a return parameter and the clock signal when the indication signal meets a preset condition;
the active amplification circuit is electrically connected with the variable gain amplifier and used for switching working states according to the state control signal, amplifying a signal according to a clock signal corresponding to the carrier signal and a modulation signal generated by the return data in an enabling state, and generating an output radio frequency signal, wherein the working states comprise an enabling state and a suspending state.
3. The RF front-end chip of claim 2, wherein the active amplification circuit comprises a clock data recovery module, a data synchronization module, and an amplifier, wherein,
the clock data recovery module is respectively electrically connected with the variable gain amplifier and the control circuit, and is used for receiving the state control signal, switching the working state according to the state control signal, extracting the clock signal of the carrier signal in the enabled state, sending the clock signal to the control circuit, and generating an amplifier control signal homologous to the clock signal;
the control circuit is specifically configured to generate the return data according to the clock signal and the return parameter;
the data synchronization module is respectively electrically connected with the clock data recovery module and the control circuit and is used for synchronizing the clock signal and the return data to generate the modulation signal;
the amplifier is respectively and electrically connected with the clock data recovery module and the data synchronization module, and is used for amplifying the modulation signal, generating the output radio frequency signal, and dissipating energy after the output radio frequency signal is output according to the amplifier control signal.
4. The rf front-end chip of claim 1, further comprising a private GPIO interface; wherein,
the private GPIO interface is respectively connected with the control circuit and the external security module and is used for transmitting the analysis instruction to the external security module so that the external security module can carry out security verification on the analysis instruction and transmit feedback information of the external security module to the control circuit;
the control circuit is further configured to generate a return parameter according to the corresponding analysis instruction when the feedback information of the external security module is successfully verified, and discard the analysis instruction when the feedback information of the external security module is unsuccessfully verified.
5. The RF front-end chip of claim 4, wherein the encoding mode of the private GPIO interface is NRZ encoding with start and stop bits.
6. The RF front-end chip according to claim 4, wherein the communication transmission between the private GPIO interface and the external security module is a multi-channel transmission channel, and the communication protocol of the private GPIO interface is a half-duplex communication mode of master-slave question-answering, wherein the external security module is a master end of communication, and the RF front-end chip is a slave end of communication.
7. The radio frequency front end chip of claim 4, wherein the baud rate of the private GPIO interface communication protocol is set to a predetermined frequency division, wherein the predetermined frequency division is less than or equal to 372 frequency division and greater than or equal to 7 frequency division.
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