CN206113785U - Clock synchronization communication circuit of electron detonator - Google Patents
Clock synchronization communication circuit of electron detonator Download PDFInfo
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- CN206113785U CN206113785U CN201620884271.2U CN201620884271U CN206113785U CN 206113785 U CN206113785 U CN 206113785U CN 201620884271 U CN201620884271 U CN 201620884271U CN 206113785 U CN206113785 U CN 206113785U
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Abstract
The utility model relates to a clock synchronization communication circuit of electron detonator, this communication circuit include communication interface, rectifier circuit, voltage stabilizing circuit, a filter circuit, the 2nd filter circuit and processing circuit, and detonating ware passes through the communication circuit of bus input electronics detonator with communication signals, and the communication circuit obtains communication data signal and rectifier circuit 0 through communication signals to process communication data signal under clock signal's control. The utility model discloses can keep the clock uniformity of the communication circuit of electron detonator, eliminate the accumulated error of clock, avoid appearing the systematic error in the communication process of detonating ware and electron detonator.
Description
Technical field
The utility model is related to electric detonator technical field, more particularly to a kind of clock synchronous communication electricity of electric detonator
Road.
Background technology
Clock is exactly the heart of single-chip microcomputer, is often beated, and the just synchronous action of each circuit of whole single-chip microcomputer is once.
Using the communication signal of single-chip microcomputer reception processing initiator, the communicating circuit of multiple electric detonators in the communicating circuit of electric detonator
Parallel connection accesses bus and is communicated with initiator, and each electric detonator is different except the burst time, requires elsewhere very well
Uniformity.In existing electric detonator communicating circuit, the clock signal of single-chip microcomputer by the way of external crystal oscillator, no
Easily ensure the clock consistency of the communicating circuit of all electric detonators, the cumulative errors of clock are larger after operation a period of time,
Easily there is system mistake in initiator and the communication process of electric detonator.
Utility model content
The utility model provides a kind of clock synchronous communication circuit of electric detonator, and technical problem to be solved is to ensure
The clock signal of the electric detonator of all accesses is consistent.
The technical scheme that the utility model solves above-mentioned technical problem is as follows：
A kind of clock synchronous communication circuit of electric detonator, the communicating circuit can receive what initiator was sent by bus
Communication signal, the communicating circuit includes communication interface, rectification circuit, mu balanced circuit, the first filter circuit, the second filter circuit
And signal processing circuit；
The communication interface is connected with the first input end and the second input of the rectification circuit, the rectification circuit
First output end input, the input of first filter circuit, second filtered electrical respectively with the mu balanced circuit
The power end connection of the input connection on road, the output end of the mu balanced circuit and the signal processing circuit, first filter
The clock signal terminal connection of the output end of wave circuit and the signal processing circuit, the output end of second filter circuit and institute
State the communication signal end connection of signal processing circuit.
Further, the mu balanced circuit is used to obtain DC voltage after processing the signal after rectification, is the letter
Number process circuit is powered；First filter circuit is used to obtain clock signal after the signal after rectification is filtered, described
Second filter circuit is used to obtain communication data signal after the signal after rectification is filtered, and the signal processing circuit is used for
The communication data signal described in reception processing under the control of the clock signal.
Further, first filter circuit is high-pass filtering circuit.
Further, second filter circuit is the bandpass filtering electricity that low-pass filter circuit and high-pass filtering circuit are constituted
Road.
Further, the rectification circuit be bridge rectifier, the first input end of the bridge rectifier and second
Input difference communication interface connection, the cathode output end of the bridge rectifier is the first output end, and cathode output end connects
Ground.
Further, the first filtered electrical routing capacitance C1 and resistance R1 is constituted, and one end of electric capacity C1 is used as the filtering
The input of circuit, the other end is connected and as the output end of first filter circuit with one end of resistance R1, resistance R1's
The other end is grounded.
Further, second filter circuit includes the low-pass filter circuit being made up of electric capacity C1, resistance R2 and by electric capacity
The high-pass filtering circuit of C3, resistance R3 composition, one end of resistance R2 as second filter circuit input, the other end point
It is not connected with one end of electric capacity C2 and one end of electric capacity C3, the other end of electric capacity C3 is connected and as described with one end of resistance R3
The other end of the output end of the second filter circuit, the other end of the electric capacity C2 and the resistance R3 is grounded.
Further, the mu balanced circuit is made up of three terminal regulator U1, electric capacity C5 and electric capacity C6, one end of electric capacity C5 and three
The input of end voltage-stablizer U1 is made after being connected with one end of electric capacity C6 as input, the output end of three terminal regulator U1 after being connected
For output end, the output end and electric capacity C5 of three terminal regulator U1, the other end of electric capacity C6 are grounded.
The beneficial effects of the utility model are to maintain the clock consistency of the communicating circuit of electric detonator, eliminate the tired of clock
Meter error, it is to avoid system mistake occur in the communication process of initiator and electric detonator
Description of the drawings
A kind of clock synchronous communication circuit diagram of electric detonator that Fig. 1 is provided for the utility model embodiment；
Fig. 2 is the utility model embodiment the second filter circuit composition schematic diagram；
A kind of clock synchronous communication circuit theory diagrams of electric detonator that Fig. 3 is provided for the utility model embodiment；
In Fig. 3, the list of parts representated by each label is as follows：
1st, communication interface, 2, rectification circuit, the 3, first filter circuit, the 4, second filter circuit, 5, signal processing circuit, 6,
Mu balanced circuit.
Specific embodiment
Principle of the present utility model and feature are described below in conjunction with accompanying drawing, example is served only for explaining this practicality
It is new, it is not intended to limit scope of the present utility model.
As shown in figure 1, a kind of clock synchronous communication circuit of electric detonator of the utility model embodiment, including communication connects
Mouth, rectification circuit, mu balanced circuit, the first filter circuit, the second filter circuit and signal processing circuit；
The communication interface is connected with the first input end and the second input of the rectification circuit, the rectification circuit
First output end input, the input of first filter circuit, second filtered electrical respectively with the mu balanced circuit
The power end connection of the input connection on road, the output end of the mu balanced circuit and the signal processing circuit, first filter
The clock signal terminal connection of the output end of wave circuit and the signal processing circuit, the output end of second filter circuit and institute
State the communication signal end connection of signal processing circuit..
As shown in Fig. 2 the filter circuit of the utility model embodiment second is low-pass filter circuit and high-pass filtering circuit group
Into band-pass circuit, the input of the low-pass filter circuit is the input of the second filter circuit, the low-pass filter circuit
Output end be connected with the input of the high-pass filtering circuit, the output end of the high-pass filtering circuit is the second filter circuit
Output end.
Fig. 3 be the utility model embodiment provide a kind of electric detonator clock synchronous communication circuit in each built-up circuit
Concrete structure, as shown in the figure：
The rectifier bridge that rectification circuit 2 is made up of diode D1 and D2,1 pin of diode D1 connects with 2 pin of diode D2
As the first input end of rectifier bridge after connecing, 2 pin of diode D1 be connected with 1 pin of diode D2 after as the second of rectifier bridge
Input, 3 pin of diode D2 are cathode output end, and 3 pin of diode D1 are grounded as cathode output end, the effect of rectifier bridge
It is the signal for making non-polar signal be transformed into polarized；
The high-pass filtering circuit that first filter circuit 3 is made up of electric capacity C1 and resistance R1, one end of electric capacity C1 is used as institute
The input of filter circuit is stated, the other end is connected and as the output end of first filter circuit, electricity with one end of resistance R1
The other end ground connection of resistance R1, the first filter circuit is used to filter the low frequency noise signals in communication signal；
Second filter circuit 4 includes the low-pass filter circuit being made up of electric capacity C1, resistance R2 and by electric capacity C3, resistance R3 groups
Into high-pass filtering circuit, one end of resistance R2 as second filter circuit input, the other end respectively with electric capacity C2
One end and electric capacity C3 one end connection, the other end of electric capacity C3 is connected and as second filtered electrical with one end of resistance R3
The other end of the output end on road, the other end of the electric capacity C2 and the resistance R3 is grounded, and the second filter circuit is used for logical
News signal carries out bandpass filtering to obtain the signal of certain frequency range；
Mu balanced circuit 6 is made up of three terminal regulator U1, electric capacity C5 and electric capacity C6, one end of electric capacity C5 and three terminal regulator U1
Input be connected after be connected with one end of electric capacity C6 as input, the output end of three terminal regulator U1 after as output end,
The output end and electric capacity C5 of three terminal regulator U1, the other end of electric capacity C6 are grounded, and mu balanced circuit is used to export stable 3.3V
DC voltage；
Signal processing circuit 5 is made up of communication chip U2 and single-chip microcomputer U3, and communication chip U2 is used to change signal
It is input into single-chip microcomputer afterwards to be processed, 1 pin of communication chip U2 is the communication signal end of signal processing circuit, 2 pin are grounded, and 3 pin are
The transmitting terminal of communication chip, is connected with 3 pin of single-chip microcomputer U3,4 pin for communication chip U2 receiving terminal, 2 pin with single-chip microcomputer U3
Connection, 1 pin of single-chip microcomputer U3 is power end, accesses the 3.3V DC voltages that mu balanced circuit 6 is provided, and 6 pin are clock signal pin
OSC1, accesses the clock signal that the first filter circuit 3 sends.
The operation principle of above-mentioned communicating circuit is specifically introduced with reference to Fig. 3：.
The communicating circuit of the multiple electric detonators bus that accesses in parallel is communicated with initiator, and initiator sends communication signal
Communicating circuit is reached by bus, by communication interface 1, the diode D2 in rectification circuit carries out rectification, after rectification
Signal filters the noise low frequency signal in communication signal by the first filter circuit, is re-fed into the clock signal pin of single-chip microcomputer U3
OSC1, so, the clock signal of the electric detonator of all carries is consistent in bus, and the signal after rectification is by the second filter
Wave circuit carries out obtaining the communication data signal of certain band limits after bandpass filtering, is re-fed into the input pin of communication chip U2
Vin, after communication chip U2 process, from transmitting terminal TX outputs, is re-fed into single-chip microcomputer pin PA1, letter of the single-chip microcomputer to input
After number being processed, from pin PA0 outputs, the receiving terminal RX of communication chip is sent into, initiator is fed back to, so as to complete to communicate
Journey.
Preferred embodiment of the present utility model is the foregoing is only, it is all in this practicality not to limit the utility model
Within new spirit and principle, any modification, equivalent substitution and improvements made etc. should be included in guarantor of the present utility model
Within the scope of shield.
Claims (9)
1. modulated signal is loaded on carrier wave and produces carrier signal and pass through bus by a kind of communicating circuit of electric detonator, initiator
Send to the communicating circuit, and receive the output signal that the communicating circuit sends, it is characterised in that the communicating circuit bag
Include communication interface, filter circuit, first switch circuit, second switch circuit, single-chip microcomputer, rectification circuit and mu balanced circuit；
The communication interface is connected with the first input end and the second input of the rectification circuit, and the first of the rectification circuit
The input of output end input, the input of the mu balanced circuit and the second switch circuit respectively with the filter circuit
End connection, the input of the first switch circuit is connected with the output end of the mu balanced circuit, the first switch circuit
Control end is connected with the output end of the filter circuit, the output end of the first switch circuit and the input of the single-chip microcomputer
Connection, the output end of the single-chip microcomputer is connected with the control end of the second switch circuit.
2. the communicating circuit of electric detonator according to claim 1, it is characterised in that the filter circuit includes high pass filter
Wave circuit, detecting circuit and low-pass filter circuit, the input of the high-pass filtering circuit is defeated with the first of the rectification circuit
Go out end connection, the output end of the high-pass filtering circuit is connected with the input of the detecting circuit, the detecting circuit it is defeated
Go out end to be connected with the input of the low-pass filter circuit, the output end of the low-pass filter circuit and the first switch circuit
Control end connection.
3. the communicating circuit of electric detonator according to claim 2, it is characterised in that it is overheated that the communicating circuit also includes
Protection circuit, the overheating protection circuit series connection is accessed between the communication interface and the rectification circuit.
4. the communicating circuit of electric detonator according to claim 3, it is characterised in that the overheating protection circuit is by PTC
Resistance is constituted.
5. the communicating circuit of electric detonator according to claim 4, it is characterised in that the rectification circuit is bridge rectifier
Circuit, the first input end of the bridge rectifier and the difference communication interface connection of the second input, the bridge rectifier electricity
The cathode output end on road is the first output end, and cathode output end is grounded.
6. the communicating circuit of electric detonator according to claim 5, it is characterised in that the mu balanced circuit is by three-terminal voltage-stabilizing
Device U1, electric capacity C1, electric capacity C2 and electric capacity C3 composition, one end of electric capacity C1 be connected with the input of three terminal regulator U1 after as defeated
Enter end, the output end of three terminal regulator U1, one end of electric capacity C2 be connected with one end of electric capacity C3 after as output end, three-terminal voltage-stabilizing
The output end and electric capacity C1 of device U1, electric capacity C2, the other end of electric capacity C3 are grounded.
7. the communicating circuit of electric detonator according to claim 6, it is characterised in that the high-pass filtering circuit is by electric capacity
C1 and resistance R1 is constituted, and the detecting circuit is made up of detector diode D3, and the low-pass filter circuit is by electric capacity C2 and resistance
R2 is constituted, one end of electric capacity C1 as the filter circuit input, other end one end respectively with resistance R1 and detection two
The anode connection of pole pipe D3, the other end ground connection of resistance R1, the negative electrode of detector diode D3 is connected with one end of resistance R2, resistance
The other end of R2 is connected and as the output end of the filter circuit with one end of electric capacity C2, and the other end of electric capacity C2 is grounded.
8. the communicating circuit of electric detonator according to claim 7, it is characterised in that the first switch electricity routing resistance
R3 and triode Q1 is constituted, and, used as control end, one end of resistance R3 is used as input, the other end and three poles for the base stage of triode Q1
The colelctor electrode of pipe Q1 is connected and as output end, the grounded emitter of triode Q1.
9. the communicating circuit of electric detonator according to claim 8, it is characterised in that the second switch electricity routing resistance
R5 and triode Q2 is constituted, and one end of resistance R5 is input, and the other end is connected with the colelctor electrode of triode Q2, triode Q2's
Base stage is control end, the grounded emitter of triode Q2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620884271.2U CN206113785U (en) | 2016-08-15 | 2016-08-15 | Clock synchronization communication circuit of electron detonator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620884271.2U CN206113785U (en) | 2016-08-15 | 2016-08-15 | Clock synchronization communication circuit of electron detonator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206113785U true CN206113785U (en) | 2017-04-19 |
Family
ID=58512705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620884271.2U Expired - Fee Related CN206113785U (en) | 2016-08-15 | 2016-08-15 | Clock synchronization communication circuit of electron detonator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206113785U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111854547A (en) * | 2020-05-22 | 2020-10-30 | 杨力 | Electronic detonator communication circuit and control method |
-
2016
- 2016-08-15 CN CN201620884271.2U patent/CN206113785U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111854547A (en) * | 2020-05-22 | 2020-10-30 | 杨力 | Electronic detonator communication circuit and control method |
| CN111854547B (en) * | 2020-05-22 | 2021-08-31 | 芯动元(广州)科技有限公司 | Electronic detonator communication circuit and control method |
| WO2021232776A1 (en) * | 2020-05-22 | 2021-11-25 | 杨力 | Electronic detonator communication circuit and control method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170419 Termination date: 20170815 |