CN205847227U - Hardware interlock protection circuit - Google Patents
Hardware interlock protection circuit Download PDFInfo
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- CN205847227U CN205847227U CN201620519645.0U CN201620519645U CN205847227U CN 205847227 U CN205847227 U CN 205847227U CN 201620519645 U CN201620519645 U CN 201620519645U CN 205847227 U CN205847227 U CN 205847227U
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Abstract
This utility model is applicable to signal processing technology field, it is provided that a kind of hardware interlock protection circuit, including: the first pulse signal generation chip, the second pulse signal generation chip；Described first pulse signal generation chip includes the first NAND gate, the second NAND gate, the 3rd NAND gate；Described second pulse signal generation chip includes the 4th NAND gate, the 5th NAND gate, the 6th NAND gate；After 3 grades of NAND gate in first pulse signal generation chip connect, input PWM1 signal by the first input end of the first NAND gate, export PWM1 signal after treatment by the outfan of the 3rd NAND gate；After 3 grades of NAND gate in second pulse signal generation chip connect, by the second input input PWM2 signal of the 4th NAND gate, export PWM2 signal after treatment by the outfan of the 6th NAND gate.The hardware interlock protection circuit that this utility model provides, compared to Product Safety and stability for software interlocks protection circuit more preferably.
Description
Technical field
This utility model belongs to signal processing technology field, particularly relates to a kind of hardware interlock protection circuit.
Background technology
Electric vehicle controller, UPS (Uninterruptible Power System/Uninterruptible Power
Supply, uninterrupted power source) etc. product can be applied to the switching devices such as IGBT or MOSFET.And PWM controls technology electronic
The IGBT of the product such as automobile controller, UPS or switch mosfet extensively apply.It is with upper and lower bridge complementation shape mostly by software
Formula output PWM, controls IGBT or switch mosfet, as shown in Figure 1.
But run into the extraneous factors such as interference when software or time program self BUG causes software failure, it is possible that up and down
Bridge exports situation that PWM is high level simultaneously rather than occurs with complementary type.According to practical situation, if the PWM of output occurs
It is the situation of high level simultaneously, the switching tube up and down of IGBT or switch mosfet can be caused to simultaneously turn on, so that positive and negative busbar
, there are the dangerous things such as on fire, blast, had both damaged component, and jeopardized again personal safety in short circuit.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of hardware interlock protection circuit, it is desirable to provide a kind of
Hardware protection circuit, solves when relying on software to control two output signals PWM, if there is software failure, program fleet etc.
Situation, can cause two output pwm signals simultaneously for high level thus the problem causing line short.
This utility model provides a kind of hardware interlock protection circuit, including:
First pulse signal generation chip, the second pulse signal generation chip；
Described first pulse signal generation chip includes 3 grades of NAND gate, the respectively first NAND gate, the second NAND gate,
Three NAND gate；Described second pulse signal generation chip includes 3 grades of NAND gate, the respectively the 4th NAND gate, the 5th NAND gate,
Six NAND gate；
The first input end input PWM1 signal of described first NAND gate, the second input input high level, described first
The outfan of NAND gate connects the first input end of described 5th NAND gate；
The first input end of described second NAND gate inputs described PWM1 signal, and the second input connects the described 4th with non-
The outfan of door, the outfan of described second NAND gate connects first, second input of described 3rd NAND gate；
The outfan output of described 3rd NAND gate PWM1 signal after treatment；
The first input end input high level of described 4th NAND gate, the second input input PWM2 signal；
Second input of described 5th NAND gate inputs described PWM2 signal, and the outfan of described 5th NAND gate connects
First, second input of described 6th NAND gate；
The outfan output of described 6th NAND gate PWM2 signal after treatment.
Further, the first input end of described first NAND gate connects resistance R1, the second input of the first NAND gate
Connecting resistance R2, the second input of described 4th NAND gate connects resistance R3；Wherein, R1=1K Ω, R2=10K Ω, R3=
1KΩ。
Further, also including electric capacity C1, the second input of described first NAND gate passes through described electric capacity C1 ground connection.
This utility model compared with prior art, has the beneficial effects that: this utility model provides a kind of hardware interlock and protects
Protection circuit, relies on hardware circuit to process signal, it is ensured that be high during two output signal differences, it is achieved that signal interlocks；
Such as, the signal after two process exported by this circuit is applied to two electricity switched controlling to connect between positive and negative busbar
Lu Shi, can avoiding relying on software when being controlled two signals, if there is the problem of software failure, may result in PWM interlocking
The generation of failure phenomenon, thus cause upper and lower switching tube to simultaneously turn on, the problem of positive and negative busbar short circuit.Improve Product Safety
And stability, personal safety simultaneously gets better protection；And the hardware interlock protection circuit that this utility model provides is former
Reason is simple, low cost.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the switch of the PWM output signal control D/C power of the employing protection circuit that prior art provides.
Fig. 2 is the schematic diagram of the hardware interlock protection circuit that this utility model embodiment provides；
Fig. 3 is corresponding the illustrating from the actual level change being input to output of 4 kinds of states in this utility model embodiment
Figure.
Detailed description of the invention
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing and enforcement
Example, is further elaborated to this utility model.Should be appreciated that specific embodiment described herein is only in order to explain
This utility model, is not used to limit this utility model.
This utility model provides a kind of hardware interlock protection circuit, including:
First pulse signal generation chip, the second pulse signal generation chip；Described first pulse signal generation chip bag
Including some grades of NAND gate, described second pulse signal generation chip includes some grades of NAND gate；
Further, described first pulse signal generation chip (not shown) includes 3 grades of NAND gate, respectively first
NAND gate U2-A, the second NAND gate U2-B, the 3rd NAND gate U2-C；Described second pulse signal generation chip includes 3 grades with non-
Door, the respectively the 4th NAND gate U1-A, the 5th NAND gate U1-B, the 6th NAND gate U1-C, the most as shown in Figure 2.
Further, the supply voltage of described first pulse signal generation chip (not shown) is 5V, described second
The supply voltage of pulse signal generation chip (not shown) is 5V.
Some grades of NAND gate of described first pulse signal generation chip, described second pulse signal generation chip some
Level is after NAND gate each connects or be connected with each other, if inputting the pwm signal and described the of described first pulse signal generation chip
The pwm signal of two pulse signal generation chips is high level simultaneously, then after the described NAND gate through respective chip processes, output
It it is high level during two paths of signals difference；If inputting the pwm signal of described first pulse signal generation chip and described second pulse
Be high level during the pwm signal difference of signal generation chip, then after the described NAND gate through respective chip processes, the signal of output
All the signal with input is same level.
Further, some grades of NAND gate of described first pulse signal generation chip, described second pulse signal occur
The connected mode of some grades of NAND gate of chip is:
The first input end input PWM1 signal of described first NAND gate U2-A, the second input input high level, described
The outfan of the first NAND gate U2-A connects the first input end of described 5th NAND gate；
In Fig. 2 pin be one end of 1 be first input end, pin be one end of 2 be the second input, pin is the one of 3
End is outfan.
Further, the second input input voltage of described first NAND gate U2-A is 5V.
The first input end of described second NAND gate U2-B inputs described PWM1 signal, and the second input connects the described 4th
The outfan of NAND gate, the first, second of outfan described 3rd NAND gate U2-C of connection of described second NAND gate U2-B is defeated
Enter end；
The outfan output of described 3rd NAND gate U2-C signal PWM1_1 after treatment；
Further, the signal PWM1_1 of the outfan output of described 3rd NAND gate U2-C is for inputting the PWMA1 of Fig. 1
Signal end.
The first input end input high level of described 4th NAND gate U1-A, the second input input PWM2 signal；
Second input of described 5th NAND gate U1-B inputs described PWM2 signal, described 5th NAND gate U1-B defeated
Go out end and connect first, second input of described 6th NAND gate；
The outfan output of described 6th NAND gate U1-C signal PWM2_2 after treatment.
Further, the signal PWM2_2 of the outfan output of described 6th NAND gate is for inputting the PWMA2 signal of Fig. 1
End.
Owing to when the outfan of described 3rd NAND gate is different from the signal that the outfan of described 6th NAND gate exports being
High level, therefore, Fig. 1 does not haves IGBT or switch mosfet is closed at, the situation of positive and negative busbar short circuit.
Further, the first input end of described first NAND gate connects resistance R1, the second input of the first NAND gate
Connecting resistance R2, the second input of described 4th NAND gate connects resistance R3；It is mainly used in current limliting.Filtering etc., wherein, R1
=1K Ω, R2=10K Ω, R3=1K Ω.
Further, described hardware interlock protection circuit also includes electric capacity C1, the second input of described first NAND gate
By described electric capacity C1 ground connection.
When PWM1 and the PWM2 signal following 4 kind state of input is set forth below, 3 grades of NAND gate of respectively hanging oneself process
After, the situation of the level of output signal is as shown in the table:
As seen from the above table, signal PWM1 and PWM2 no matter inputted is high level or low level, and the signal of output is the most not
Can be high level simultaneously.Specifically, when input signal PWM1 and PWM2 be high level simultaneously time, the signal PWM1_1 of output with
PWM2_2 is all low level, it is achieved thereby that signal interlocking, does not haves upper and lower switching tube and simultaneously turns on, positive and negative busbar short circuit
Problem.During more specifically, be the situation that high level, i.e. corresponding states are 2-4 when signal PWM1 with PWM2 of input is different, defeated
The signal PWM1_1 gone out is same level with the signal PWM1 of corresponding input, the signal PWM2_2 of output and corresponding input
Signal PWM2 is same level.Such as, in state 3, PWM1 and PWM2 of input is respectively 1,0, after 3 grades of NAND gate process,
Signal PWM1_1 and PWM2_2 of output is respectively 1,0；Similarly, state 2 and state 4 are also identical situations.Above-mentioned 4 kinds
Corresponding the changing as shown in Figure 3 from the actual level being input to output of state.
This utility model provides a kind of hardware interlock protection circuit, relies on hardware circuit to process signal, it is ensured that
It is high during two output signal differences, it is achieved that signal interlocks；Such as, the signal after two process exported by this circuit should
During for controlling two circuit switched connected between positive and negative busbar in Fig. 1, software can be avoided relying on and be controlled two letters
Number time, if the problem of software failure or program fleet occurs, may result in PWM and interlock the generation of unsuccessfully phenomenon, thus cause
Switching tube simultaneously turns on up and down, the problem of positive and negative busbar short circuit.Improve Product Safety and stability, personal safety simultaneously obtains
Arrive more preferable guarantee；And the hardware interlock protection circuit principle that this utility model provides is simple, low cost.
The foregoing is only preferred embodiment of the present utility model, not in order to limit this utility model, all at this
Any amendment, equivalent and the improvement etc. made within the spirit of utility model and principle, should be included in this utility model
Protection domain within.
Claims (3)
1. a hardware interlock protection circuit, it is characterised in that including:
First pulse signal generation chip, the second pulse signal generation chip；
Described first pulse signal generation chip includes 3 grades of NAND gate, the respectively first NAND gate, the second NAND gate, the 3rd with
Not gate；Described second pulse signal generation chip includes 3 grades of NAND gate, the respectively the 4th NAND gate, the 5th NAND gate, the 6th with
Not gate；
The first input end input PWM1 signal of described first NAND gate, the second input input high level, described first with non-
The outfan of door connects the first input end of described 5th NAND gate；
The first input end of described second NAND gate inputs described PWM1 signal, and the second input connects described 4th NAND gate
Outfan, the outfan of described second NAND gate connects first, second input of described 3rd NAND gate；
The outfan output of described 3rd NAND gate PWM1 signal after treatment；
The first input end input high level of described 4th NAND gate, the second input input PWM2 signal；
Second input of described 5th NAND gate inputs described PWM2 signal, and the outfan of described 5th NAND gate connects described
First, second input of the 6th NAND gate；
The outfan output of described 6th NAND gate PWM2 signal after treatment.
2. hardware interlock protection circuit as claimed in claim 1, it is characterised in that the first input end of described first NAND gate
Connecting resistance R1, the second input of the first NAND gate connects resistance R2, and the second input of described 4th NAND gate connects electricity
Resistance R3；Wherein, R1=1K Ω, R2=10K Ω, R3=1K Ω.
3. hardware interlock protection circuit as claimed in claim 1, it is characterised in that also including electric capacity C1, described first with non-
Second input of door is by described electric capacity C1 ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620519645.0U CN205847227U (en) | 2016-05-31 | 2016-05-31 | Hardware interlock protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620519645.0U CN205847227U (en) | 2016-05-31 | 2016-05-31 | Hardware interlock protection circuit |
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| CN205847227U true CN205847227U (en) | 2016-12-28 |
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| CN201620519645.0U Active CN205847227U (en) | 2016-05-31 | 2016-05-31 | Hardware interlock protection circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108901099A (en) * | 2018-07-02 | 2018-11-27 | 惠州市华阳光电技术有限公司 | A kind of light modulation toning circuit based on two conducting wire connection LED components |
| CN110365201A (en) * | 2019-06-27 | 2019-10-22 | 芜湖康爱而电气有限公司 | A kind of PWM interlock protection circuit suitable for three level IGBT bridge arms |
| CN113839550A (en) * | 2021-09-29 | 2021-12-24 | 陕西省地方电力（集团）有限公司 | Bridge arm interlocking circuit suitable for SiC MOSFET |
-
2016
- 2016-05-31 CN CN201620519645.0U patent/CN205847227U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108901099A (en) * | 2018-07-02 | 2018-11-27 | 惠州市华阳光电技术有限公司 | A kind of light modulation toning circuit based on two conducting wire connection LED components |
| CN110365201A (en) * | 2019-06-27 | 2019-10-22 | 芜湖康爱而电气有限公司 | A kind of PWM interlock protection circuit suitable for three level IGBT bridge arms |
| CN110365201B (en) * | 2019-06-27 | 2021-01-19 | 安徽康爱而电气有限公司 | PWM interlocking protection circuit suitable for three-level IGBT bridge arm |
| CN113839550A (en) * | 2021-09-29 | 2021-12-24 | 陕西省地方电力（集团）有限公司 | Bridge arm interlocking circuit suitable for SiC MOSFET |
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Effective date of registration: 20180428 Granted publication date: 20161228 |
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| PD01 | Discharge of preservation of patent |
Date of cancellation: 20210428 Granted publication date: 20161228 |
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| PP01 | Preservation of patent right |
Effective date of registration: 20210428 Granted publication date: 20161228 |
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Date of cancellation: 20240428 Granted publication date: 20161228 |
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