CN203490827U - Signal acquisition terminal and test box data acquisition system - Google Patents
Signal acquisition terminal and test box data acquisition system Download PDFInfo
- Publication number
- CN203490827U CN203490827U CN201320629649.0U CN201320629649U CN203490827U CN 203490827 U CN203490827 U CN 203490827U CN 201320629649 U CN201320629649 U CN 201320629649U CN 203490827 U CN203490827 U CN 203490827U
- Authority
- CN
- China
- Prior art keywords
- pins
- resistance
- pin
- cpu
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Images
Landscapes
- Electronic Switches (AREA)
Abstract
The utility model discloses a signal acquisition terminal which comprises a processor, a signal acquisition interface, an RS-485 communication interface and an RS-232 communication interface, wherein the signal acquisition interface is connected with an I/O port of the processor; the RS-485 communication interface is connected with a second UART of the processor; and the RS-232 communication interface is connected with a third UART of the processor. The utility model also discloses a test box data acquisition system; multiple signal acquisition terminals are used in the system; each signal acquisition terminal is correspondingly connected with one test box; the signal acquisition interface and RS-232 communication interface of the signal acquisition terminal are connected with the test box; and the RS-485 communication interface is connected in an RS-485 network. In the utility model, the test boxes from different manufacturers can be subjected to equipment networking and centralized display and control; and in combination with large screen display, early warning and alarm about the key operation indexes of the test boxes are realized, and the working strength of the operator on duty is greatly reduced.
Description
Technical field
The utility model relates to a kind of harvester of industrial control equipment, particularly a kind of signals collecting terminal that adopts RS-485 network communication; The utility model also relates to the chamber data acquisition system (DAS) of using aforementioned signals collecting terminal.
Background technology
At the environment of electromechanical equipment and reliability, detect, in the burn-in test of electronic devices and components, electromagnetic compatibility test, equipment under test requires in chamber, to move different cycles according to test program.At test period, the running status of each chamber needs regularly manual inspection and record, also will intervene processing to emergent emergency condition.This mode of operation needs the special case of special messenger to be responsible for one to one, can meet the situation that test mission is few, chamber quantity is few.But in the face of ever-increasing chamber quantity and test mission and in night situation on duty, above-mentioned mode of operation allows staff prove definitely inferior.
The monitoring of test chamber apparatus critical excitation, has crucial impact to the normal operation of chamber system, and the collection of these facility switching amount signals, early warning and intervention are had great importance in real work.
Summary of the invention
Technical problem to be solved in the utility model is for the deficiencies in the prior art, a kind of signals collecting terminal is provided, the state of different brands, different model test chamber apparatus and operation information, centralized displaying on large-size screen monitors is also made fault pre-alarming in advance, greatly reduces operator on duty's working strength.
Another technical matters to be solved in the utility model has been to provide a kind of chamber data acquisition system (DAS) of using aforementioned signals collecting terminal.
Technical problem to be solved in the utility model is to realize by following technical scheme.The utility model is a kind of signals collecting terminal, is characterized in: comprise STM32F103 processor, signals collecting interface, RS-485 communication interface and RS-232 communication interface;
Signals collecting interface is connected on the I/O port of STM32F103 processor;
RS-485 communication interface is connected on the 2nd UART of STM32F103 processor;
RS-232 communication interface is connected on the 3rd UART of STM32F103 processor;
Described signals collecting interface is comprised of the acquisition module of three same structures, and the collection pin of INPUT0, INPUT1, INPUT2 is externally provided, and what be connected to STM32F103 processor is respectively INPUT0_CPU, INPUT1_CPU, INPUT2_CPU pin; INPUT0_CPU is connected to the I/O pin of STM32F103 processor P B12; INPUT1_CPU is connected to the I/O pin of STM32F103 processor P B13; INPUT2_CPU is connected to the I/O pin of STM32F103 processor P B14;
Described acquisition module is comprised of photoelectric coupled device A1, comparer IC1A, pilot lamp LED1 and resistance R 1, R2, R3, R4, R5, R6; Wherein INPUT0 is connected to one end of resistance R 1, and the other end of R1 is connected to 1 pin of photoelectric coupled device A1; 2 pins of A1 are connected to COM; Resistance R 2 is connected between 1 pin and 2 pins of A1; 3 pins of A1 are connected to signal ground, and 4 pins of A1 are pulled to 5V by resistance R 3, and are connected to "+" input of comparer IC1A, and "-" input of IC1A is connected to comparative level V+, and V+ sets 3.3V; The output of IC1A is pulled to 3.3V by resistance R 4, and one end of contact resistance R5, and the other end of R5 is connected to INPUT0_CPU; INPUT0_CPU is connected with the LED1 with current-limiting resistance R6, and R6 is pulled to 3.3V;
Described RS-485 communication interface is comprised of photoelectric coupling module, RS-485 transceiver, RS-485 bus immunity module and power supply DC-DC; RS-485 transceiver is chip SP485;
RS-485 bus immunity module is comprised of bus protection elements T VS, resistance R 108, R109, R110, capacitor C 103, C104, inductance L 1, L2;
8 pins of chip SP485 are connected to V_485, and 5 pins are connected to GND_485, and 6 pins of chip SP485 are connected to one end of inductance L 1, and the L1 other end is connected to A_485, and 7 pins of chip SP485 are connected to inductance L 2, and the L2 other end is connected to B_485; Resistance R 109 is connected between 6 pins and 7 pins of chip SP485; Resistance R 108 is connected between 7 pins and V_485 of chip SP485; Resistance R 110 is connected between 6 pins and GND_485 of chip SP485; One end of capacitor C 104 is connected to 7 pins of chip SP485, and the other end of C104 is connected to GND_485; One end of capacitor C 103 is connected to 6 pins of chip SP485, and the other end of C103 is connected to GND_485; 1 pin of TVS is connected to A_485, and 2 pins are connected to B_485, and 3 pins are connected to GND_485;
Photoelectric coupling module composition buffer circuit, by high-speed photoelectric coupler part A101, A102, common optoelectronic coupler part A103, resistance R 101, R102, R103, R104, R105, R106, R107 and capacitor C 101, C102, formed;
6 pins of high-speed photoelectric coupler part A101 are pulled to 3.3V by resistance R 101, are connected with RX_CPU simultaneously; 2 pins of A101 are connected to V_485 voltage by resistance R 105; 3 pins of A101 are connected to 1 pin of chip SP485; The VCC pin of A101 is connected to 3.3V, and the GND pin of A101 is connected to signal ground; Capacitor C 101 is connected in 3.3V and signal ground;
2 pins of A102 are connected to 3.3V by resistance R 104; 3 pins of A102 are connected to TX_CPU; 6 pins of A102 are pulled to V_485 by resistance R 107, are connected to 4 pins of SP485 simultaneously; The VCC pin of A102 is connected to V_485, and the GND pin of A102 is connected to GND_485; Capacitor C 101 is connected in V_485 and GND_485;
1 pin of A103 is connected to 3.3V by resistance R 102, and 2 pins of A103 are connected to TX_EN_CPU, and resistance R 103 is connected between 1 pin and 2 pins of A103; 4 pins of A103 are connected to V_485, and 3 pins of A103 are pulled down to GND_485 by resistance R 106, are connected between 2 pins and 3 pins of SP485 simultaneously;
RX_CPU, the TX_CPU of the UART serial ports of STM32F103 processor connects RO, the DI pin of chip SP485 by photoelectric isolating circuit, control signal TX_EN_CPU through photoelectric isolating circuit go control chip SP485 DE and/RE pin.
The invention also discloses a kind of chamber data acquisition system (DAS), be characterized in, this system is used several signals collecting terminals as described in above technical scheme, each signals collecting terminal and 1 corresponding connection of chamber, signals collecting interface and the RS-232 communication interface of signals collecting terminal are connected in chamber, RS-485 communication interface is connected in RS-485 network, and the information exchange that different tests case collects is crossed RS-485 network and sent to central control room and focus on.
Signal in chamber enters acquisition module through INPUT0; COM be in chamber publicly; When INPUT0 is high level, pilot lamp LED1 lights, now photoelectric coupled device A1 conducting, comparer IC1A+to hold as low level, comparer is output as low level, and the signal that STM32F103 processor collects is low level; When INPUT0 is low level, pilot lamp LED1 extinguishes, now not conducting of photoelectric coupled device A1, comparer IC1A+to hold as high level, comparer is output as high level, and the signal that STM32F103 processor collects is high level;
The TX_EN_CPU signal of being exported by STM32F103 processor is one state, the DE of chip SP485 and/RE pin is one state, transmitter is effective, receiver forbids, now STM32F103 processor sends data byte by RS-485 bus;
TX_EN_CPU signal is " 0 " state, the DE of chip SP485 and/RE pin be " 0 " state, transmitter forbids, receiver is effective, now STM32F103 processor reception is from the data byte of RS-485 bus; Resistance R 106 and photoelectric coupled device A103 form the inhibition circuit that powers on simultaneously, during guaranteeing that STM32F103 processor powers on, the DE that resistance R 106 connects and/RE pin is in " 0 " state, avoid having a plurality of transceivers to be operated in " transmission " state in a RS-485 network simultaneously, cause loss of data, produce mistake, make RS-485 network paralysis;
Be connected to A_485 pin pull-up resistor R108, be connected to B_485 pin pull down resistor R110 for guaranteeing that connectionless SP485 chip is in idle condition, network failure protection is provided.
The utility model is connected in test chamber apparatus by data acquisition interface, RS-232 communication interface, utilize above-mentioned two interfaces to collect the service data of chamber, by RS-485 communication interface, the service data collecting is aggregated into central control room, through respective handling, in large-screen display, shows.
The utility model both can acquisition test case by RS-232 interface test figure, can send again the steering order of central control room.
The utility model obtains the data of switching signal amount by acquisition interface, while collecting high level signal, corresponding LED lamp is lighted; While collecting low level signal, corresponding LED lamp extinguishes.
The signals collecting interface of the utility model design provides the collection of switch amount signal; The RS-232 interface of the utility model design provides the running status of chamber and the method for operation is gathered and controlled; The network communication module of the RS-485 of the utility model design, is connected with the 2nd UART interface of STM32F103 processor, and photoelectric coupling isolation and the inhibit feature that powers on are provided, and has realized RS-485 network communicating function.
Running status and the test figure of the signals collecting interface designing by the utility model and RS-232 interface acquisition test case, the large-size screen monitors that send to Central Control Room by RS-485 network show; The control command of the Central Control Room transmitting by RS-485 network sends in chamber through RS-232 interface, adjusts the method for operation of chamber.
A kind of data acquisition of networking and the Long-distance Control mode of providing is provided, by the utility model, the chamber of different manufacturers can be carried out to equipment networking, centralized displaying and control, in conjunction with large screen display, the crucial operating index of chamber is carried out to early warning and warning, to greatly reduce operator on duty's working strength, particularly for some, be not suitable for personnel's chamber environment at the scene and have more use value.
Accompanying drawing explanation
Fig. 1 is the module map of the utility model signals collecting terminal;
Fig. 2 is the system architecture diagram of the utility model system;
Fig. 3 is the line graph of signals collecting interface;
Fig. 4 is RS-485 communication interface figure.
Embodiment
Referring to accompanying drawing, further describe concrete technical scheme of the present utility model, so that those skilled in the art understands the utility model further, and do not form the restriction to its right.
Embodiment 1, and with reference to Fig. 1, Fig. 3-4, a kind of signals collecting terminal, comprises STM32F103 processor, signals collecting interface, RS-485 communication interface and RS-232 communication interface;
Signals collecting interface is connected on the I/O port of STM32F103 processor;
RS-485 communication interface is connected on the 2nd UART of STM32F103 processor;
RS-232 communication interface is connected on the 3rd UART of STM32F103 processor;
Described signals collecting interface is comprised of the acquisition module of three same structures, and the collection pin of INPUT0, INPUT1, INPUT2 is externally provided, and what be connected to STM32F103 processor is respectively INPUT0_CPU, INPUT1_CPU, INPUT2_CPU pin; INPUT0_CPU is connected to the I/O pin of STM32F103 processor P B12; INPUT1_CPU is connected to the I/O pin of STM32F103 processor P B13; INPUT2_CPU is connected to the I/O pin of STM32F103 processor P B14;
Described acquisition module is comprised of photoelectric coupled device A1, comparer IC1A, pilot lamp LED1 and resistance R 1, R2, R3, R4, R5, R6; Wherein INPUT0 is connected to one end of resistance R 1, and the other end of R1 is connected to 1 pin of photoelectric coupled device A1; 2 pins of A1 are connected to COM; Resistance R 2 is connected between 1 pin and 2 pins of A1; 3 pins of A1 are connected to signal ground, and 4 pins of A1 are pulled to 5V by resistance R 3, and are connected to "+" input of comparer IC1A, and "-" input of IC1A is connected to comparative level V+, and V+ sets 3.3V; The output of IC1A is pulled to 3.3V by resistance R 4, and one end of contact resistance R5, and the other end of R5 is connected to INPUT0_CPU; INPUT0_CPU is connected with the LED1 with current-limiting resistance R6, and R6 is pulled to 3.3V;
Described RS-485 communication interface is comprised of photoelectric coupling module, RS-485 transceiver, RS-485 bus immunity module and power supply DC-DC; RS-485 transceiver is chip SP485;
RS-485 bus immunity module is comprised of bus protection elements T VS, resistance R 108, R109, R110, capacitor C 103, C104, inductance L 1, L2;
8 pins of chip SP485 are connected to V_485, and 5 pins are connected to GND_485, and 6 pins of chip SP485 are connected to one end of inductance L 1, and the L1 other end is connected to A_485, and 7 pins of chip SP485 are connected to inductance L 2, and the L2 other end is connected to B_485; Resistance R 109 is connected between 6 pins and 7 pins of chip SP485; Resistance R 108 is connected between 7 pins and V_485 of chip SP485; Resistance R 110 is connected between 6 pins and GND_485 of chip SP485; One end of capacitor C 104 is connected to 7 pins of chip SP485, and the other end of C104 is connected to GND_485; One end of capacitor C 103 is connected to 6 pins of chip SP485, and the other end of C103 is connected to GND_485; 1 pin of TVS is connected to A_485, and 2 pins are connected to B_485, and 3 pins are connected to GND_485;
Photoelectric coupling module composition buffer circuit, by high-speed photoelectric coupler part A101, A102, common optoelectronic coupler part A103, resistance R 101, R102, R103, R104, R105, R106, R107 and capacitor C 101, C102, formed;
6 pins of high-speed photoelectric coupler part A101 are pulled to 3.3V by resistance R 101, are connected with RX_CPU simultaneously; 2 pins of A101 are connected to V_485 voltage by resistance R 105; 3 pins of A101 are connected to 1 pin of chip SP485; The VCC pin of A101 is connected to 3.3V, and the GND pin of A101 is connected to signal ground; Capacitor C 101 is connected in 3.3V and signal ground;
2 pins of A102 are connected to 3.3V by resistance R 104; 3 pins of A102 are connected to TX_CPU; 6 pins of A102 are pulled to V_485 by resistance R 107, are connected to 4 pins of SP485 simultaneously; The VCC pin of A102 is connected to V_485, and the GND pin of A102 is connected to GND_485; Capacitor C 101 is connected in V_485 and GND_485;
1 pin of A103 is connected to 3.3V by resistance R 102, and 2 pins of A103 are connected to TX_EN_CPU, and resistance R 103 is connected between 1 pin and 2 pins of A103; 4 pins of A103 are connected to V_485, and 3 pins of A103 are pulled down to GND_485 by resistance R 106, are connected between 2 pins and 3 pins of SP485 simultaneously;
RX_CPU, the TX_CPU of the UART serial ports of STM32F103 processor connects RO, the DI pin of chip SP485 by photoelectric isolating circuit, control signal TX_EN_CPU through photoelectric isolating circuit go control chip SP485 DE and/RE pin.
Embodiment 2, with reference to Fig. 2, a kind of chamber data acquisition system (DAS), this system is used several signals collecting terminals as claimed in claim 1, each signals collecting terminal and 1 corresponding connection of chamber, signals collecting interface and the RS-232 communication interface of signals collecting terminal are connected in chamber, and RS-485 communication interface is connected in RS-485 network, and the information exchange that different tests case collects is crossed RS-485 network and sent to central control room and focus on;
Signal in chamber enters acquisition module through INPUT0; COM be in chamber publicly; When INPUT0 is high level, pilot lamp LED1 lights, now photoelectric coupled device A1 conducting, comparer IC1A+to hold as low level, comparer is output as low level, and the signal that STM32F103 processor collects is low level; When INPUT0 is low level, pilot lamp LED1 extinguishes, now not conducting of photoelectric coupled device A1, comparer IC1A+to hold as high level, comparer is output as high level, and the signal that STM32F103 processor collects is high level;
The TX_EN_CPU signal of being exported by STM32F103 processor is one state, the DE of chip SP485 and/RE pin is one state, transmitter is effective, receiver forbids, now STM32F103 processor sends data byte by RS-485 bus;
TX_EN_CPU signal is " 0 " state, the DE of chip SP485 and/RE pin be " 0 " state, transmitter forbids, receiver is effective, now STM32F103 processor reception is from the data byte of RS-485 bus; Resistance R 106 and photoelectric coupled device A103 form the inhibition circuit that powers on simultaneously, during guaranteeing that STM32F103 processor powers on, the DE that resistance R 106 connects and/RE pin is in " 0 " state, avoid having a plurality of transceivers to be operated in " transmission " state in a RS-485 network simultaneously, cause loss of data, produce mistake, make RS-485 network paralysis;
Be connected to A_485 pin pull-up resistor R108, be connected to B_485 pin pull down resistor R110 for guaranteeing that connectionless SP485 chip is in idle condition, network failure protection is provided.
Claims (2)
1. a signals collecting terminal, is characterized in that: comprise STM32F103 processor, signals collecting interface, RS-485 communication interface and RS-232 communication interface;
Signals collecting interface is connected on the I/O port of STM32F103 processor;
RS-485 communication interface is connected on the 2nd UART of STM32F103 processor;
RS-232 communication interface is connected on the 3rd UART of STM32F103 processor;
Described signals collecting interface is comprised of the acquisition module of three same structures, and the collection pin of INPUT0, INPUT1, INPUT2 is externally provided, and what be connected to STM32F103 processor is respectively INPUT0_CPU, INPUT1_CPU, INPUT2_CPU pin; INPUT0_CPU is connected to the I/O pin of STM32F103 processor P B12; INPUT1_CPU is connected to the I/O pin of STM32F103 processor P B13; INPUT2_CPU is connected to the I/O pin of STM32F103 processor P B14;
Described acquisition module is comprised of photoelectric coupled device A1, comparer IC1A, pilot lamp LED1 and resistance R 1, R2, R3, R4, R5, R6; Wherein INPUT0 is connected to one end of resistance R 1, and the other end of R1 is connected to 1 pin of photoelectric coupled device A1; 2 pins of A1 are connected to COM; Resistance R 2 is connected between 1 pin and 2 pins of A1; 3 pins of A1 are connected to signal ground, and 4 pins of A1 are pulled to 5V by resistance R 3, and are connected to "+" input of comparer IC1A, and "-" input of IC1A is connected to comparative level V+, and V+ sets 3.3V; The output of IC1A is pulled to 3.3V by resistance R 4, and one end of contact resistance R5, and the other end of R5 is connected to INPUT0_CPU; INPUT0_CPU is connected with the LED1 with current-limiting resistance R6, and R6 is pulled to 3.3V;
Described RS-485 communication interface is comprised of photoelectric coupling module, RS-485 transceiver, RS-485 bus immunity module and power supply DC-DC; RS-485 transceiver is chip SP485;
RS-485 bus immunity module is comprised of bus protection elements T VS, resistance R 108, R109, R110, capacitor C 103, C104, inductance L 1, L2;
8 pins of chip SP485 are connected to V_485, and 5 pins are connected to GND_485, and 6 pins of chip SP485 are connected to one end of inductance L 1, and the L1 other end is connected to A_485, and 7 pins of chip SP485 are connected to inductance L 2, and the L2 other end is connected to B_485; Resistance R 109 is connected between 6 pins and 7 pins of chip SP485; Resistance R 108 is connected between 7 pins and V_485 of chip SP485; Resistance R 110 is connected between 6 pins and GND_485 of chip SP485; One end of capacitor C 104 is connected to 7 pins of chip SP485, and the other end of C104 is connected to GND_485; One end of capacitor C 103 is connected to 6 pins of chip SP485, and the other end of C103 is connected to GND_485; 1 pin of TVS is connected to A_485, and 2 pins are connected to B_485, and 3 pins are connected to GND_485;
Photoelectric coupling module composition buffer circuit, by high-speed photoelectric coupler part A101, A102, common optoelectronic coupler part A103, resistance R 101, R102, R103, R104, R105, R106, R107 and capacitor C 101, C102, formed;
6 pins of high-speed photoelectric coupler part A101 are pulled to 3.3V by resistance R 101, are connected with RX_CPU simultaneously; 2 pins of A101 are connected to V_485 voltage by resistance R 105; 3 pins of A101 are connected to 1 pin of chip SP485; The VCC pin of A101 is connected to 3.3V, and the GND pin of A101 is connected to signal ground; Capacitor C 101 is connected in 3.3V and signal ground;
2 pins of A102 are connected to 3.3V by resistance R 104; 3 pins of A102 are connected to TX_CPU; 6 pins of A102 are pulled to V_485 by resistance R 107, are connected to 4 pins of SP485 simultaneously; The VCC pin of A102 is connected to V_485, and the GND pin of A102 is connected to GND_485; Capacitor C 101 is connected in V_485 and GND_485;
1 pin of A103 is connected to 3.3V by resistance R 102, and 2 pins of A103 are connected to TX_EN_CPU, and resistance R 103 is connected between 1 pin and 2 pins of A103; 4 pins of A103 are connected to V_485, and 3 pins of A103 are pulled down to GND_485 by resistance R 106, are connected between 2 pins and 3 pins of SP485 simultaneously;
RX_CPU, the TX_CPU of the UART serial ports of STM32F103 processor connects RO, the DI pin of chip SP485 by photoelectric isolating circuit, control signal TX_EN_CPU through photoelectric isolating circuit go control chip SP485 DE and/RE pin.
2. a chamber data acquisition system (DAS), it is characterized in that, this system is used several signals collecting terminals as claimed in claim 1, each signals collecting terminal and 1 corresponding connection of chamber, signals collecting interface and the RS-232 communication interface of signals collecting terminal are connected in chamber, RS-485 communication interface is connected in RS-485 network, and the information exchange that different tests case collects is crossed RS-485 network and sent to central control room and focus on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320629649.0U CN203490827U (en) | 2013-10-13 | 2013-10-13 | Signal acquisition terminal and test box data acquisition system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320629649.0U CN203490827U (en) | 2013-10-13 | 2013-10-13 | Signal acquisition terminal and test box data acquisition system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203490827U true CN203490827U (en) | 2014-03-19 |
Family
ID=50261641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320629649.0U Withdrawn - After Issue CN203490827U (en) | 2013-10-13 | 2013-10-13 | Signal acquisition terminal and test box data acquisition system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203490827U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489302A (en) * | 2013-10-13 | 2014-01-01 | 连云港杰瑞深软科技有限公司 | Signal collection terminal and test box data collection system |
| CN108986431A (en) * | 2018-08-08 | 2018-12-11 | 江苏拓米洛环境试验设备有限公司 | Chamber cloud alarm and protection system |
-
2013
- 2013-10-13 CN CN201320629649.0U patent/CN203490827U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489302A (en) * | 2013-10-13 | 2014-01-01 | 连云港杰瑞深软科技有限公司 | Signal collection terminal and test box data collection system |
| CN103489302B (en) * | 2013-10-13 | 2016-03-02 | 连云港杰瑞深软科技有限公司 | A kind of signals collecting terminal and chamber data acquisition system (DAS) |
| CN108986431A (en) * | 2018-08-08 | 2018-12-11 | 江苏拓米洛环境试验设备有限公司 | Chamber cloud alarm and protection system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103489302B (en) | A kind of signals collecting terminal and chamber data acquisition system (DAS) | |
| CN203490827U (en) | Signal acquisition terminal and test box data acquisition system | |
| CN103885375A (en) | Console displaying and monitoring system | |
| CN105933170A (en) | Profibus data acquisition system | |
| CN102723995B (en) | A kind of active light module controller | |
| CN103529763B (en) | Factory Power Monitoring System | |
| CN208207547U (en) | Suitable for network edition RTU device | |
| CN204495976U (en) | A kind of alarm device being applied to power supply monitoring system | |
| CN110244176A (en) | A kind of high-tension connector fault detection system and high-voltage power system | |
| CN206003089U (en) | A kind of idle call multifunctional signal switching device | |
| CN212992040U (en) | Monitoring device for air conditioner communication line | |
| CN210466075U (en) | Information acquisition and control device for clothes hanger hanging system | |
| CN102647229A (en) | XFP (10 Gigabit Small Form Factor Pluggable) interface optical module self-loop method and device | |
| CN208862636U (en) | Transforming plant DC power supply smart measure and control device | |
| CN103346894B (en) | Chip chamber interface conversion circuit and the network equipment | |
| CN218587174U (en) | Communication isolation circuit and switching power supply | |
| CN106200620B (en) | A kind of intelligent terminal outputs circuit self checking method and feedback circuit | |
| CN221263821U (en) | RS485 communication circuit with optical coupling isolation and communication system | |
| CN202796000U (en) | Trigger circuit of mining display control box | |
| CN212850537U (en) | Bus networking device and system | |
| CN211180807U (en) | Plug-and-play serial port expansion card device based on CAN bus | |
| CN213715730U (en) | Data acquisition device | |
| CN107863957A (en) | MOSFET digital quantity output circuits | |
| CN217607826U (en) | Ethernet interface circuit | |
| CN204258840U (en) | A kind of isolating and protecting device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140319 Effective date of abandoning: 20160302 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20140319 Effective date of abandoning: 20160302 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |