CN1866231A - Method for implementing logic interrupt priority in embedded real-time operating system - Google Patents
Method for implementing logic interrupt priority in embedded real-time operating system Download PDFInfo
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- CN1866231A CN1866231A CN 200510069397 CN200510069397A CN1866231A CN 1866231 A CN1866231 A CN 1866231A CN 200510069397 CN200510069397 CN 200510069397 CN 200510069397 A CN200510069397 A CN 200510069397A CN 1866231 A CN1866231 A CN 1866231A
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Abstract
The related method to set logic interruption PRI in ISR of ERTOS comprises: a. according to correlation among all PRIs in ISR of ERTOS and the corresponding mask bits in IMR, calculating configuration parameters for PIC; b. after receiving interruption trigger from peripheral, the CPU sets all mask bits as PIC configuration, and executes the interruption with level free to hardware PRI limit in PIC.
Description
Technical field
The present invention relates in embedded real-time operating system (ERTOS) to the treatment technology of interrupt priority level particularly a kind of method that in ERTOS, realizes the logic interrupt priority level.
Background technology
At present, the peripheral hardware among the ERTOS can adopt the mode of interruption to CPU request service.Each interrupts all being provided with corresponding interrupt service routine (ISR).When the peripheral hardware among the ERTOS passed through corresponding interrupt source to CPU triggering interruption, CPU carried out the corresponding ISR of interruption that is triggered, and finishes this interrupt operation.Owing to can have a plurality of peripheral hardware collaborative works among the ERTOS, correspondingly, can have a plurality of interruptions among the ERTOS, for the ease of the management of CPU to a plurality of interruptions, CPU can encapsulate programmable interrupt controller (PIC) and come the peripheral hardware of a plurality of ERTOS is controlled by the interruption of the interrupt source triggering of correspondence.
In PIC or in the Interrupt Process of the CPU part, also has interrupt mask register (IMR), each peripheral hardware all triggers by interrupt source and interrupts, a mask bit among all corresponding IMR of each interrupt source, CPU is provided with situation according to the mask bit among the IMR and determines whether to respond the interruption of peripheral hardware by the correspondence that interrupt source triggered among the ERTOS, thereby makes CPU carry out this interrupt operation.
When CPU carries out interrupt operation, can introduce the notion of hardware interrupts priority level in advance, each interrupts all can being provided with a hardware interrupts priority, the progression of hardware interrupts priority is provided with by PIC, usually the progression of hardware interrupts priority can be less than the interrupt source number that PIC provides, this is in order to reduce the number of times of CPU response by interruption that interrupt source triggers, to alleviate the load of CPU handling interrupt.For example: the interrupt source number that PIC provides is 64, but the progression of the interrupt priority level of its setting is 8.
At present, the different CPU of ERTOS is also different to interrupting operating process, and different CPU can be divided into two classes, the first kind to the different operating process of interrupting: CPU masked segment in current interrupt operation process interrupts; Second class: CPU shields all interruptions in current interrupt operation process.
For first kind CPU as shown in Figure 1 to the operating process interrupted:
Step 100, ERTOS carry out initialization, and each interruption corresponding hardware interrupt priority level of ERTOS is set in PIC.
Peripheral hardware among step 101, the ERTOS triggers to CPU and interrupts.
Have no progeny during step 102, CPU receive, be set to this interruption corresponding hardware interrupt priority level according to the priority level that CPU is set among the PIC.
The ISR of the interruption correspondence that is received in step 103, the CPU execution in step 102.
CPU begin to respond one interrupt executing this interrupt corresponding ISR during this period of time in, than CPU just when the high interruption of processing hardware interrupt priority level is triggered, CPU is other with the interruption corresponding hardware interrupt priority level that is triggered by the priority level that relatively self is provided with, judging is triggered interrupts and can be responded, then stop to carry out the ISR of the current interruption correspondence of carrying out, being set to be triggered according to the priority level that CPU is set of PIC, to interrupt the corresponding hardware interrupt priority level other, interrupts corresponding ISR then carry out this.Than CPU just when the interruption low and that equal the disconnected priority of CPU present of processing hardware interrupt priority level is triggered, CPU is other with the interruption corresponding hardware interrupt priority level that is triggered by the priority level that relatively self is provided with, judging is triggered interrupts not responded, and then shields this interruption.
For this situation, because the hardware interrupts priority progression that PIC is provided with is less than the number of interrupt source, make some interrupt sources can be set to same hardware interrupts priority, when having when responding the identical down trigger of the hardware interrupts priority of interruption with CPU, then PIC can't respond and initiate the interruption that triggers.
For the second class CPU as shown in Figure 2 to the operating process interrupted:
Step 200, ERTOS carry out initialization, and ERTOS is set in PIC, and each interrupts the corresponding hardware interrupt priority level.
Peripheral hardware among step 201, the ERTOS triggers to CPU by PIC and interrupts.
Have no progeny during step 202, CPU receive, IMR is set,, perhaps close the PIC global interrupt all set of interrupt mask bits all among the IMR.
The ISR of the interruption correspondence that is received in step 203, the CPU execution in step 202.
CPU begin to respond a hardware interrupts finishes to the ISR that executes this hardware interrupts correspondence during this period of time in, PIC can close global interrupt or because CPU detects the set of all interrupt mask bits of IMR, thus all interruptions can not responded.After CPU handled the corresponding ISR of this interruption, CPU opened the PIC global interrupt again.This class CPU does not relate to the hardware interrupts priority of interruption to the operating process of interrupting, and the interruption higher than the hardware interrupts priority of the current performed interruption of CPU also can't interrupt the current performed interruption of CPU, carries out in advance.
From the operating process of above-mentioned two class CPU to interrupting, the operating process of CPU does not relate to the hardware interrupts priority of interruption, the interruption higher than the hardware interrupts priority of the current performed interruption of CPU also can't interrupt the current performed interruption of CPU, carries out in advance; Though the operating process of CPU relates to the hardware interrupts priority of interruption, and the interruption higher than the hardware interrupts priority of the current performed interruption of CPU can interrupt the current performed interruption of CPU, carry out in advance, but because the number of levels that hardware interrupts priority is provided with is less than the interrupt source number, the situation that a plurality of interruptions must be set to same hardware interrupts priority can occur, interrupt real interrupt priority level and can't really distinguish each.Further, because the number of levels that hardware interrupts priority is provided with is relevant with PIC, so encapsulate the interrupt source that the ERTOS of different PIC can't provide the number of levels with unified hardware interrupts priority for the user.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of method that realizes the logic interrupt priority level in ERTOS, this method can realize that the interrupt priority level progression that is provided with is not subjected to the influence of the hardware interrupts priority progression of PIC setting, the assurance interruption higher than the logic interrupt priority level of the current performed interruption of CPU can interrupt the current performed interruption of CPU, carry out in advance, thereby make the ERTOS of the different PIC of encapsulation that the interrupt source with unified interrupt priority level progression is provided for the user.
According to above-mentioned purpose, technical scheme of the present invention is achieved in that
In embedded real-time operating system ERTOS, realize the method for logic interrupt priority level, the logic interrupt priority level of this interruption is set among the interrupt service routine ISR of the interruption correspondence in ERTOS, the number of interrupt source under set logic interrupt priority level progression equals to interrupt at the most, this method also comprises:
A, ERTOS initialization, according to relativeness between the logic interrupt priority level of all ISR settings among the ERTOS and the corresponding mask bit that interrupts affiliated interrupt source in interrupt mask register IMR correspondence of all ISR, calculate the programmable interrupt controller PIC configuration item of interruption;
B, CPU receive that peripheral hardware triggered among the ERTOS in have no progeny, after according to the PIC configuration item that interrupts each mask bit of IMR being provided with, carry out this interruption.
When the interruption that is higher than the performed interruption of described step b when the logic interrupt priority level was triggered, this method also comprised:
C1, CPU receive peripheral hardware and are higher than the interruption of the performed interruption of step b by the logic interrupt priority level that interrupt source triggered, and the interruption that is triggered according to definite this interrupt source of the mask bit value of setting among the corresponding IMR of this interrupt source can be responded, and responds this interruption;
After d1, CPU are higher than the interruption of the performed interruption of step b according to the logic interrupt priority level PIC configuration item is reset each mask bit of IMR, carry out this interruption.
Be less than or equal to described step b when carrying out the interruption of interrupting and being triggered when the logic interrupt priority level, this method also comprises:
C2, CPU receive peripheral hardware is less than or equal to the performed interruption of step b by the logic interrupt priority level that interrupt source triggered interruption, determine that according to the mask bit value of setting among the corresponding IMR of this interrupt source the interruption that this interrupt source is triggered can not be responded, have no progeny in the continuation execution of step b execution, the response logic interrupt priority level is less than or equal to the interruption of the performed interruption of step b again;
After d2, CPU are less than or equal to the interruption of the performed interruption of step b according to the logic interrupt priority level PIC configuration item is reset each mask bit of IMR, carry out this interruption.
For described first kind CPU, before each mask bit to IMR was provided with, this method also comprises: CPU closed the PIC global interrupt earlier, and current logic interrupt priority level is set to minimum;
Before step b carried out this interruption, this method also comprised: CPU opens the PIC global interrupt.
For the described second class CPU, before each mask bit to IMR was provided with, this method also comprises: CPU closed the PIC global interrupt earlier;
Before step b carried out this interruption, this method also comprised: CPU opens the PIC global interrupt.
For the task among the ERTOS is provided with the PIC configuration item, before step b, this method also comprises:
B1, CPU execute the task, and are provided with according to the PIC configuration item of task setting each mask bit to IMR;
Had no progeny during peripheral hardware triggers in the described ERTOS of receiving of step b, also comprised:
B2, CPU determine according to the mask bit value of setting among the corresponding IMR of interrupt source that is triggered under interrupting whether this interruption can be responded, if, the subsequent process of execution in step b; Otherwise, continue after the task of executing the subsequent process of execution in step b again.
Described PIC configuration item is the Configuration Values corresponding to each mask bit of IMR, and each mask bit of this IMR and interruption are corresponding one by one.
When interrupting being responded, the not set of mask bit in the described PIC configuration item corresponding to the IMR of interrupt source under this interruption; When interrupting being responded, the mask bit set in the described PIC configuration item corresponding to the IMR of interrupt source under this interruption.
From such scheme as can be seen, the present invention is provided with the logic interrupt priority level in advance the ISR that interrupts correspondence, when the ERTOS initialization, to interruption the PIC configuration item is set according to the mask bit of interrupt source in IMR under relativeness between the logic interrupt priority level of all ISR settings of ERTOS and the corresponding interruption of ISR, in the middle of open close when crossing place interrupt source and triggering, be arranged on mask bit among the IMR according to the PIC configuration item of this interruption.Because the logic interrupt priority level progression of setting of the present invention is not subjected to the influence of the hardware interrupts priority progression of PIC setting, so the progression that the logic interrupt priority level can be set can equal the number of interrupt source at most, the assurance interruption higher than the logic interrupt priority level of the current performed interruption of CPU can interrupt the current performed interruption of CPU, carries out in advance.Thereby make the ERTOS of the different PIC of encapsulation that the interrupt source with unified interrupt priority level progression is provided for the user.Further, task also can set in advance the PIC configuration item, when task run, is arranged on mask bit among the IMR according to the PIC configuration item of task setting, thereby shields the interruption that some need shield.
Description of drawings
Fig. 1 is the operating process process flow diagram of first kind CPU to interrupting of prior art;
Fig. 2 is the operating process process flow diagram of the second class CPU to interrupting of prior art;
Fig. 3 is the operating process process flow diagram of first kind CPU of the present invention to interrupting;
Fig. 4 is the operating process process flow diagram of the second class CPU of the present invention to interrupting;
Fig. 5 is being the process flow diagram of first kind CPU after interrupting that the logic interrupt priority level is set to the operation embodiment one of interruption for the present invention;
Fig. 6 is being the process flow diagram of first kind CPU after interrupting that the logic interrupt priority level is set to the operation embodiment two of interruption for the present invention.
Embodiment
In order to make the purpose, technical solutions and advantages of the present invention clearer, below lift specific embodiment and, the present invention is described in more detail with reference to accompanying drawing.
The present invention is provided with interrupt priority level in order to realize to each interruption, rather than same hardware interrupts priority is set for as prior art a plurality of interruptions, has introduced the notion of logic interrupt priority level.The present invention is provided with the logic interrupt priority level of this interruption in interrupting corresponding ISR when the ISR that interrupts correspondence is set.
The present invention is not the priority of the interrupt source on the hardware meaning at the logic interrupt priority level that ISR is provided with, but in logic, is that the mask bit of other interrupt source correspondences by dynamic shielding IMR embodies.For example: when the high ISR of logic interrupt priority level moves, the mask bit of the interrupt source correspondence that other all set logic interrupt priority levels are low all is set, but the hardware interrupts priority of the interruption that interrupt source triggered of these conductively-closeds might be higher than moving ISR corresponding hardware interrupts priority of interrupting.
For whole ERTOS, the ISR of all interruptions is static to be created.After the ERTOS operation, do not allow to create again and interrupt corresponding ISR, do not allow to change yet and create the logic interrupt priority level that ISR is provided with.This is because after the ERTOS operation, ERTOS can calculate the PIC configuration item of respective interrupt correspondence according to the logic interrupt priority level that each ISR is provided with, this calculating depends on the logic interrupt priority level that each ISR is provided with, if the logic interrupt priority level that ISR is provided with has carried out change or created ISR again, then can have influence on ERTOS and calculate the PIC configuration item that other interrupt correspondence.
The present invention is after ERTOS operation, and ERTOS can calculate the PIC configuration item of respective interrupt correspondence according to the logic interrupt priority level that each ISR is provided with, and the content of interrupting corresponding PIC configuration item is to each mask bit of IMR information of set whether.
ERTOS calculates the process of interrupting corresponding PIC configuration item: at the ERTOS initial phase, according to the relativeness between the logic interrupt priority level that is provided with among all ISR in the ERTOS, calculate the corresponding PIC configuration item that interrupts of each ISR.For example: be provided with ISRA, ISRB, ISRC and ISRD among the ERTOS, corresponding logic interrupt priority level is respectively 1,3,2,4, and the corresponding mask bit that interrupts place interrupt source correspondence in IMR of institute is respectively the 1st, the 2nd, the 3rd and the 4th.Like this,, just know that the logic interrupt priority level of ISRA is the highest at the ERTOS initial phase, ISRA the corresponding PIC configuration item that interrupts be set to 0000, other interruption all mustn't interrupt the execution of ISRA; For ISRB, the logic interrupt priority level of ISRA and ISRC is not higher than ISRB, ISRB the corresponding PIC configuration item that interrupts be set to 1010, the interruption of ISRA and ISRC correspondence can interrupt the execution of ISRB; For ISRC, the logic interrupt priority level of ISRA is higher than ISRC, ISRC the corresponding PIC configuration item that interrupts be set to 1000, the interruption of ISRA correspondence can interrupt the execution of ISRC; For ISRD, the logic interrupt priority level of ISRA, ISRB and ISRC is higher than ISRD, ISRD the corresponding PIC configuration item that interrupts be set to 1110, the interruption of ISRA, ISRB and ISRC correspondence can interrupt the execution of ISRC.
Fig. 3 is being the operational flowchart of first kind CPU to interrupting after interrupting that the logic interrupt priority level is set for the present invention, and its concrete steps are:
Step 300, ERTOS carry out initialization, calculate the corresponding PIC configuration item that interrupts of each ISR according to the logic interrupt priority level that sets in advance among all ISR of ERTOS.
Calculating is according to the mask bit among the IMR of corresponding relation between the logic interrupt priority level that sets in advance among all ISR and the corresponding interruption of ISR place interrupt source correspondence.
Peripheral hardware among step 301, the ERTOS triggers to CPU by interrupt source and interrupts.
Have no progeny during step 302, CPU receive, CPU closes the PIC global interrupt.
Step 303, CPU interrupt priority level are set to minimum, and CPU can respond any interruption under this state.
Step 304, CPU receive the PIC configuration item that interrupts according to step 302 IMR are configured, the logic interrupt priority level is received the mask bit that interrupts low and the interruption place interrupt source correspondence that equals than step 302 carry out set, as reset, the interruption that triggers by the interrupt source corresponding to the mask bit that passes through set can not be responded by CPU.
Step 305, CPU open the PIC global interrupt.
The ISR of the interruption correspondence that is received in step 306, the execution in step 302.
Fig. 4 is being the operational flowchart of the second class CPU to interrupting after interrupting that the logic interrupt priority level is set for the present invention, and its concrete steps are:
Peripheral hardware among step 401, the ERTOS triggers to CPU and interrupts.
Have no progeny during step 402, CPU receive, close the PIC global interrupt, IMR is configured, the logic interrupt priority level is received interruption mask bit low and the interruption place interrupt source correspondence that equals than institute carry out set according to the receive PIC configuration item that interrupts.
After according to the PIC configuration item of the interruption of the current execution of CPU the mask bit of IMR being set according to Fig. 3 and the described method of Fig. 4, when being triggered than the high interruption of the current execution interrupt logic of CPU interrupt priority level, CPU inquiry IMR is triggered and interrupts the mask bit of place interrupt source correspondence, obtaining this mask bit is not set, then CPU responds the interruption that is triggered, stop to carry out the interruption of current execution, interrupt operating to being triggered, carry out the interruption that is triggered according to Fig. 3 or the described step of Fig. 4.When being triggered than the interruption low or that equal of the current execution interrupt logic of CPU interrupt priority level, the CPU inquiry is triggered and interrupts the mask bit of place interrupt source correspondence, obtaining this mask bit is set, then CPU does not respond the interruption that is triggered, continue to execute current execution in have no progeny, interrupt operating to being triggered according to Fig. 3 or the described step of Fig. 4 again, carry out the interruption that is triggered.
Because the CPU among the ERTOS can carry out two class methods: task and the corresponding ISR that interrupts.So the present invention not only can be provided with the logic interrupt priority level at the ISR that interrupts correspondence, and the PIC configuration item can also be set in task.Like this, when the CPU among the ERTOS executed the task, also the PIC configuration item according to task disposed IMR, thereby when task is carried out, some interruptions is not responded by CPU.
But the PIC configuration item of task is different fully with the application target of the PIC configuration item of ISR.The PIC configuration item of task does not embody the logic interrupt priority level, but autotelicly shields some interruption.For example: task A is a fault processing task that starts when the ERTOS mistake takes place, only allow to handle an exterior interrupt in task A operational process: clock interrupts, other all interruptions all must shield, this is because ERTOS this moment makes a mistake, can not do any processing, but need regularly for fault processing itself, interrupt so CPU can respond clock.The present invention can achieve the above object by set in advance the method for PIC configuration item in task.In most of the cases, the logic interrupt priority level of set task is minimum, and when the ERTOS initialization, the corresponding PIC configuration item of calculation task also can respond all interruptions.
Below lift specific embodiment explanation the present invention and how to realize the logic interrupt priority level of the setting of the PIC configuration item of task and interruption.
Suppose to have task TASK-A, interrupt A and interrupt B, the ISR that interrupts the A correspondence is ISRA, and the ISR that interrupts the B correspondence is ISRB, and the PIC configuration item that TASK-A is provided with is not for shielding interrupt source of interrupting the A place and the interrupt source of interrupting the B place.
The logic interrupt priority level of supposing the ISRA setting is less than or equal to the logic interrupt priority level that ISRB is provided with, and the current TASK-A that carrying out of hypothesis CPU, after interruption A is triggered earlier, interrupts B and is triggered.Fig. 5 is being the process flow diagram of first kind CPU after interrupting that the logic interrupt priority level is set to the operation embodiment one of interruption for the present invention, and its concrete steps are:
Step 500, the current TASK-A that carrying out of CPU, the mask bit of IMR has carried out set according to the PIC configuration item that is provided with by TASK-A.
Step 501, interruption A are triggered, and CPU receives and interrupts A.
Step 502, CPU inquiry IMR are triggered and interrupt the mask bit of A place interrupt source correspondence, determine the not set of this mask bit.
Step 503, CPU stop to carry out the current TASK-A that is carrying out, and A is interrupted in response, according to the step 302 among Fig. 3～step 305, carry out the ISRA that interrupts the A correspondence.
Step 504, interruption B are triggered, and CPU receives and interrupts B.
Step 505, CPU inquiry IMR are triggered and interrupt the mask bit of the affiliated interrupt source correspondence of B, determine the not set of this mask bit, and this is to be higher than the logic interrupt priority level that interrupts A owing to interrupt the logic interrupt priority level of B.
Step 506, CPU stop to carry out the ISRA of the current interruption A correspondence of carrying out, and B is interrupted in response, according to the step 302 among Fig. 3～305, carry out the ISRB that interrupts the B correspondence.
After step 507, CPU executed the ISRB that interrupts the B correspondence, A was interrupted in response again, according to the step 302 among Fig. 3～step 305, carried out the ISRA that interrupts the A correspondence.
Step 508, CPU respond TASK-A after executing the ISRA that interrupts the A correspondence again, according to the step 302 among Fig. 3～step 305, carry out TASK-A.
When the present invention uses the second class CPU that interruption is operated after for task the logic interrupt priority level being set, the described execution according to the step 302 among Fig. 3～step 305 of step 503, step 506, step 507 and the step 508 of Fig. 5 can be replaced with according to the step 402 among Fig. 4～step 403 execution.
Suppose that the logic interrupt priority level that ISRA is provided with is higher than the logic interrupt priority level that ISRB is provided with, and the current TASK-A that carrying out of hypothesis CPU, after interruption A is triggered earlier, interrupts B and be triggered again.Fig. 6 is being the process flow diagram of first kind CPU after interrupting that the logic interrupt priority level is set to the operation embodiment two of interruption for the present invention, and its concrete steps are:
When after the present invention is being to interrupt the logic interrupt priority level is set, using the second class CPU that interruption is operated, the described execution according to the step 302 among Fig. 3～step 305 of step 503, step 607 and the step 608 of Fig. 6 can be replaced with according to the step 402 among Fig. 4～step 403 execution.
The present invention is for first kind CPU, can distinguish the interrupt priority level that interrupts on littler granularity, being used to of setting the logic interrupt priority level progression of distinguishing interrupt priority level can equal the number of the interrupt source that PIC provides at most; For the second class CPU, the present invention can realize interrupt nesting.The interruption that the logic interrupt priority level is low can be interrupted by the high interruption of logic interrupt priority level, and similarly, the progression of the logic interrupt priority level of setting at most also can equal the number of interrupt source.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being made within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1, in embedded real-time operating system ERTOS, realizes the method for logic interrupt priority level, it is characterized in that, the logic interrupt priority level of this interruption is set among the interrupt service routine ISR of the interruption correspondence in ERTOS, the number of interrupt source under set logic interrupt priority level progression equals to interrupt at the most, this method also comprises:
A, ERTOS initialization, according to relativeness between the logic interrupt priority level of all ISR settings among the ERTOS and the corresponding mask bit that interrupts affiliated interrupt source in interrupt mask register IMR correspondence of all ISR, calculate the programmable interrupt controller PIC configuration item of interruption;
B, CPU receive that peripheral hardware triggered among the ERTOS in have no progeny, after according to the PIC configuration item that interrupts each mask bit of IMR being provided with, carry out this interruption.
2, the method for claim 1 is characterized in that, when the interruption that is higher than the performed interruption of described step b when the logic interrupt priority level was triggered, this method also comprised:
C1, CPU receive peripheral hardware and are higher than the interruption of the performed interruption of step b by the logic interrupt priority level that interrupt source triggered, and the interruption that is triggered according to definite this interrupt source of the mask bit value of setting among the corresponding IMR of this interrupt source can be responded, and responds this interruption;
After d1, CPU are higher than the interruption of the performed interruption of step b according to the logic interrupt priority level PIC configuration item is reset each mask bit of IMR, carry out this interruption.
3, the method for claim 1 is characterized in that, is less than or equal to described step b when carrying out the interruption of interrupting and being triggered when the logic interrupt priority level, and this method also comprises:
C2, CPU receive peripheral hardware is less than or equal to the performed interruption of step b by the logic interrupt priority level that interrupt source triggered interruption, determine that according to the mask bit value of setting among the corresponding IMR of this interrupt source the interruption that this interrupt source is triggered can not be responded, have no progeny in the continuation execution of step b execution, the response logic interrupt priority level is less than or equal to the interruption of the performed interruption of step b again;
After d2, CPU are less than or equal to the interruption of the performed interruption of step b according to the logic interrupt priority level PIC configuration item is reset each mask bit of IMR, carry out this interruption.
As claim 1,2 or 3 described methods, it is characterized in that 4, before each mask bit to IMR was provided with, this method also comprises: CPU closed the PIC global interrupt earlier, current logic interrupt priority level is set to minimum;
Before step b carried out this interruption, this method also comprised: CPU opens the PIC global interrupt.
As claim 1,2 or 3 described methods, it is characterized in that 5, before each mask bit to IMR was provided with, this method also comprises: CPU closed the PIC global interrupt earlier;
Before step b carried out this interruption, this method also comprised: CPU opens the PIC global interrupt.
6, the method for claim 1 is characterized in that, for the task among the ERTOS is provided with the PIC configuration item, before step b, this method also comprises:
B1, CPU execute the task, and are provided with according to the PIC configuration item of task setting each mask bit to IMR;
Had no progeny during peripheral hardware triggers in the described ERTOS of receiving of step b, also comprised:
B2, CPU determine according to the mask bit value of setting among the corresponding IMR of interrupt source that is triggered under interrupting whether this interruption can be responded, if, the subsequent process of execution in step b; Otherwise, continue after the task of executing the subsequent process of execution in step b again.
As claim 1 or 6 described methods, it is characterized in that 7, described PIC configuration item is the Configuration Values corresponding to each mask bit of IMR, each mask bit of this IMR and interruption are corresponding one by one.
8, method as claimed in claim 7 is characterized in that, when interrupting being responded, and the not set of mask bit in the described PIC configuration item corresponding to the IMR of interrupt source under this interruption; When interrupting being responded, the mask bit set in the described PIC configuration item corresponding to the IMR of interrupt source under this interruption.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102932599A (en) * | 2012-11-09 | 2013-02-13 | 北京百纳威尔科技有限公司 | Device and method to achieve camera function based on general purpose input/output (GPIO) stimulated data bus |
| CN101964681B (en) * | 2009-07-22 | 2013-08-21 | 中兴通讯股份有限公司 | Device and method for detecting alarm by interruption |
| CN113419450A (en) * | 2021-06-29 | 2021-09-21 | 北京猎户星空科技有限公司 | Motor FOC control and operation method, device, electronic equipment and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| FR2680591B1 (en) * | 1991-08-22 | 1996-01-26 | Telemecanique | PROGRAMMABLE INTERRUPTION CONTROLLER, INTERRUPTIVE SYSTEM, AND INTERRUPTION CONTROL METHOD. |
| JP3556465B2 (en) * | 1998-04-21 | 2004-08-18 | 株式会社ルネサステクノロジ | Interrupt controller |
| US6807595B2 (en) * | 2001-05-10 | 2004-10-19 | Qualcomm Incorporated | Mobile communication device having a prioritized interrupt controller |
| JP2004355111A (en) * | 2003-05-27 | 2004-12-16 | Matsushita Electric Ind Co Ltd | Interruption controller and interruption control method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964681B (en) * | 2009-07-22 | 2013-08-21 | 中兴通讯股份有限公司 | Device and method for detecting alarm by interruption |
| CN102932599A (en) * | 2012-11-09 | 2013-02-13 | 北京百纳威尔科技有限公司 | Device and method to achieve camera function based on general purpose input/output (GPIO) stimulated data bus |
| CN113419450A (en) * | 2021-06-29 | 2021-09-21 | 北京猎户星空科技有限公司 | Motor FOC control and operation method, device, electronic equipment and medium |
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