CN1523664A - 封装基板和倒装型半导体器件 - Google Patents
封装基板和倒装型半导体器件 Download PDFInfo
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- CN1523664A CN1523664A CNA200410004428XA CN200410004428A CN1523664A CN 1523664 A CN1523664 A CN 1523664A CN A200410004428X A CNA200410004428X A CN A200410004428XA CN 200410004428 A CN200410004428 A CN 200410004428A CN 1523664 A CN1523664 A CN 1523664A
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Abstract
本发明提供提高了封装后的成品率的封装基板和倒装型半导体器件。以倒装方式连接了以低热膨胀的金属为核心并在其两面上层叠了叠加布线层的封装基板9与半导体芯片1,在金属核心中形成了多个贯通孔或狭缝。尽管对于在封装基板9的表面上形成的与安装基板6的连接端子来说,在金属核心与安装基板6之间存在热膨胀率的差别,但利用在金属核心中形成了的多个贯通孔或狭缝减少了其约束力。此外,另一方面,由于金属核心是低热膨胀的,故与半导体芯片1之间的热膨胀率差小,对倒装连接凸点3或半导体芯片1表面施加的压力也非常小。此外,本发明提供以低热膨胀的金属为核心并在其两面上层叠了叠加布线层的封装基板9。
Description
技术领域
本发明涉及半导体封装体,特别是涉及封装基板和倒装型半导体器件。
背景技术
现有的倒装型半导体封装体具有如图14和图15中所示的剖面结构,由下述部分构成:安装基板6;在安装基板6上经BGA球(焊料球)5连接的封装基板2;经倒装连接凸点3与封装基板2连接的半导体芯片1;以及保护半导体芯片1与倒装连接凸点3之间的底层填料树脂4。图14是在封装基板2的上部表面上具有连接了半导体芯片1的结构的例子,另一方面,图15是在封装基板2的背面上具有连接了半导体芯片1的结构的例子。此外,在图14和图15中示意性地示出了封装基板2和安装基板6的内部结构,而不是示出准确的结构。关于封装基板2,在图18中示出其详细的结构。关于安装基板,例如使用包含通常使用的玻璃环氧树脂的基板。
以往,对于倒装型半导体封装体来说,使用了陶瓷基板或树脂基板作为安装半导体芯片1的布线用的封装基板2。半导体芯片1经由焊料构成的倒装连接凸点3被连接到封装基板2上,被充填了保护该连接部用的被称为底层填料树脂4的热硬化性树脂。在封装基板2的表面上形成了取得与安装基板6的导电性的连接用的外部连接电极,经作为在该外部连接电极上安装的焊料球的BGA球5取得与安装基板6之间的连接。在倒装型半导体封装体中,其特征在于:倒装连接部和BGA连接部的任一连接部都被异种材料夹持。即,一般来说,倒装连接部被由硅构成的半导体芯片1和由陶瓷或树脂构成的封装基板2夹持。另一方面,BGA连接部被封装基板2和一般来说由FR-4等的纤维强化树脂构成的安装基板6夹持。
通常使用氧化铝于陶瓷制的封装基板2。因为氧化铝的热膨胀率为5.5ppm/℃,硅的热膨胀率为3ppm/℃,故成为与作为半导体芯片1的主要构成材料的硅极为接近的值。另一方面,在树脂制的封装基板2的情况下,一般使用以BT树脂为基体层叠了环氧树脂的叠加基板。在此,BT的热膨胀率为17ppm/℃,其特征是,该值与硅的相应的值的偏离较大。因此,关于倒装连接部,对于树脂基板的一方来说处于容易施加应力的状态。实际上,对于其温度循环试验中的寿命来说,如果比较在-65℃/125℃的温度循环下达到50%的不良发生的循环数,则在陶瓷基板的情况下为1900循环,而在树脂基板的情况下为1000循环,大体减少了一半。
再者,该热膨胀率的差引起半导体芯片1和封装基板2的翘曲。在将18×18mm的半导体芯片1以倒装方式连接到50×50mm的封装基板2上的情况下,在陶瓷基板的情况下,在芯片安装部中其翘曲为不到10μm、在整个封装体中其翘曲为50μm,是非常小的值。与此不同,在树脂基板的情况下,在芯片安装部中其翘曲为100μm、在整个封装体中其翘曲为270μm,是非常大的值。从图14和图15中示出的示意性的剖面结构可明白,整个封装体的翘曲成为使BGA球5的连接端子的平坦性恶化的主要原因。通常要求倒装型半导体封装体的BGA球5的连接端子的平坦性为200μm以下。因而,在上述的树脂基板的情况下,成为难以满足200μm以下的平坦性的要求的状态。
对在图14中示出的现有的倒装型半导体封装体进行散热用的安装结构,如图16和图17中所示,具有在半导体芯片1上经热传导树脂7安装的热沉8。此外,在图16和图17中,示意性地示出了封装基板2和安装基板6的内部结构,而不是示出准确的结构。关于封装基板2,在图18中示出其详细的结构。关于安装基板,例如使用包含通常使用的玻璃环氧树脂的基板。图17是在图16中半导体芯片1的附近部分的放大图,示出了安装基板6、在安装基板6上经BGA球5连接的封装基板2、在封装基板2上经倒装连接凸点3连接的半导体芯片1、保护倒装连接凸点3部分的底层填料树脂4和在半导体芯片1上经热传导树脂7连接的热沉8。通常在倒装型半导体封装体的情况下,从半导体芯片1的背面起经热传导树脂7朝向热沉8等的冷却***散热。关于热传导树脂7,通常使用将环氧或硅酮树脂作为粘合剂并充填金属粉的树脂,但其热传导率约为1W/m/k,如果与由硅构成的半导体芯片1的热传导率150W/m/k、由铝构成的热沉的情况的热传导率200W/m/k或由铜构成的热沉的情况的热传导率390W/m/k相比,则其热传导性较差。因而,为了实现高散热化,重要的是尽可能减薄热传导树脂7的厚度。但是,在使用了树脂基板的倒装型半导体封装体中,由于半导体芯片1翘曲了100μm,故厚度必然不能为100μm以下。如果将其转换为热阻,则相当于增加0.3℃/W,例如,在40W的大规模LSI中,晶体管的温度就上升12℃,成为极为严重的问题。
图14至图17中示出的现有的封装基板2,如图18的剖面放大图中所示,由下述部分构成:树脂基板18;在树脂基板18开了口的通路孔12;微细金属布线13;微通路孔14;以及在封装基板2的表面背面上形成的焊料抗蚀剂15。在封装基板2的两面上层叠了以叠加树脂作为层间绝缘膜17的布线层。对于通路孔12来说,充填了玻璃环氧等的绝缘性的树脂。
已确认了现有的倒装型半导体封装体的成品率下降主要是因半导体芯片1和封装基板2的热膨胀差引起的破坏所致。
【专利文献1】
特开2002-332544号公报
【专利文献2】
特开2002-353584号公报
【专利文献3】
特开2002-223070号公报
如以上已说明的那样,在使用了倒装连接部中引起了热膨胀的失配的树脂基板的倒装型半导体封装体中,存在下述问题:(a)倒装连接部的可靠性是不充分的,(b)BGA球5的连接端子的平坦性差,(c)散热性是不充分的,(d)难以使用低介电常数的层间绝缘膜作为半导体芯片1的多层布线等。
另一方面,在BGA球5的连接一侧,陶瓷基板与树脂基板相比压倒性地处于不利状态。在安装基板6中使用的FR-4的热膨胀率为17ppm/℃,而陶瓷基板的氧化铝的热膨胀率为5.5ppm/℃(偏离11.5ppm/℃)、树脂基板的BT的热膨胀率为15ppm/℃(偏离2ppm/℃)。因此,例如对32×25mm的封装体进行-65℃/125℃的温度循环试验的情况下,在陶瓷基板中,在500循环中达到50%的不良,而在树脂基板中寿命达到1000循环以上。如果封装体尺寸变大,则所积累的位移量成比例地增加,因此,陶瓷基板的寿命进一步缩短。因而,在陶瓷基板的情况下,存在封装体尺寸的使用范围受到限制的大的问题。
发明内容
本发明的目的在于提供由于与半导体芯片之间的热膨胀率差小、对倒装连接凸点或半导体芯片表面施加的应力小而提高了封装后的成品率的封装基板和倒装型半导体器件。
为了实现上述目的,本发明的第1特征的要旨是一种封装基板,其特征在于,具备:(一)具有多个贯通孔的低热膨胀率基板;(二)在低热膨胀率基板的两面上以层叠方式形成的树脂绝缘层;(三)进而在低热膨胀率基板的两面中并在树脂绝缘层上以层叠方式形成的叠加布线层;以及(四)在低热膨胀率基板上形成的半导体芯片安装区,在从低热膨胀率基板的中心起用直线连结了外周上的任意的点时,在该直线上的低热膨胀率基板上必定存在贯通孔。
本发明的第2特征的要旨是一种倒装型半导体器件,其特征在于,具备:(一)在半导体元件形成面上形成了连接端子的半导体芯片;(二)封装基板,具有有多个贯通孔的低热膨胀率基板、在低热膨胀率基板的两面上被层叠了的树脂绝缘层和进而在低热膨胀率基板的两面中并在上述树脂绝缘层上以层叠方式形成的叠加布线层,以倒装方式连接有半导体芯片;(三)倒装连接凸点,以倒装方式连接半导体芯片与封装基板之间;以及(四)底层填料树脂,密封以倒装方式连接了的封装基板与半导体芯片之间的间隙,在从封装基板的中心起用直线连结了外周上的任意的点时,在该直线上的低热膨胀率基板上必定存在贯通孔。
附图说明
图1是与本发明的第1实施例有关的倒装型半导体封装体的示意性的剖面结构图。
图2是与本发明的第1实施例有关的倒装型半导体封装体的示意性的剖面结构图。
图3是示出在与本发明的第1实施例有关的倒装型半导体封装体中使用的封装基板的详细结构的示意性的剖面结构图。
图4是示出在图3中连接了BGA球的封装基板的详细结构的示意性的剖面结构图。
图5是示出在图3中连接了倒装连接凸点的封装基板的详细结构的示意性的剖面结构图。
图6是示出在与本发明的第2实施例有关的倒装型半导体器件的封装基板中使用的金属板核心的贯通孔形成图形的上方透视图。
图7是示出在与本发明的第2实施例有关的倒装型半导体器件的封装基板中使用的金属板核心的贯通孔形成图形的上方透视图。
图8是示出在对图6中使用的金属板核心施加压缩应力时的变形状态的示意图。
图9是示出在对图7中使用的金属板核心施加压缩应力时的变形状态的示意图。
图10是示出在与本发明的第3实施例有关的倒装型半导体器件的封装基板中使用的金属板核心的贯通孔形成图形的上方透视图。
图11是示出在与本发明的第3实施例有关的倒装型半导体器件的封装基板中使用的金属板核心的贯通孔形成图形的上方透视图。
图12是示出在与本发明的第3实施例的变形例有关的倒装型半导体器件的封装基板中使用的金属板核心的贯通孔形成图形的上方透视图。
图13是示出在与本发明的第4实施例有关的封装基板上利用引线键合安装了半导体芯片的状况的示意性的剖面结构图。
图14是示出现有的倒装型半导体封装体的剖面结构图。
图15是示出现有的倒装型半导体封装体的剖面结构图。
图16是示出在图14示出的现有的半导体封装体上安装冷却***的方法的剖面结构图。
图17是在图16中半导体封装体部分的放大图。
图18是示出在现有的倒装型半导体封装体中使用的封装基板的详细结构的示意性的剖面结构图。
图19是示出半导体芯片多层布线的层间绝缘膜的介电常数与强度和封装成品率的关系的图。
图20是示出封装基板的热膨胀率与封装成品率的关系的图。
具体实施方式
其次,参照附图说明本发明的实施例。在以下的图面中,对同一或类似的部分附以同一或类似的符号。此外,以下示出的实施例例示使本发明的技术思想具体化用的装置或方法,而不是将本发明的技术思想指定为下述的实施例。在技术方案的范围内,本发明的技术思想可增加各种变更。
在与本发明的实施例有关的封装基板中,使用以低热膨胀率的材料为核心的低热膨胀率基板,具有在其两面上层叠了叠加布线层的结构。低热膨胀率基板,只要是低热膨胀率的材料,金属板也好、陶瓷板也好、玻璃板也好,都是可以的。在以下的说明中,作为低热膨胀率基板,代表性地以金属板的情况为例来说明。在与本发明的实施例有关的倒装型半导体器件中,倒装连接了例如以金属为核心并在在其两面上层叠了叠加布线层作为低热膨胀的材料的封装基板与半导体芯片,在金属核心中形成了多个贯通孔或狭缝。对于在封装基板的表面上形成的与安装基板的连接端子来说,尽管在金属核心与安装基板之间存在热膨胀率的差别,但利用在金属核心中形成的贯通孔或狭缝减少了其约束力。此外,另一方面,由于金属核心是低热膨胀的,故与半导体芯片之间的热膨胀率的差小,对倒装连接凸点或半导体芯片表面施加的应力也非常小。
如图19中所示,在变更了构成半导体芯片的多层布线的层间绝缘膜的相对介电常数时的因树脂基板引起的封装后的成品率结果和层间绝缘膜的相对强度在层间绝缘膜的相对介电常数为2.5与3.0之间显示出急剧的变化。实线表示层间绝缘膜的相对强度,虚线表示封装后的成品率。现在的半导体芯片由于多层布线部的高速化的缘故而趋于采用被称为Low-K的低介电常数的层间绝缘膜的方向。但是,从图19可明白,由于相对介电常数减少的缘故,层间绝缘膜的强度显著地下降,封装后的成品率也显著地下降。
如图20中所示,使用热膨胀率不同的封装基板2对采用相对介电常数为2.7的Low-K的层间绝缘膜构成的半导体芯片1进行封装密封时的成品率结果在封装基板的热膨胀率为6ppm/℃与10ppm/℃之间显示出急剧的变化。从图20可明白,封装基板的热膨胀率越低,成品率越良好。即,因为成品率随热膨胀率降低而改善,故可确认现有的倒装型半导体封装体的成品率下降是由于因半导体芯片与封装基板的热膨胀差引起的破坏所致。
(第1实施例)
与本发明的第1实施例有关的倒装型半导体器件,如图1和图2中示出其示意性的剖面结构那样,由下述部分构成:封装基板9;经倒装连接凸点3和封装基板9连接的半导体芯片1;保护封装基板9与半导体芯片1的连接部的底层填料树脂4;以及在封装基板9的表面或背面上形成的BGA球5。此外,在图1和图2中,示意性地示出了封装基板9的内部结构,而不是示出准确的结构。在图3中示出封装基板9的详细的结构。
图1和图2中示出的倒装型半导体器件中使用的与本发明的第1实施例有关的封装基板9,如图3中示出其剖面放大图那样,由下述部分构成:金属板核心10;在金属板核心10中开了口的贯通孔11;在贯通孔11的内侧形成的通路孔12;微细金属布线13;微通路孔14;以及在封装基板9的表面背面上形成的焊料抗蚀剂15。封装基板9以金属板核心10为核心,在其两面上层叠了由以叠加树脂为层间绝缘膜17的微细金属布线13构成的布线层。在金属板核心10中开出了多个贯通孔11,在其一部分中形成了贯通其内部的通路孔12,对由微细金属布线13构成的上下叠加布线层进行了连线。使用低热膨胀金属、例如铁镍合金或因瓦合金等作为金属板核心10。此外,即使对于贯通孔11和通路孔12来说,也在制造工序中充填了玻璃环氧等的绝缘性的树脂。
关于图1和图2中示出的封装基板9与BGA球5的连接的细节,例如,如图4中所示,通过图形化对焊料抗蚀剂15开出窗口,在利用金属蒸镀等形成了外部连接电极后,在该外部连接电极上通过使BGA球5接触来进行。同样,关于图1和图2中示出的封装基板9与倒装连接凸点3的连接的细节,例如,如图5中所示,通过图形化对焊料抗蚀剂15开出窗口,在利用金属蒸镀等形成了外部连接电极后,在该外部连接电极上通过使倒装连接凸点3接触来进行。
如在图6和图7中示出其上方透视图那样,在形成与本发明的第1实施例有关的封装基板和倒装型半导体器件中使用的金属板核心10的金属板上形成了多个贯通孔11,利用弯曲的线来连系其间。在图6的例子中,贯通孔11的形状为矩形形状,而在图7的例子中,贯通孔11具有正六角形的形状。在贯通孔11的配置中,在用直线连结封装基板9的中心与外周的任意的点时,在其直线上必定存在贯通孔11。这是为了在因封装基板9与安装基板6的热膨胀差引起的位移发生的方向上通过不连续地配置刚性且平直的金属板核心10来赋予柔性。
如果在图6和图7中示出的形状的金属板核心10用箭头示出的方向上将位移量进行夸张而示意性地示出进行压缩位移的状况,则分别如图8和图9中所示,通过对于位移方向不连续地存在金属板核心10,可确认构成为柔性的结构的状况。此外,在其中图9中示出的贯通孔11具有正六角形的形状这一点,在对于所有的方位成为柔性的结构这方面来说,是最为理想的。
(第2实施例)
如在图10中示出其上方透视图那样,在与本发明的第2实施例有关的封装基板和倒装型半导体器件中,对于金属板核心10来说,将贯通孔11形成为正六角形的六角密集充填配置,而且,使朝向半导体芯片安装区16的贯通孔11的形成为最小限度,在半导体芯片安装区16的部分上维持了刚直且低热膨胀的特性。其结果,大幅度地减少了因半导体芯片1与封装基板9之间的热膨胀差引起的翘曲。例如,在将18×18mm的半导体芯片1安装在50×50mm的封装基板9上的情况下,在使用了现有的树脂基板的情况下,如上所述,产生在芯片安装部中其翘曲为100μm、在整个封装体中其翘曲为270μm这样的大的翘曲,而如果使用与本发明的第2实施例有关的倒装型半导体器件的封装基板9,则在芯片安装部中其翘曲为不到10μm、即使在整个封装体中其翘曲也为80μm,其翘曲是极小的,可确认得到了很大的改善。再者,可得到以倒装方式连接形成了相对介电常数为2.7的Low-K膜的半导体芯片1时的100%的封装体组装后的成品率。
此外,另一方面,在该半导体芯片非安装区中,由于形成了更多的贯通孔11,故与图7中示出的与本发明的第1实施例有关的封装基板同样,维持了作为封装基板9整体的柔性。一般来说,倒装型半导体封装体中的半导体芯片安装位置为封装体中心附近。此外,离封装体中心越远,因与安装基板6的热膨胀差引起的对作为外部连接电极的BGA球5的应力越大,这是众所周知的事实。因而,在与本发明的第2实施例有关的倒装型半导体器件中,在有选择地使对作为外部连接端子的BGA球5施加最大的应力的部分变得呈柔性这一点上成为非常理想的结构。
(第3实施例)
如在图11中示出其上方透视图那样,在与本发明的第3实施例有关的封装基板和倒装型半导体器件中,其特征在于:避开从半导体芯片1的中心起以放射状扩展的多条直线形成半导体芯片安装区16中的金属板核心10的贯通孔11的配置。作为一例,在图11中,从半导体芯片1的中心起以30°间隔将12条的放射状的直线作为非贯通部留下。因半导体芯片1与封装基板9的热膨胀差引起的不良情况、即对倒装连接部的应力或半导体芯片安装区16的翘曲等都是由于从被安装在半导体芯片安装区16上的半导体芯片1的中心起以放射状扩展的位移而引起的。因而,通过在该方向上形成连续的金属板核心10,封装基板9成为刚性且平直且低热膨胀的基板。关于另一方的半导体芯片非安装区,与本发明的第1及第2实施例有关的封装基板和倒装型半导体器件同样,由于未形成在从半导体芯片1的中心起以放射状延伸的方向上连续的金属板核心10,故成为具有柔性的结构。因而,可减少因封装基板9与安装基板6的热膨胀差引起的对作为外部连接端子的BGA球5的应力。
此外,在与本发明的第3实施例有关的封装基板和倒装型半导体器件中,不规定金属板核心10的贯通区域对非贯通区域的面积比。因而,与本发明的第2实施例有关的封装基板和倒装型半导体器件同样,可使半导体芯片安装区16的贯通面积比比非安装区域的贯通面积比小,或者也可使半导体芯片安装区16的贯通面积比与非安装区域的贯通面积比相同。在后者的情况下,由于对金属板核心10的树脂充填时所必要的树脂量在封装基板9上的整个面上是均匀的,故使树脂的供给变得容易,此外,在贯通孔11的充填的同时在表面背面上一并地形成绝缘层的情况下,具有可使绝缘层的厚度为恒定的优点。
(第3实施例的变形例)
作为本发明的实施例,使用安装了1个半导体芯片1的封装体进行了说明,但当然即使是安装了多个半导体芯片1的情况,也能得到完全同样的效果。在图12中示出在封装基板9上具有2个部位的半导体芯片安装区16的例子。如图12中所示,通过在封装基板9的中心部分中配置多个半导体芯片安装区16,能以高的成品率来安装多个半导体芯片1。与第2实施例同样,大幅度地减少了因半导体芯片1与封装基板9之间的热膨胀差引起的翘曲。此外,另一方面,在半导体芯片非安装区中,由于形成了更多的贯通孔11,故与在图10中示出的与本发明的第2实施例有关的封装基板同样,维持了作为封装基板9整体的柔性。此外,在上述变形例中示出了在2个部位上设置半导体芯片安装区16的例子,但也可设定更多个部位。或者,也可在封装基板9的中心部分中归纳起来作为共同区域来设定。
(第4实施例)
作为本发明的实施例,使用倒装型半导体封装体进行了说明,但即使在不是倒装型的半导体封装体中,当然在缓和对BGA球施加的应力这一点上也能得到同样的效果。具体地说,即使是具有在封装基板9上以面朝上的方式安装半导体芯片1、用引线键合连接了半导体芯片1与封装基板9那样的结构的封装体也没有关系。例如,如图13中所示,与本发明的第4实施例有关的封装基板9由下述部分构成:在封装基板9上形成的外部连接电极30和33;外部连接电极30上的半导体芯片1;底层填料树脂4;以及键合引线32。可利用键合引线32对在半导体芯片1上形成的键合焊区与在封装基板9上形成的外部连接电极33之间进行连线。通过例如采用图11中示出的结构作为封装基板9的结构,在半导体芯片安装区16上配置半导体芯片1。在半导体芯片1的周边部中,在封装基板9上形成外部连接电极33,如上所述那样使用键合引线32来结合于半导体芯片上形成的键合焊区之间。在与本发明的第4实施例有关的封装基板9中,示出了利用引线键合来连接半导体芯片1的例子,但因为抑制了封装基板9本身的热膨胀,故抑制了对半导体芯片1或引线键合的连接部施加的应力,可提供成品率良好的封装基板9。此外,在图13中,示意性地示出了封装基板9的内部结构,而不是示出准确的结构。在图3中示出封装基板9的详细的结构,这一点与第1实施例是同样的。
按照与本发明的第1至第3实施例有关的封装基板和倒装型半导体器件,既能减少半导体芯片1与封装基板9之间的热膨胀率差,又能降低对封装基板9与安装基板6之间的连接端子施加的应力。其结果,可同时实现以下的显著的特征。延长了在温度循环应力中达到倒装连接凸点3的断裂为止的寿命。延长了在温度循环应力中达到在半导体芯片1与封装基板9之间充填的底层填料树脂4的剥离、裂纹的发生为止的寿命。即使在使用了在半导体元件的形成面上具备脆弱的层间绝缘膜的半导体芯片1的情况下,也能提供高的封装成品率,延长了在温度循环应力中达到层间绝缘膜的破坏为止的寿命。延长了在温度循环应力中达到在封装基板9与安装基板6之间形成的连接端子、即BGA球5或LGA连接焊料的断裂为止的寿命。伴随封装基板9的翘曲的减少,提高了外部连接端子的平坦性。伴随半导体芯片1的翘曲的减少,可实现充填与冷却部件、即盖或热沉8之间的高散热的热传导树脂7的薄膜化,减少了热阻。
此外,在与本发明的第1至第3实施例有关的封装基板和倒装型半导体器件中,使用低热膨胀的金属板作为封装基板9的金属板核心10进行了说明,但这只是考虑了加工性以可实现性最高的材料为代表例进行了记载,当然即使是陶瓷或玻璃也能达到同样的效果。总之,只要是低热膨胀且刚性且平直的材料即可。
按照与本发明的封装基板和倒装型半导体器件,既能减少半导体芯片与封装基板之间的热膨胀率差,又能降低对封装基板与安装基板之间的连接端子施加的应力。
Claims (19)
1.一种封装基板,其特征在于:
具备:
具有多个贯通孔的低热膨胀率基板;
在上述低热膨胀率基板的两面上以层叠方式形成的树脂绝缘层;
进而在上述低热膨胀率基板的两面中并在上述树脂绝缘层上以层叠方式形成的叠加布线层;以及
在上述低热膨胀率基板上形成的半导体芯片安装区,
在从上述低热膨胀率基板的中心起用直线连结了外周上的任意的点时,在该直线上的上述低热膨胀率基板上必定存在上述贯通孔。
2.如权利要求1中所述的封装基板,其特征在于:
上述低热膨胀率基板的热膨胀率为10ppm/℃或10ppm/℃以下。
3.如权利要求1中所述的封装基板,其特征在于:
在上述低热膨胀率基板上形成了以上述封装基板的中心为中心的同轴的多角形或圆状的狭缝,以上述低热膨胀率基板的非开口部桥连的方式连系了各自的上述狭缝间,该桥连的配置不在从内周朝向外周的同一直线上。
4.如权利要求1中所述的封装基板,其特征在于:
在上述低热膨胀率基板上形成了以正三角形为基本单位的六角密集充填配置的贯通孔。
5.如权利要求4中所述的封装基板,其特征在于:
在上述低热膨胀率基板上形成的六角密集充填配置的贯通孔是六边形。
6.如权利要求1中所述的封装基板,其特征在于:
上述低热膨胀率基板的上述半导体芯片安装区中的贯通部的面积对于非贯通部的面积的比率比该半导体芯片非安装区中的贯通部的面积对于非贯通部的面积的比率小。
7.如权利要求1中所述的封装基板,其特征在于:
避开了连结上述半导体芯片安装区的中心与上述半导体芯片安装区的外周的多条直线形成了上述低热膨胀率基板的上述半导体芯片安装区中形成的贯通孔。
8.如权利要求1中所述的封装基板,其特征在于:
上述封装基板还具备在上述封装基板的半导体芯片安装面和半导体芯片非安装面的某一方上形成的外部连接电极,在上述外部连接电极中经焊料球连接到安装基板上。
9.如权利要求1中所述的封装基板,其特征在于:
存在多个上述封装基板上的上述半导体芯片安装区。
10.如权利要求1中所述的封装基板,其特征在于:
利用引线键合来连接上述封装基板上的上述半导体芯片安装区上被安装了的半导体芯片。
11.一种倒装型半导体器件,其特征在于:
具备:
在半导体元件形成面上形成了连接端子的半导体芯片;
封装基板,其具有有多个贯通孔的低热膨胀率基板、在上述低热膨胀率基板的两面上被层叠了的树脂绝缘层和进而在上述低热膨胀率基板的两面中并在上述树脂绝缘层上以层叠方式形成的叠加布线层,以倒装方式连接有上述半导体芯片;
倒装连接凸点,其以倒装方式连接着上述半导体芯片与上述封装基板之间;以及
底层填料树脂,其密封着上述以倒装方式连接了的上述封装基板与上述半导体芯片之间的间隙,
在从上述封装基板的中心起用直线连结了外周上的任意的点时,在该直线上的上述低热膨胀率基板上必定存在上述贯通孔。
12.如权利要求11中所述的倒装型半导体器件,其特征在于:
上述低热膨胀率基板的热膨胀率为10ppm/℃或10ppm/℃以下。
13.如权利要求11中所述的倒装型半导体器件,其特征在于:
在上述低热膨胀率基板上形成了以上述封装基板的中心为中心的同轴的多角形或圆状的狭缝,以上述低热膨胀率基板的非开口部桥连的方式连系了各自的上述狭缝间,该桥连的配置不在从内周朝向外周的同一直线上。
14.如权利要求11中所述的倒装型半导体器件,其特征在于:
在上述低热膨胀率基板上形成了以正三角形为基本单位的六角密集充填配置的贯通孔。
15.如权利要求14中所述的倒装型半导体器件,其特征在于:
在上述低热膨胀率基板上形成的六角密集充填配置的贯通孔是六边形。
16.如权利要求11中所述的倒装型半导体器件,其特征在于:
上述低热膨胀率基板的上述半导体芯片安装区中的贯通部的面积对于非贯通部的面积的比率比该半导体芯片非安装区中的贯通部的面积对于非贯通部的面积的比率小。
17.如权利要求11中所述的倒装型半导体器件,其特征在于:
避开了连结上述半导体芯片安装区的中心与上述半导体芯片安装区的外周的多条直线形成了上述低热膨胀率基板的上述半导体芯片安装区中形成的贯通孔。
18.如权利要求11中所述的倒装型半导体器件,其特征在于:
上述封装基板还具备在上述封装基板的半导体芯片安装面和半导体芯片非安装面的某一方上形成的外部连接电极,在上述外部连接电极中具备连接到安装基板上的焊料球。
19.如权利要求11中所述的倒装型半导体器件,其特征在于:
存在多个上述封装基板上的上述半导体芯片安装区。
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JP045018/2003 | 2003-02-21 | ||
JP2003045018A JP2004253738A (ja) | 2003-02-21 | 2003-02-21 | パッケージ基板及びフリップチップ型半導体装置 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108336042A (zh) * | 2017-12-26 | 2018-07-27 | 上海矽润科技有限公司 | 一种三维叠层芯片SiP封装 |
CN108962764A (zh) * | 2017-05-22 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法、半导体芯片、封装方法及结构 |
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EP1713313A4 (en) * | 2004-02-04 | 2010-06-02 | Ibiden Co Ltd | MULTILAYER PRINTED BOARD |
JP4360240B2 (ja) * | 2004-03-22 | 2009-11-11 | 日立化成工業株式会社 | 半導体装置と半導体装置用多層基板 |
JP4559163B2 (ja) * | 2004-08-31 | 2010-10-06 | ルネサスエレクトロニクス株式会社 | 半導体装置用パッケージ基板およびその製造方法と半導体装置 |
JP2007230193A (ja) * | 2006-03-03 | 2007-09-13 | Canon Finetech Inc | 液体吐出ヘッド |
US7687391B2 (en) * | 2006-09-27 | 2010-03-30 | International Business Machines Corporation | Electrically optimized and structurally protected via structure for high speed signals |
JP5068060B2 (ja) * | 2006-10-30 | 2012-11-07 | 新光電気工業株式会社 | 半導体パッケージおよびその製造方法 |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8936966B2 (en) | 2012-02-08 | 2015-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods for semiconductor devices |
US8105875B1 (en) | 2010-10-14 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approach for bonding dies onto interposers |
US9029991B2 (en) * | 2010-11-16 | 2015-05-12 | Conexant Systems, Inc. | Semiconductor packages with reduced solder voiding |
JP5357239B2 (ja) * | 2011-12-05 | 2013-12-04 | 新光電気工業株式会社 | 配線基板、半導体装置、及び配線基板の製造方法 |
JP6282425B2 (ja) * | 2012-10-29 | 2018-02-21 | 新光電気工業株式会社 | 配線基板の製造方法 |
US9281269B2 (en) * | 2012-11-20 | 2016-03-08 | Texas Instruments Incorporated | Integrated circuit package and method of manufacture |
JP2015146401A (ja) * | 2014-02-04 | 2015-08-13 | 大日本印刷株式会社 | ガラスインターポーザー |
TWM555065U (zh) * | 2017-09-05 | 2018-02-01 | 恆勁科技股份有限公司 | 電子封裝件及其封裝基板 |
WO2020078752A1 (en) * | 2018-10-17 | 2020-04-23 | Lumileds Holding B.V. | Circuit assembly |
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JPH0636462B2 (ja) | 1985-08-31 | 1994-05-11 | イビデン株式会社 | 金属コアプリント配線板及びその製造方法 |
US6333857B1 (en) * | 1998-12-25 | 2001-12-25 | Ngk Spark Plug Co., Ltd. | Printing wiring board, core substrate, and method for fabricating the core substrate |
JP2001267473A (ja) * | 2000-03-17 | 2001-09-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002223070A (ja) | 2001-01-29 | 2002-08-09 | Hitachi Metals Ltd | メタルコアプリント配線板用金属板の製造方法及びメタルコアプリント配線板の製造方法 |
JP2002332544A (ja) | 2001-05-08 | 2002-11-22 | Hitachi Metals Ltd | メタルコア基板用金属板およびその製造方法およびそれを用いたメタルコア基板、ビルドアップ基板 |
JP2002353584A (ja) | 2001-05-24 | 2002-12-06 | Hitachi Ltd | 両面実装電子装置、その製造方法、及び電子機器 |
JP2003031719A (ja) | 2001-07-16 | 2003-01-31 | Shinko Electric Ind Co Ltd | 半導体パッケージ及びその製造方法並びに半導体装置 |
-
2003
- 2003-02-21 JP JP2003045018A patent/JP2004253738A/ja not_active Abandoned
-
2004
- 2004-01-14 US US10/756,507 patent/US7042083B2/en not_active Expired - Fee Related
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CN108962764A (zh) * | 2017-05-22 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法、半导体芯片、封装方法及结构 |
US11335648B2 (en) | 2017-05-22 | 2022-05-17 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor chip fabrication and packaging methods thereof |
CN108336042A (zh) * | 2017-12-26 | 2018-07-27 | 上海矽润科技有限公司 | 一种三维叠层芯片SiP封装 |
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US20040207094A1 (en) | 2004-10-21 |
US7042083B2 (en) | 2006-05-09 |
JP2004253738A (ja) | 2004-09-09 |
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