CN1405849A - 应用于约束等离子体反应室的半导体双镶嵌蚀刻制作过程 - Google Patents
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Abstract
本发明揭示一种半导体双镶嵌蚀刻制作过程,利用一具有约束等离子体功能的蚀刻反应室,将半导体双镶嵌蚀刻制作过程中,原本于不同反应室中进行的介电层蚀刻、去光阻、去除阻挡层等几个步骤,于该约束等离子体反应室中连续完成。该约束等离子体反应室包含环绕于一个晶片的一个约束环及一个抗蚀刻的上电极板,可使上述步骤均于干净模式下进行。本发明不仅可减少该半导体双镶嵌制作过程所需的时间,且可大幅降低成本。
Description
发明领域
本发明关于一种半导体双镶嵌蚀刻制作过程,特别是关于利用一个约束等离子体反应室进行蚀刻的半导体双镶嵌蚀刻制作过程。
发明背景
随着集成电路的集成度增加,半导体器件的金属导线间的距离也愈来愈近。由该些导线的电阻及相邻导线间的介电质的电容引起RC延迟成为信号传输时间延迟的主要原因且限制了器件速度。此外,为克服改进的制作过程中线宽渐窄的趋势所造成寄生电阻及电容的升高,铜金属导线及具有低介电常数的导线间层(Intermetal Dielectric:IMD)被不断地改进,并应用于深次微米的器件制造以克服由先前制造过程中较窄线宽导致的寄生电阻和电容的增高。
双镶嵌制作过程是用于取代目前以铝-铜为金属线的制作过程,属于晶片制造的后段制作过程,即在形成硅底层的接触栓塞后使用,且依器件设计的金属导线层数,可能需重复进行多次。目前世界上各大半导体厂均投入大量人力及成本来开发双镶嵌制作过程,故其制作过程成果及其稳定度,将极大地影响各大半导体厂的竞争力。
由于铜金属导线不易以气体等离子体(干式)的方式加以蚀刻,因此铜金属连线的制作大都是采用双镶嵌制作过程,而其中的蚀刻部分,为整个双镶嵌制作过程中非常重要的一环。双镶嵌蚀刻制作过程依结构形成顺序的不同而大致上可分为几类,其中图1(a)至图1(d)显示目前最为普遍应用的双镶嵌蚀刻制作过程,其中先完成通孔,再完成其余的结构。参照图1(a),首先蚀刻一半导体器件10的导线间层102、104及一蚀刻停止层106,形成可连接至一阻挡层108的一通孔,即该导线间层104中的缺口。然后,定义一光阻层114作为后续蚀刻沟渠的掩模,且将原本定义该通孔的硬掩模层116暴露于该光阻层114缺口的部分去除。参照图1(b),蚀刻该导线间层102,并停止于该蚀刻停止层106,形成一沟渠,即该导线间层102中的缺口。参照图1(c),去除该光阻层114。参照图1(d),最后蚀刻该阻挡层108及该硬掩模层116,使该通孔可接触位于该阻挡层108下的一金属导线层112,而形成双镶嵌结构。
另一种双镶嵌制作过程是先形成沟渠结构后,再进行后续制作过程,如图2(a)至图2(d)所示。参照图2(a),首先在一半导体器件20上形成具有沟渠的结构,包含导线间层202、204、一蚀刻停止层206、一阻挡层208、一金属导线层212及一光阻层214。该导线间层202中的缺口即为一沟渠。该光阻层214中的缺口,则供后续蚀刻通孔使用。参照图2(b),蚀刻该蚀刻停止层206及导线间层204,且停止于该阻挡层208,形成一通孔。参照图2(c),去除该光阻层214,并覆盖一硬掩模层216作为后续去除该阻挡层208的掩模。参照图2(d),蚀刻该阻挡层208及该硬掩模层216,而形成双镶嵌结构。
除了上述的双镶嵌蚀刻制作过程外,还有一种不需蚀刻停止层106、206的方法如图3(a)至图3(e)所示。参照图3(a),一半导体器件30包含一导线间层302、一阻挡层304、一金属导线层306、一硬掩模层308及一光阻层312。该导线间层302中的缺口即为一通孔。参照图3(b),蚀刻该硬掩模层308,定义出沟渠所需图样。参照图3(c),蚀刻该导线间层302,并于中途停止蚀刻,而于该导线间层302的上部形成一沟渠。参照图3(d),去除该光阻层312。参照图3(e),蚀刻该阻挡层304及该硬掩模层308,且使该通孔可接触该金属导线层306。
大部分已知的蚀刻反应室的设计均采用所谓的聚合物化的模式,或称为脏模式,即于在蚀刻前该反应室内表面沉积一聚合物层,一方面防止等离子体直接接触反应室内壁而造成金属污染,另一方面可得到对光阻较高的选择性。此外,因目前大量生产的光阻大部分是一有机物,而已知去光阻的方法均使用另一光阻去除剂以氧气或氧气等离子体去除光阻,或于一酸槽中以热硫酸及双氧水混合溶液去除。若于蚀刻反应室中以氧气等离子体去除光阻,将连同该聚合物层一并去除。故上述的通孔或沟渠蚀刻、去除光阻、蚀刻阻挡层及去除硬掩模层等制作过程步骤,并无法于同一蚀刻反应室中完成,而必须于不同机台中分别进行。一般蚀刻制作过程是于真空状态下反应,故晶片于更换机台时必须经过通风、不同机台间传送、抽真空及机械手臂传送等制作过程,若再加上待机的时间,非常不符合时间成本的效益。
发明的简要说明
本发明的半导体双镶嵌蚀刻制作过程,是应用于一约束等离子体反应室,将上述各制作过程步骤于该约束等离子体反应室中连续完成,可有效减少制作过程时间及生产成本。另外,本发明的双镶嵌蚀刻制作过程是于一干净模式下进行,可减少传统的聚合物化模式的记忆效应所导致的制作过程不稳定。故本发明的双镶嵌蚀刻制作过程可将不同的制作过程步骤于同一反应室中进行,且由于该约束等离子体反应室中并无聚合物的残留,故可降低微尘的数量及产生机率,而延长预防维护(PM)实施的周期。
本发明的半导体双镶嵌蚀刻制作过程,是应用于一约束等离子体反应室,该约束等离子体反应室包含环绕于一晶片的一约束环及一抗蚀刻的上电极板。该半导体双镶嵌蚀刻制作过程包含蚀刻至少一介电层、去除一光阻层及蚀刻一阻挡层等步骤。上述步骤均于干净模式下进行,且于该约束等离子体反应室中连续完成,不需经由其它机台,因此可有效节省机台投资的成本。
该约束环可由石英组成,用以防止等离子体外泄而接触到该反应室内壁。上电极板可由硅组成。石英为一种二氧化硅组成,而一般介电层也为一种二氧化硅组成,只是构造不同。故蚀刻时由石英组成的约束环可产生挥发性的气体,如一氧化碳(CO)及氟化硅(SiF4)等。且该石英环可能会于蚀刻制作过程中释放石英材料中的氧,故可有效的避免聚合物的沉积。介电质蚀刻中常用的碳-氟(CxFy)气体对于硅有相当高的选择性,即对硅的蚀刻速率非常慢,故不易因蚀刻受损伤,可作为上电极板使用。且该硅板具有结合气体等离子体中的氟的功能,可提升蚀刻时的选择性。
本发明亦可应用于一具有含硅光阻层的双镶嵌蚀刻制作过程,利用干蚀刻的方式定义出沟渠的图样,以取代传统的石版印刷制作过程中的显影步骤,并改善光阻选择性不足的问题。另外,若制作过程中包含一硬掩模层,则必须增加一步骤将该硬掩模层去除。
附图简述本发明将依附图加以说明,其中:图1(a)至图1(d)显示已知的先形成通孔的双镶嵌蚀刻制作过程;图2(a)至图2(d)显示已知的先形成沟渠的双镶嵌蚀刻制作过程;图3(a)至图3(e)显示已知的无蚀刻停止层的双镶嵌蚀刻制作过程;图4是本发明的约束等离子体反应室的构造示意图;图5(a)至图5(d)显示本发明的应用于约束等离子体反应室的双镶嵌蚀刻制作过程;及图6(a)至图6(f)显示本发明的另一应用于约束等离子体反应室的双镶嵌蚀刻制作过程。
较佳实施例说明
本发明的较佳实施例的约束等离子体反应室如图4所示。该约束等离子体反应室40的一晶片402置于一静电式吸附台(ESC)404上。一石英环406环绕于该晶片402周围而作为一约束环,以防止蚀刻时所产生的等离子体408接触该约束等离子体反应室40的内壁410。一硅板412构成该约束等离子体反应室40的上电极。一由硅组成的边缘环414置于该石英环406的下方,一方面与该硅板412及该石英环406形成一封闭区间以约束该等离子体408,另一方面则可提高该晶片402于边缘处的选择性。
本发明是于一干净模式下进行,在理想的状况下,该约束等离子体反应室40中并不会有聚合物的沉积,故可于该反应室中直接以氧气等离子体进行原始光阻去除,且同时清洁该约束等离子体反应室40中残留的聚合物。此外,亦可于每片晶片蚀刻完成且离开该约束等离子体反应室40后,施以一无晶片自动清洁(WAC)来清洁该约束等离子体反应室40中的制作过程对象(process kits)。由于在该约束等离子体反应室40中可直接去光阻,不需移至另一种机台进行,故可将双镶嵌蚀刻制作过程中所有的步骤于该约束等离子体反应室40中连续完成。
图5(a)至图5(d)显示本发明的应用于约束等离子体反应室的双镶嵌蚀刻制作过程,其中所有的步骤均于该约束等离子体反应室40中完成。参照图5(a),提供一通孔已完成的半导体器件50,该半导体器件50包含一导线间层502、一蚀刻停止层506、另一导线间层504、一阻挡层508、一金属导线层512、一光阻层514及一硬掩模层516。该导线间层502、504均由介电材料组成,而该蚀刻停止层506、阻挡层508及硬掩模层516可由氮化硅(Si3N4)、碳化硅(SiC)或氮氧化硅(SiON)组成。参照图5(b),以碳-氟为主的混合气体(如CF4、CHF3、C4F8等)等离子体蚀刻该导线间层502,并停止于该蚀刻停止层506。该导线间层502中的缺口即一沟渠结构。参照图5(c),以氧气为主的混合气体等离子体去除该光阻层514,且亦可添加CF4以增加去除聚合物的能力。参照图5(d),以CF4为主的混合气体等离子体蚀刻该阻挡层508及去除该硬掩模层516,而形成双镶嵌结构。值得注意的是,去除该光阻层514的步骤与去除该阻挡层508及该硬掩模层516的步骤可依制作过程需要而更换其顺序。如此一来,甚至可省略该硬掩模层516,而直接以该光阻层514作为蚀刻该阻挡层508时的掩模。
图6(a)至图6(d)显示本发明的另一应用于约束等离子体反应室的双镶嵌蚀刻制作过程,用以解决蚀刻时光阻选择性不足的问题。其中所有的步骤亦可于该约束等离子体反应室中连续完成。参照图6(a),提供一具有半完成的通孔的半导体器件60。该半导体器件60包含导线间层602、604、一蚀刻停止层606、一阻挡层608、一金属导线层612、一硬掩模层614、一光阻层616及一含硅光阻层618。参照图6(b),利用氧气、氮气等混合气体等离子体蚀刻该光阻层616,而定义出沟渠及通孔所需的图样,用以取代光微影制作过程中的显影步骤。参照图6(c),以CF4为主的混合气体等离子体蚀刻该蚀刻停止层606及该硬掩模614。参照图6(d),以CF4、CHF3或C4F8为主的混合气体等离子体蚀刻该导线间层602、604,而形成通孔及沟渠结构。参照图6(e),以碳-氟及氧气为主的混合气体等离子体依序去除该含硅光阻层618及光阻层616。参照图6(f),以CF4为主的气体等离子体去除该阻挡层608及该硬掩模层614,而形成双镶嵌结构。
除了上述的实施例之外,凡是先形成沟渠及无蚀刻停止层的双镶嵌制作过程等种种变化,均可应用本发明的整合式双镶嵌介电层蚀刻制作过程于同一约束等离子体反应室中而连续完成。
本发明的技术内容及技术特点已揭示如上,然而熟悉本项技术的人士仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰。因此,本发明的保护范围应不限于实施例所揭示的,而应包括各种不背离本发明的替换及修饰,并为以下的申请专利范围所涵盖。
Claims (18)
1.一种应用于约束等离子体反应室的半导体双镶嵌蚀刻制作过程,该约束等离子体反应室是处于一干净模式且包含一约束环及一抗蚀刻的上电极板,该半导体双镶嵌蚀刻制作过程包含下列步骤:
提供具有一通孔、一导线间层、一金属导线层、一阻挡层及一用于定义沟渠图样的光阻层的一晶片,且该晶片是设置于该约束环及该上电极板所形成的封闭空间内;
蚀刻该导线间层,用以形成该沟渠;
通过等离子体去除该光阻层,且同时清洁该约束等离子体反应室;及
蚀刻该阻挡层,使该通孔可接触该阻挡层下的该金属导线层。
2.如权利要求1所述的半导体双镶嵌蚀刻制作过程,其中还包含一蚀刻一硬掩模的步骤。
3.如权利要求1所述的半导体双镶嵌蚀刻制作过程,其中该光阻层为一含硅光阻层。
4.如权利要求1所述的半导体双镶嵌蚀刻制作过程,还包括一清洁步骤,在该晶片离开该约束等离子体反应室后,去除该约束等离子体反应室中残留的聚合物。
5.如权利要求4所述的半导体双镶嵌蚀刻制作过程,其中该清洁步骤是使用氧气等离子体进行。
6.如权利要求4所述的半导体双镶嵌蚀刻制作过程,其中该清洁步骤是使用包含氧气与CF4的混合等离子体进行。
7.如权利要求1所述的半导体双镶嵌蚀刻制作过程,其中该约束环是以石英制成。
8.如权利要求1所述的半导体双镶嵌蚀刻制作过程,其中该上电极板是以硅制成。
9.如权利要求1所述的半导体双镶嵌蚀刻制作过程,其中该导线间层是以基于碳-氟气体为主的等离子体进行蚀刻。
10.如权利要求1所述的半导体双镶嵌蚀刻制作过程,其中该等离子体是氧气等离子体。
11.如权利要求1所述的半导体双镶嵌蚀刻制作过程,其中该等离子体是包含氧气及CF4的混合等离子体。
12.如权利要求1所述的半导体双镶嵌蚀刻制作过程,其中该阻挡层是以基于CF4的混合等离子体来去除。
13.一种应用于约束等离子体反应室的半导体双镶嵌蚀刻制作过程,该约束等离子体反应室是处于一干净模式且包含一约束环及一抗蚀刻的上电极板,该半导体双镶嵌蚀刻制作过程包含下列步骤:
提供具有一沟渠、一导线间层、一金属导线层、一阻挡层及一用于定义通孔图样的光阻层的一晶片,且该晶片是设置于该约束环及该上电极板所形成的封闭空间内;
蚀刻该导线间层,用以形成该通孔;
通过等离子体去除该光阻层,且同时清洁该约束等离子体反应室;及
蚀刻该阻挡层,使该通孔可接触该阻挡层下的该金属导线层。
14.如权利要求13所述的半导体双镶嵌蚀刻制作过程,还包括一清洁步骤,在该晶片离开该约束等离子体反应室后,去除该约束等离子体反应室中残留的聚合物。
15.如权利要求14所述的半导体双镶嵌蚀刻制作过程,其中该清洁步骤是利用氧气等离子体进行。
16.一种应用于约束等离子体反应室的半导体双镶嵌蚀刻制作过程,该约束等离子体反应室是处于一干净模式且包含一约束环及一抗蚀刻的上电极板,该半导体双镶嵌蚀刻制作过程包含下列步骤:
提供具有一导线间层、一金属导线层、一阻挡层及一用于定义沟渠图样的光阻层的一晶片,且该晶片是设置于该约束环及该上电极板所形成的封闭空间内;
蚀刻该导线间层,用以形成该沟渠及一通孔;
通过等离子体去除该光阻层,且同时清洁该约束等离子体反应室;及
蚀刻该阻挡层,使该通孔可接触该阻挡层下的该金属导线层。
17.如权利要求16所述的半导体双镶嵌蚀刻制作过程,还包括一清洁步骤,在该晶片离开该约束等离子体反应室后,去除该约束等离子体反应室中残留的聚合物。
18.如权利要求17所述的半导体双镶嵌蚀刻制作过程,其中该清洁步骤是使用氧气等离子体进行。
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CN1251310C (zh) | 2006-04-12 |
TW567554B (en) | 2003-12-21 |
US6559049B2 (en) | 2003-05-06 |
US20030032278A1 (en) | 2003-02-13 |
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