CN1299352C - 制造动态随机存取存储器单元电容器的方法 - Google Patents
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Abstract
本发明提供了制造具有改善的垂直和底部形貌的极柱型电容器的方法。在抗反射涂层上淀积存储节点的导电层。在腐蚀导电层和后续的过腐蚀存储节点图形的步骤中,抗反射涂层使得在存储节点的侧壁上更易形成聚合物集结。所得到的聚合物集结作为腐蚀阻挡层。
Description
技术领域
本发明涉及半导体制造,特别是制造叠层电容器的方法。
背景技术
集成电路电容器被广泛地应用在集成电路器件中。例如,在动态随机存取存储器(DRAM)中,集成电路电容器可以用于在其中存储电荷而保存数据。随着DRAM器件集成度的持续增加,在减少各个电容器在集成电路衬底上所占有的面积的同时,需要保持足够高的存储电容量。
在集成电路电容器的集成度增加时,将电容器的下电极,也称作存储节点,与下面的接触孔对准变得更加困难。而为了在减少电容器的衬底表面面积的同时让电容器具有较高的容量,当面积减少时可以增加存储节点的高度。例如在叠层电容器结构中,存储节点的高度可以增加到一微米或更高。这可以导致存储节点的高的深宽比,例如超过5的深宽比。高的深宽比难以对厚的导电层进行构图,形成存储节点。
形成叠层电容器的传统工艺如下:在半导体衬底上形成绝缘层。在绝缘层内开有通到半导体衬底有源区的接触,再将导电材料淀积在接触开口内以形成接触栓塞。将厚的导电层淀积在含有接触栓塞的绝缘层上。进行各向异性腐蚀,以腐蚀各个接触栓塞间的厚的导电层,并由此形成叠层电容器。一般在主腐蚀厚的导电层后进行过腐蚀,以使腐蚀均匀,且避免各个存储节点和其相邻节点间的微跨接。
遗憾的是,在存储节点的各向异性的腐蚀中,可能发生侧向腐蚀,特别是在过腐蚀工艺中,上述侧向腐蚀可能破坏存储节点。特别地,随着腐蚀工艺继续腐蚀到暴露出绝缘层的上表面,所暴露的层可能被腐蚀剂正充电。其结果,腐蚀剂气体将存储节点的底端腐蚀而引起底割(undercut)现象。
发明内容
鉴于上述问题而做出本发明,本发明的目的在于提供制造DRAM单元电容器的方法,该方法能够防止电容器电极的侧向腐蚀。
本发明的另一目的在于提供制造DRAM单元电容器的方法,该方法能够减少电容器下电极在其制造过程中的破损。
本发明的上述和其它目的通过在氧化层(在其中开有接触)和存储节点的多晶硅层间形成抗反射涂层来实现。上述抗反射涂层由如SiN或SiON一类的材料制成,上述材料与下层的氧化层相比具有较低的反射率,且对于预定的腐蚀剂具有介于绝缘层和多晶硅层之间的腐蚀率。因此,抗反射涂层能够使得在下电极的底端较易形成聚合物集结,并由此防止下电极在其底部的侧向腐蚀。
特别地,通过形成由半导体衬底上的氧化物组成的绝缘层来制造叠层下电极。在绝缘层上淀积抗反射涂层。在抗反射涂层和绝缘层内开有接触。在接触开口内和抗反射涂层上淀积如多晶硅层一类的导电层并达到决定下电极的高度的厚度。在各个接触开口和相邻接触开口间的导电层被各向异性腐蚀,形成下电极。
上述抗反射涂层包括氮化硅(SiN)层和氮氧化硅(SiON)层中的至少一种。各向异性腐蚀使用包含有六氟化物(SF6)、氯化物(Cl2)和氮气(N2)的混合腐蚀剂。在腐蚀中,最好过腐蚀抗反射涂层,在与抗反射涂层相邻的下电极的底端形成聚合物。通过腐蚀剂气体和被腐蚀层间的反应形成聚合物。例如,所形成的聚合物层包括SiFXNY。在下电极的底端上的形成的聚合物集结保护其不受腐蚀剂气体腐蚀。
本发明的一方面,接触栓塞可以在接触开口内形成。换句话说,在形成接触开口后,在接触开口内填充第一导电材料,形成接触栓塞。然后,在含有接触栓塞的抗反射涂层上淀积下电极的第二导电层。对第二导电层进行腐蚀,形成下电极。
附图说明
通过参考以下附图,对于本领域的技术人员来说可以理解本发明,使本发明的目的变得明了。
图1是根据本发明所述的半导体衬底的横断面图,其中绝缘层和抗反射涂层已形成且在其中开有接触;
图2示出了在如图1中所示的后面的工序步骤,其中在接触开口内形成了接触栓塞;
图3示出了在如图2中所示的后面的工序步骤,其中在其侧壁上形成聚合物集结的同时形成了中间的下电极;
图4示出了在如图3中所示的后面的工序步骤,其中完全形成具有良好的垂直形貌的下电极。
具体实施方式
下面将参照附图对本发明进行全面的描述,其中示出了本发明的实施例。然而本发明可以以不同的形式实施,而且不局限于这里示出的实施例。更确切地说,提出上述实施例是为了使本发明公开得更全面和完整,对于本领域的技术人员来说,能够充分地表达本发明的范围。在图中,为了清楚起见,层和区域的厚度被夸大。另外,在此描述和阐述的各个实施例也包括与它相反导电类型的实施例。为了清楚起见,在图中只示出一个电容器和一个晶体管。
图1示意地示出了根据本发明的已经经过一些工艺的半导体衬底的横截面图。器件隔离层102在半导体衬底100的预定的区域内形成以限定其内的有源区和无源区。在有源区上形成晶体管。在现有技术中已经知道,晶体管包括涂有氮化硅层(也即,硬掩模和侧壁间隔层)的栅电极104和一对源/漏区106。晶体管的制造在现有技术中已经知道,在此不需要再进行描述。
在半导体衬底100上和晶体管上淀积如氧化层一类的第一绝缘层108。在第一绝缘层108上淀积抗反射涂层110,其厚度约在200埃至600埃。上述抗反射涂层110由如SiN或SiON一类的材料制成,上述材料与下面的第一绝缘层108相比具有较低的反射率,且对于预定的腐蚀剂具有介于第一绝缘层和后面的用于形成下电极的导电层之间的腐蚀率。同时,抗反射涂层区域110允许用于接触孔形成的光工艺裕度。
利用已知的光腐蚀工艺,在抗反射涂层110内和第一绝缘层108内开有通向源/漏区106之一的接触112。在接触开口内淀积第一导电层并被平面化,形成如图2所示的接触栓塞114。上述平面化可以通过化学机械抛光或深腐蚀技术进行。上述第一导电层由多晶硅制成。
在上述所得到的结构上淀积下电极的第二导电层。第二导电层的厚度由所要求的电容量所决定。例如,多晶硅淀积到厚度约为8,000埃到12,000埃。利用光腐蚀工艺,第二绝缘层的选中区域被腐蚀以形成如图3所示下电极116。腐蚀包括各向异性的干腐蚀。特别地,干腐蚀使用约20到50sccm的Cl2、1到10sccm的SF6和1到10sccm的N2的混合物,在约2到30mtorr的压力、约400至800W的源功率、约30至100W的偏置功率的条件下进行。进行过腐蚀以使腐蚀均匀且避免各个存储节点与相邻节点间的微跨接。在这时,在下电极116的侧壁上形成如SiFXNY一类的聚合物118(腐蚀副产品)的同时,腐蚀了抗反射层涂层110的部分厚度。上述聚合物层118保护下电极116的侧壁在过腐蚀过程中不被腐蚀剂腐蚀。
用于下电极的光腐蚀工艺如下。将第二绝缘层(未示出)作为掩模淀积在第二导电层上。第二绝缘层由氮氧化硅层组成。将光致抗蚀剂层旋转涂覆在第二绝缘层上并构图成所需要的形状以限定下电极。利用构图的光致抗蚀剂层,腐蚀第二绝缘层,形成掩模图形。利用所构图的光致抗蚀剂层和掩模图形,在第二导电层上进行上述各向异性腐蚀,形成如图3所示的下存储节点结构。
在使用传统的方法去除构图的光致抗蚀剂层后,去除第二绝缘层、第一绝缘层108。利用H3PO4溶液在约100℃到200℃的温度下执行1到10分钟的腐蚀工艺,然后利用SC-1溶液在约50℃到100℃的温度下执行1到10分钟的清洗工艺来除去第二绝缘层。在上述腐蚀和清洗工艺中,聚合物118和第一绝缘层110也被除去,于是形成如图4所示的完整的下电极116。
根据本发明的另一实施例,同时形成接触栓塞和下电极。在形成接触开口112后,在接触开口112内和抗反射涂层110上淀积用于形成下电极的导电层,至决定下电极高度的厚度。利用上述光腐蚀工艺,对导电层进行腐蚀,形成下电极。
Claims (17)
1.一种在DRAM中制造电容器的方法,包括步骤:
在具有多个源/漏区的半导体衬底上形成底层,所述底层具有含有氮的抗反射涂层;
腐蚀所述底层的选中部分并形成多个通到所述源/漏区的开口;
在所述开口内和所述底层上淀积上导电层;
腐蚀所述上导电层并腐蚀各个开口间的所述抗反射涂层的部分厚度,以形成多个导电极,同时在所述导电极的各个侧壁上形成腐蚀副产品集结作为腐蚀阻挡层。
2.根据权利要求1所述的方法,其特征在于:所述上导电层包括多晶硅。
3.根据权利要求1所述的方法,其特征在于:所述抗反射涂层从SiN和SiON中选择。
4.根据权利要求1所述的方法,其特征在于:所述抗反射涂层的厚度在200埃到600埃的范围。
5.根据权利要求1所述的方法,其特征在于:所述上导电层的厚度在8,000埃到12,000埃的范围。
6.根据权利要求1所述的方法,其特征在于:所述腐蚀所述上导电层的步骤包括干腐蚀。
7.根据权利要求6所述的方法,其特征在于:所述干腐蚀是在使用20到50sccm的Cl2、1到10sccm的SF6和1到10sccm的N2的混合物在2到30mtorr的压力和400至800W的源功率、30至100W的偏置功率的条件下进行的。
8.根据权利要求1所述的方法,其特征在于:所述腐蚀副产品集结包括SiFXNY。
9.一种在DRAM中制造电容器的方法,包括步骤:
在具有包括源区、漏区和栅电极的晶体管的半导体衬底上形成多层绝缘层,所述多层绝缘层具有包括氮的抗反射涂层绝缘层;
腐蚀所述多层绝缘层并在其内开出通到所述漏区的接触孔;
用第一导电层填充所述接触孔以形成接触栓塞;
在所述多层绝缘层上和所述接触栓塞上淀积第二导电层;
腐蚀所述第二导电层并腐蚀各个接触栓塞间的所述抗反射涂层绝缘层的部分厚度以形成导电极,同时在所述导电极的侧壁上形成腐蚀副产品集结作为腐蚀阻挡层。
10.根据权利要求9所述的方法,其特征在于:所述第一导电层包括多晶硅。
11.根据权利要求9所述的方法,其特征在于:所述第二导电层包括多晶硅。
12.根据权利要求9所述的方法,其特征在于:所述抗反射涂层绝缘层从SiN和SiON中选择。
13.根据权利要求9所述的方法,其特征在于:所述抗反射涂层绝缘层的厚度在200埃到600埃之间。
14.根据权利要求9所述的方法,其特征在于:所述第二导电层的厚度在8,000埃到12,000埃之间。
15.根据权利要求9所述的方法,其特征在于:所述腐蚀所述第二导电层的步骤包括干腐蚀。
16.根据权利要求15所述的方法,其特征在于:所述干腐蚀是在使用20到50sccm的Cl2、1到10sccm的SF6和1到10sccm的N2的混合物在2到30mtorr的压力和400至800W的源功率、30至100W的偏功率的条件下进行的。
17.根据权利要求9所述的方法,其特征在于:所述腐蚀副产品集结包括SiFXNY。
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KR1019980026583A KR100272670B1 (ko) | 1998-07-02 | 1998-07-02 | 반도체 장치의 제조 방법 |
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JP (1) | JP3987239B2 (zh) |
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KR100625393B1 (ko) * | 2004-01-05 | 2006-09-19 | 주식회사 하이닉스반도체 | 반도체소자의 제조방법 |
CN112599474B (zh) * | 2020-12-21 | 2023-04-07 | 维沃移动通信(重庆)有限公司 | 闪存器件制作方法、闪存器件及电子设备 |
Citations (3)
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US5208657A (en) * | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
US5494841A (en) * | 1993-10-15 | 1996-02-27 | Micron Semiconductor, Inc. | Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells |
JPH08330539A (ja) * | 1995-05-31 | 1996-12-13 | Nec Corp | 半導体装置の製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US5208657A (en) * | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
US5494841A (en) * | 1993-10-15 | 1996-02-27 | Micron Semiconductor, Inc. | Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells |
JPH08330539A (ja) * | 1995-05-31 | 1996-12-13 | Nec Corp | 半導体装置の製造方法 |
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KR100272670B1 (ko) | 2000-12-01 |
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TW406412B (en) | 2000-09-21 |
CN1241024A (zh) | 2000-01-12 |
KR20000007304A (ko) | 2000-02-07 |
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