CN118276633A - Voltage follower with process error compensation and method - Google Patents
Voltage follower with process error compensation and method Download PDFInfo
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Abstract
The invention discloses a voltage follower with process error compensation and a method thereof, wherein the voltage follower comprises: the voltage follower main circuit realizes the following from input voltage to output voltage, the compensation generating circuit generates compensation current related to a process angle, the reference current source provides bias for the circuit, when the process angle changes, the compensation generating circuit detects the change and outputs compensation current corresponding to the change, so that voltage drops at two sides of a compensation resistor in the voltage follower main circuit are changed to offset process error voltage, finally, the output voltage is consistent with the input voltage, the process angle compensation function is realized, the output consistency of the voltage follower circuit is greatly improved, and the stability of the circuit under different processes is ensured.
Description
Technical Field
The invention relates to a voltage follower with process error compensation and a method thereof, belonging to the technical field of signal conditioning circuits.
Background
In analog circuits, a voltage follower (also known as a buffer amplifier, a unity gain amplifier, or an isolation amplifier) is an operational amplifier circuit whose output voltage is equal to the input voltage (it "follows" the input voltage). Therefore, the voltage follower operational amplifier does not amplify the input signal, and the voltage gain is 1. The main function of the circuit is to isolate the input signal from the output signal, perform the function of impedance conversion and improve the load capacity of the circuit.
The simplest voltage follower is a negative feedback operational amplifier. The feedback of the output voltage is directly connected to the inverting input terminal and the homodromous input terminal is connected to the input voltage, so that the output voltage is equal to the input voltage. Another common voltage follower is a cascade of a P-type source follower and an N-type source follower. The P-type source electrode follower lifts the input voltage, and the N-type source electrode follower reduces the lifted voltage, so that the follow-up from input to output is realized. However, since the threshold voltage of the MOS transistor is greatly affected by the process, the rising or falling amplitude of the P-type source follower or the N-type source follower to the voltage is also changed, which makes the output voltage unable to accurately follow the input voltage, and affects the accuracy of the output voltage.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the voltage follower with the process error compensation and the method thereof are provided, and the compensation current related to the process angle flows through the compensation resistor between the P-type source follower and the N-type source follower of the voltage follower, so that the voltage drop at two ends of the compensation resistor is related to the change of the process angle, the output voltage is finally equal to the input voltage, the process angle compensation function is realized, the output consistency of the voltage follower is greatly improved, and the stability of the circuit under different processes is ensured.
The invention adopts the following technical scheme for solving the technical problems:
A voltage follower with process error compensation, the voltage follower comprising: the voltage follower main circuit, the compensation generating circuit and the reference current source; the compensation generating circuit is used for detecting the process angle change and outputting two compensation currents Ip and In which are equal In size and opposite In direction and correspond to the process angle change; the compensation current flows through a compensation resistor in the voltage follower main circuit to generate a compensation voltage, and the compensation voltage enables the output voltage and the input voltage of the voltage follower main circuit to be kept equal; the reference current source is used for generating a P-type first bias voltage, a P-type second bias voltage, an N-type first bias voltage and an N-type second bias voltage, transmitting the N-type first bias voltage and the N-type second bias voltage to the compensation generating circuit, providing N-type current bias for the compensation generating circuit, transmitting the P-type first bias voltage, the P-type second bias voltage, the N-type first bias voltage and the N-type second bias voltage to the voltage follower main circuit, and providing P-type current bias and N-type current bias for the voltage follower main circuit.
As a preferred embodiment of the present invention, the compensation generating circuit includes: PMOS tube MP3-MP17, NMOS tube MN3-MN21 and resistors R1-R4; the source of the PMOS tube MP3, the source of the PMOS tube MP4, the source of the PMOS tube MP5, the source of the PMOS tube MP6, the source of the PMOS tube MP7, the source of the PMOS tube MP9, one end of the resistor R3, the source of the PMOS tube MP11, the source of the PMOS tube MP12, the source of the PMOS tube MP13, the source of the PMOS tube MP14 and the source of the PMOS tube MP16 are connected with a power supply together; The source of the NMOS tube MN3, the source of the NMOS tube MN7, one end of a resistor R1, the source of the NMOS tube MN10, the source of the NMOS tube MN12, one end of a resistor R4, the source of the NMOS tube MN16, one end of a resistor R2, the source of the NMOS tube MN19 and the source of the NMOS tube MN21 are grounded together; the grid electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP3, the drain electrode of the NMOS tube MN3, the grid electrode of the NMOS tube MN3 and the grid electrode of the NMOS tube MN4, the grid electrode of the PMOS tube MP4 is connected with the grid electrode of the PMOS tube MP5, the drain electrode of the PMOS tube MP4 and the drain electrode of the NMOS tube MN4, and the drain electrode of the PMOS tube MP5 is connected with the drain electrode of the NMOS tube MN5 and the grid electrode of the NMOS tube MN 8; The grid electrode of the NMOS tube MN5 is connected with the source electrode of the NMOS tube MN8 and the other end of the resistor R1, the source electrode of the NMOS tube MN4 is connected with the source electrode of the NMOS tube MN5 and the drain electrode of the NMOS tube MN6, the source electrode of the NMOS tube MN6 is connected with the drain electrode of the NMOS tube MN7, the grid electrode of the PMOS tube MP6 is connected with the grid electrode of the PMOS tube MP7, the grid electrode of the PMOS tube MP9, the drain electrode of the PMOS tube MP6 and the drain electrode of the NMOS tube MN8, the drain electrode of the PMOS tube MP7 is connected with the source electrode of the PMOS tube MP8, The drain electrode of the PMOS tube MP9 is connected with the source electrode of the PMOS tube MP10, the grid electrode of the PMOS tube MP8, the drain electrode of the NMOS tube MP8, the grid electrode of the NMOS tube MN9, the grid electrode of the NMOS tube MN11 and the drain electrode of the NMOS tube MN9 are connected together, the source electrode of the NMOS tube MN9 is connected with the drain electrode of the NMOS tube MN10, the grid electrode of the NMOS tube MN10 and the grid electrode of the NMOS tube MN12, the source electrode of the NMOS tube MN11 is connected with the drain electrode of the NMOS tube MN12, the other end of the resistor R3 is connected with the other end of the resistor R4 and the grid electrode of the NMOS tube MN13, The grid electrode of the PMOS tube MP11 is connected with the grid electrode of the PMOS tube MP12, the drain electrode of the PMOS tube MP11 and the drain electrode of the NMOS tube MN13, the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN14 and the grid electrode of the NMOS tube MN17, the grid electrode of the NMOS tube MN14 is connected with the source electrode of the NMOS tube MN17 and the other end of the resistor R2, the source electrode of the NMOS tube MN13 is connected with the source electrode of the NMOS tube MN14 and the drain electrode of the NMOS tube MN15, the source electrode of the NMOS tube MN15 is connected with the drain electrode of the NMOS tube MN16, The grid electrode of the PMOS tube MP13 is connected with the grid electrode of the PMOS tube MP14, the grid electrode of the PMOS tube MP16, the drain electrode of the PMOS tube MP13 and the drain electrode of the NMOS tube MN17, the drain electrode of the PMOS tube MP14 is connected with the source electrode of the PMOS tube MP15, the drain electrode of the PMOS tube MP16 is connected with the source electrode of the PMOS tube MP17, the grid electrode of the PMOS tube MP15 is connected with the grid electrode of the PMOS tube MP17, the drain electrode of the NMOS tube MP15, the grid electrode of the NMOS tube MN18, the grid electrode of the NMOS tube MN20 and the drain electrode of the NMOS tube MN18, The source electrode of the NMOS tube MN18 is connected with the drain electrode of the NMOS tube MN19, the grid electrode of the NMOS tube MN19 and the grid electrode of the NMOS tube MN21, and the source electrode of the NMOS tube MN20 is connected with the drain electrode of the NMOS tube MN 21; The grid electrode of the NMOS tube MN7 and the grid electrode of the NMOS tube MN16 are connected with the N-type first bias voltage, and the grid electrode of the NMOS tube MN6 and the grid electrode of the NMOS tube MN15 are connected with the N-type second bias voltage; the drain of NMOS tube MN11 and the drain of PMOS tube MP17 generate compensation current In, and the drain of PMOS tube MP10 and the drain of NMOS tube MN20 generate compensation current Ip.
As a preferred embodiment of the present invention, the voltage follower main circuit includes: PMOS tube MP0-MP2, NMOS tube MN0-MN2 and resistor R0; the source electrode of the PMOS tube MP0 and the drain electrode of the NMOS tube MN0 are connected with a power supply together, and the drain electrode of the PMOS tube MP2 and the source electrode of the NMOS tube MN2 are grounded together; the drain electrode of the PMOS tube MP0 is connected with the source electrode of the PMOS tube MP1, and the drain electrode of the PMOS tube MP1 is connected with the source electrode of the PMOS tube MP2, one end of the resistor R0 and the compensation current In; the drain electrode of the NMOS tube MN2 is connected with the source electrode of the NMOS tube MN1, and the grid electrode of the NMOS tube MN0 is connected with the other end of the resistor R0 and the compensation current Ip; the grid electrode of the NMOS tube MN1 is connected with the N-type second bias voltage, and the grid electrode of the NMOS tube MN2 is connected with the N-type first bias voltage; the grid electrode of the PMOS tube MP1 is connected with the P-type second bias voltage, and the grid electrode of the PMOS tube MP0 is connected with the P-type first bias voltage; the grid electrode of the PMOS tube MP2 is connected with an input voltage Vin, and the source electrode of the NMOS tube MN0 and the drain electrode of the NMOS tube MN1 are used for outputting a voltage Vout.
As a preferred embodiment of the present invention, the reference current source includes: PMOS tube MP18-MP27, NMOS tube MN22-MN29 and resistor R5; the source of the PMOS transistor MP18, the source of the PMOS transistor MP20, the source of the PMOS transistor MP22, the source of the PMOS transistor MP24, and the source of the PMOS transistor MP26 are connected to a power supply, and the source of the NMOS transistor MN23, the source of the NMOS transistor MN25, the source of the NMOS transistor MN26, the lower end of the resistor R5, and the source of the NMOS transistor MN29 are grounded; the grid electrode of the PMOS tube MP18 is connected with the drain electrode of the PMOS tube MP18 and the source electrode of the PMOS tube MP19 to generate a P-type first bias voltage; the grid electrode of the PMOS tube MP19 is connected with the drain electrode of the PMOS tube MP19 and the drain electrode of the NMOS tube MN22 to generate a P-type second bias voltage; the source electrode of the NMOS tube MN22 is connected with the drain electrode of the NMOS tube MN23, the grid electrode of the NMOS tube MN22 is connected with the grid electrode of the NMOS tube MN24, the drain electrode of the NMOS tube MN24 and the drain electrode of the PMOS tube MP21, and the grid electrode of the NMOS tube MN23 is connected with the grid electrode of the NMOS tube MN25, the drain electrode of the NMOS tube MN25 and the source electrode of the NMOS tube MN 24; the drain electrode of the PMOS tube MP20 is connected with the source electrode of the PMOS tube MP21, the grid electrode of the PMOS tube MP20 is connected with the grid electrode of the PMOS tube MP22, the grid electrode of the PMOS tube MP24, the drain electrode of the PMOS tube MP24, the grid electrode of the PMOS tube MP26 and the source electrode of the PMOS tube MP25, the grid electrode of the PMOS tube MP21 is connected with the grid electrode of the PMOS tube MP23, the grid electrode of the PMOS tube MP25, the grid electrode of the PMOS tube MP27 and the drain electrode of the NMOS tube MN27, the drain electrode of the PMOS tube MP22 is connected with the source electrode of the PMOS tube MP23, the drain electrode of the NMOS tube MN26 and the grid electrode of the NMOS tube MN27 are connected together, the source electrode of the NMOS tube MN27 is connected with one end of the resistor R5, and the drain electrode of the PMOS tube MP26 is connected with the source electrode of the PMOS tube MP 27; the drain electrode of the PMOS tube MP27 is connected with the grid electrode of the NMOS tube MN28 and the drain electrode of the NMOS tube MN28 to generate an N-type second bias voltage, and the source electrode of the NMOS tube MN28 is connected with the grid electrode of the NMOS tube MN29 and the drain electrode of the NMOS tube MN29 to generate an N-type first bias voltage.
The voltage following method of the voltage follower based on the self-carried process error compensation comprises the following steps:
the compensation generating circuit is used for detecting the process angle change and outputting two compensation currents Ip and In which are equal In size and opposite In direction and correspond to the process angle change, the compensation current Ip is generated by the PMOS tube MP10 and the NMOS tube MN20, the compensation current In is generated by the PMOS tube MP17 and the NMOS tube MN11, and the magnitudes of the compensation currents Ip and In are as follows:
，
In the method, in the process of the invention, The current through resistors R1 and R2 respectively,For the gate voltage of NMOS transistor MN4,The gate voltage of the NMOS transistor MN 13;
In the main circuit of the voltage follower, a compensation resistor R0 is introduced, compensation current Ip flows In from one end of the R0, compensation current In flows In from the other end of the R0, and as Ip is equal to In, the current values of other MOS tubes In the circuit cannot change, the original working state of the circuit is unchanged, so that the compensation resistor R0 is equal to a resistor R1 and a resistor R2, a resistor R3 is equal to a resistor R4, the following from an input voltage to an output voltage is realized, the output voltage is not influenced by the process angle change, namely, the voltage change from Vin to Vout satisfies the following conditions:
，
In the method, in the process of the invention, Is the voltage difference between the source electrode and the grid electrode of the PMOS tube MP2,As the voltage difference between the gate and source of NMOS transistor MN0,To compensate for the voltage drop across resistor R0,AndThreshold voltages of all PMOS tubes and all NMOS tubes respectively, andIs a negative value, and is a positive value,Positive values.
Compared with the prior art, the technical scheme provided by the invention has the following technical effects:
The voltage follower with the process error compensation provided by the invention consists of three parts: the compensation generating circuit is used for detecting process angle change and outputting two compensation currents which are equal in size and opposite in direction and correspond to the process angle change; the compensation current flows through the compensation resistor in the voltage follower main circuit to generate compensation voltage, and the compensation voltage enables the output voltage and the input voltage of the voltage follower main circuit to be kept strictly equal, so that the output consistency of the voltage follower circuit is greatly improved, and the stability of the circuit under different processes is ensured.
Drawings
FIG. 1 is a circuit diagram of a voltage follower with process error compensation according to the present invention;
FIG. 2 is a circuit diagram of the proposed voltage follower main circuit;
FIG. 3 (a) is a circuit diagram of a compensation generating circuit according to the present invention;
FIG. 3 (b) is another part of a circuit diagram of the compensation generating circuit according to the present invention;
FIG. 4 is a circuit diagram of a reference current source according to the present invention;
FIG. 5 (a) is a graph showing the simulation effect of compensating current at different process angles without the present invention;
FIG. 5 (b) is a graph of the output voltage corresponding to each process corner when the input signal is 1.3V in the case of FIG. 5 (a);
FIG. 5 (c) is a graph showing the simulated effect of compensation current that has been proposed using the present invention at different process angles;
fig. 5 (d) is a graph of output voltages corresponding to respective process corners when the input signal is 1.3V in the case of fig. 5 (c).
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
As shown in fig. 1, a circuit diagram of a voltage follower with process error compensation according to the present invention includes: the voltage follower circuit comprises a voltage follower main circuit, a compensation generating circuit and a reference current source. The compensation generating circuit generates compensation current which is connected to a compensation resistor in the main circuit of the voltage follower, the reference current source provides voltage and current bias for the circuit, when a process angle changes, the compensation generating circuit detects the change and outputs compensation current corresponding to the process angle change, so that voltage drop at two sides of the compensation resistor of the main circuit of the voltage follower changes, and finally, the difference between the output voltage and the input voltage is zero, and the following function from the input voltage to the output voltage is realized.
The compensation generating circuit generates a compensation current related to the process corner, and the compensation current flows through a compensation resistor of the voltage follower main circuit to generate a compensation voltage. When the process angle changes, the compensation voltage changes along with the process angle, the final output voltage is irrelevant to the process angle and is only relevant to the input voltage, so that the compensation function of the process angle is realized, the output consistency of the voltage follower is greatly improved, and the stability of the circuit under different processes is ensured.
The compensation generating circuit generates two equal and opposite compensation currents Ip and In related to the process angle, which both increase the final output voltage compared with the final output voltage before the compensation resistor and the compensation current are not introducedOr (b)Because the compensation current Ip or In can detect the change of the process angle, the process angle change inside the main circuit of the voltage follower is reflected on the voltage drop at two ends of the resistor R0 by reasonably adjusting the magnitudes of Ip, in and R0, and finally the output signal of the main circuit of the voltage follower is irrelevant to the process angle, so that the expected function of the circuit is realized.
The compensation generating circuit generates two compensation currents Ip and In which have the same magnitude and opposite directions and are related to the process angle, so that no extra current flows into the input signal end and the output signal end after the compensation generating circuit is introduced, and the working state of the original circuit is maintained.
As shown in fig. 2, the input voltage Vin of the voltage follower main circuit reaches the MP2 source through the P-type source follower of the PMOS transistor MP2, then flows through the resistor R0 to reach the gate of the NMOS transistor MN0, and finally is output from the source of the MN0 through the N-type source follower of the MN 0. Due to the compensation currents Ip and In, the signal flow is raised by one across the resistor R0Even if the process angle changes to cause the parameters such as the threshold values of the MP2 pipe and the MN0 pipe to change, the difference between the final output voltage Vout and the input voltage Vin is zero and is irrelevant to the process angle changes.
As shown in fig. 3 (a), the PMOS transistor MP3 and the NMOS transistor MN3 are connected in series to generate the voltage VG. VG generates the same voltage VG on the grid electrode of MN5 through a unit gain buffer circuit formed by MOS tubes MP4, MP5, MN4, MN5, MN6, MN7 and MN 8; when the process angle changes, parameters such as threshold voltages of the PMOS tube MP3 and the NMOS tube MN3 change, so that the voltage VG changes, the grid voltage of the MN5 tube changes, the voltage at two ends of the resistor R1 changes, the current flowing through the resistor R1 can detect the change of the process angle, and the compensation current is output In the form of Ip and In through a current mirror formed by the PMOS tubes MP 6-MP 10 and the NMOS tubes MN 9-MN 12.
Since VG has the expression of the supply voltage Vdd, the compensation voltage generated by the compensation current generated by VG alone must also have Vdd, which needs to be eliminated to ensure that the final output voltage is equal to the input voltage.
As shown in fig. 3 (b), the resistor R3 and the resistor R4 are connected in series to generate a voltage。Is the voltage division of the supply voltage Vdd through the resistors R3 and R4 and is therefore independent of the process corner but dependent on the supply voltage Vdd.The same voltage is generated at the grid electrode of MN14 through a unit gain buffer circuit consisting of MOS tubes MP11, MP12, MN13, MN14, MN15, MN16 and MN17，The current is generated on R2, and then is output In the form of Ip and In through a current mirror composed of PMOS transistors MP 13-MP 17 and NMOS transistors MN 18-MN 21. In is generated by the PMOS transistor MP17, ip is generated by the NMOS transistor MN20, and the polarity of the compensation current generated by the voltage VG is opposite, so that the term of the power supply voltage Vdd can be cancelled when the compensation voltage is generated.
As shown in fig. 4, a bias current source composed of PMOS transistors MP22 to MP25, NMOS transistors MN26 to MN27, and a resistor R5 generates a reference current, which is duplicated by a current mirror composed of PMOS transistors MP26 to MP27, for generating bias voltages VN1 and VN2; the reference current is copied by a current mirror composed of PMOS transistors MP 20-MP 21 and NMOS transistors MN 22-MN 25, and is used for generating bias voltages VP1 and VP2.
The signal reaches the source electrode of the PMOS tube MP2 from the grid electrode of the PMOS tube MP2, and the voltage risesThe signal reaches the source of NMOS transistor MN0 from the gate of NMOS transistor MN0, the voltage dropsIn the case of no compensation current and compensation resistor shorting, the voltage change from Vin to Vout is:
，
Wherein, Is the voltage difference between the source electrode and the grid electrode of the PMOS tube MP2,Is the voltage difference between the gate and source of NMOS transistor MN 0. The current formula of the MOS tube in the saturation region (neglecting the ditch length modulation effect) is as follows:
，
Wherein I is the current flowing through the PMOS tube MP2 or the NMOS tube MN 0.
The P-type current bias and the N-type current bias generated in the reference current source are equal in size, and in design, the following is ensured:
，
in this case, the voltage variation from Vin to Vout satisfies:
，
Wherein, AndIs the threshold voltage of PMOS and NMOS, andIs a negative value, and is a positive value,Positive values. In general, since the threshold values of NMOS and PMOS are not exactly equal in size, and when the process corner changes,AndThe size of the voltage follower is changed, and thus, a general voltage follower cannot accurately perform the following effect of the input voltage to the output voltage.
In the compensation generating circuit, the gate voltage VG of the NMOS transistor MN4 is determined by the PMOS transistor MP3 and the NMOS transistor MN 3. The PMOS tube MP3 and the NMOS tube MN3 are connected in series, and the flowing currents are equal:
，
Wherein Vdd is the supply voltage. The design guarantees that:
，
The two formulas are combined to obtain:
，
Note that, an operational amplifier in a negative feedback state is formed by the NMOS transistor MN4, the NMOS transistor MN5, the NMOS transistor MN6, the NMOS transistor MN7, the NMOS transistor MN8, the PMOS transistor MP4, and the PMOS transistor MP5, so the gate voltages of the NMOS transistor MN4 and the NMOS transistor MN5 are equal. The current flowing through resistor R1 is:
，
Here, the PMOS transistors MP 7-MP 10 and the NMOS transistors MP 9-MP 12 are of a Cascode current mirror structure, which replicates the current flowing through the PMOS transistor MP6, so that the currents flowing through the NMOS transistor MN11 and the PMOS transistor MP10 are both of the same magnitude 。
Gate voltage of NMOS transistor MN13Determined by the partial voltage of the resistors R3 and R4:
，
similarly, the gate voltages of the NMOS transistor MN13 and the NMOS transistor MN14 are equal. The current flowing through resistor R2 is:
，
Therefore, the currents flowing through the NMOS tube MN20 and the PMOS tube MP17 are both 。
The compensation current Ip is generated by the PMOS tube MP10 and the NMOS tube MN20, the compensation current In is generated by the PMOS tube MP17 and the NMOS tube MN11, and the compensation currents Ip and In are obtained by combining the deduction:
，
In the main circuit of the voltage follower, a compensation resistor R0 is introduced, compensation current Ip flows from the upper part of R0, and compensation current In flows from the lower part of R0, so that the current values of other MOS tubes In the circuit cannot change, and the original working state of the circuit is unchanged. In the design, let resistance R1 and resistance R2 equal, at this time, the voltage drop across compensation resistor R0 is:
，
After the introduction of the compensation resistor R0, the voltage variation from Vin to Vout satisfies:
，
simplifying and shifting the term to obtain:
，
Wherein the coefficient is The numerator and denominator of (a) comprise resistors, the ratio matching between the resistors belongs to local random mismatch, and the error is far lower than the global process angle change, so that the resistors can be consideredIs constant not affected by process angle variation; in the circuit design, it is necessary to ensure that the resistances of the resistors R0, R1 and R2 are equal, and the resistances of the resistor R3 and the resistor R4 are equal, so that the coefficientsAndAnd the output voltage and the input voltage of the voltage follower are equal and are not influenced by the process angle change when the output voltage and the input voltage are 0.
As shown in fig. 5 (a), in order to show the simulation effect of the compensation current provided by the invention under different process angles, a total of 15 process angle combinations are provided for five process angles (tt, ff, ss, snfp, fnsp) of the MOS transistor and three process angles (tt, ff, ss) of the resistor; for the same input voltage, as shown in fig. 5 (b), taking vin=1.3v as an example, vout= 1.2746V corresponding to the standard process angle (MOS transistor: tt, resistor: tt), and output voltages corresponding to the other process angles are distributed between 1.2050V and 1.3473V, and the variation range is 0.1423V.
As shown in fig. 5 (c), in order to show the simulation effect of the compensation current proposed by the present invention under different process angles, a total of 15 process angle combinations are performed for five process angles (tt, ff, ss, snfp, fnsp) and three process angles (tt, ff, ss) of the resistor of the MOS transistor; for the same input voltage, as shown in fig. 5 (d), taking vin=1.3v as an example, vout= 1.3046V corresponding to the standard process angle (MOS transistor: tt, resistor: tt), and output voltages corresponding to the other process angles are distributed between 1.2962V and 1.3132V, and the variation range is 0.017V.
As can be seen from comparison of the two, after compensation, the output change range caused by 15 process angle deviations is changed from 0.1423V to 0.017V.
Since the corresponding straight lines are approximately parallel at different process angles in the input-output characteristics, the above-described variation range is considered to be applicable to other input voltages.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention.
Claims (5)
1. A voltage follower with process error compensation, the voltage follower comprising: the voltage follower main circuit, the compensation generating circuit and the reference current source; the compensation generating circuit is used for detecting the process angle change and outputting two compensation currents Ip and In which are equal In size and opposite In direction and correspond to the process angle change; the compensation current flows through a compensation resistor in the voltage follower main circuit to generate a compensation voltage, and the compensation voltage enables the output voltage and the input voltage of the voltage follower main circuit to be kept equal; the reference current source is used for generating a P-type first bias voltage, a P-type second bias voltage, an N-type first bias voltage and an N-type second bias voltage, transmitting the N-type first bias voltage and the N-type second bias voltage to the compensation generating circuit, providing N-type current bias for the compensation generating circuit, transmitting the P-type first bias voltage, the P-type second bias voltage, the N-type first bias voltage and the N-type second bias voltage to the voltage follower main circuit, and providing P-type current bias and N-type current bias for the voltage follower main circuit.
2. The self-contained process error compensated voltage follower of claim 1 wherein the compensation generating circuit comprises: PMOS tube MP3-MP17, NMOS tube MN3-MN21 and resistors R1-R4; the source of the PMOS tube MP3, the source of the PMOS tube MP4, the source of the PMOS tube MP5, the source of the PMOS tube MP6, the source of the PMOS tube MP7, the source of the PMOS tube MP9, one end of the resistor R3, the source of the PMOS tube MP11, the source of the PMOS tube MP12, the source of the PMOS tube MP13, the source of the PMOS tube MP14 and the source of the PMOS tube MP16 are connected with a power supply together; The source of the NMOS tube MN3, the source of the NMOS tube MN7, one end of a resistor R1, the source of the NMOS tube MN10, the source of the NMOS tube MN12, one end of a resistor R4, the source of the NMOS tube MN16, one end of a resistor R2, the source of the NMOS tube MN19 and the source of the NMOS tube MN21 are grounded together; the grid electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP3, the drain electrode of the NMOS tube MN3, the grid electrode of the NMOS tube MN3 and the grid electrode of the NMOS tube MN4, the grid electrode of the PMOS tube MP4 is connected with the grid electrode of the PMOS tube MP5, the drain electrode of the PMOS tube MP4 and the drain electrode of the NMOS tube MN4, and the drain electrode of the PMOS tube MP5 is connected with the drain electrode of the NMOS tube MN5 and the grid electrode of the NMOS tube MN 8; The grid electrode of the NMOS tube MN5 is connected with the source electrode of the NMOS tube MN8 and the other end of the resistor R1, the source electrode of the NMOS tube MN4 is connected with the source electrode of the NMOS tube MN5 and the drain electrode of the NMOS tube MN6, the source electrode of the NMOS tube MN6 is connected with the drain electrode of the NMOS tube MN7, the grid electrode of the PMOS tube MP6 is connected with the grid electrode of the PMOS tube MP7, the grid electrode of the PMOS tube MP9, the drain electrode of the PMOS tube MP6 and the drain electrode of the NMOS tube MN8, the drain electrode of the PMOS tube MP7 is connected with the source electrode of the PMOS tube MP8, The drain electrode of the PMOS tube MP9 is connected with the source electrode of the PMOS tube MP10, the grid electrode of the PMOS tube MP8, the drain electrode of the NMOS tube MP8, the grid electrode of the NMOS tube MN9, the grid electrode of the NMOS tube MN11 and the drain electrode of the NMOS tube MN9 are connected together, the source electrode of the NMOS tube MN9 is connected with the drain electrode of the NMOS tube MN10, the grid electrode of the NMOS tube MN10 and the grid electrode of the NMOS tube MN12, the source electrode of the NMOS tube MN11 is connected with the drain electrode of the NMOS tube MN12, the other end of the resistor R3 is connected with the other end of the resistor R4 and the grid electrode of the NMOS tube MN13, The grid electrode of the PMOS tube MP11 is connected with the grid electrode of the PMOS tube MP12, the drain electrode of the PMOS tube MP11 and the drain electrode of the NMOS tube MN13, the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN14 and the grid electrode of the NMOS tube MN17, the grid electrode of the NMOS tube MN14 is connected with the source electrode of the NMOS tube MN17 and the other end of the resistor R2, the source electrode of the NMOS tube MN13 is connected with the source electrode of the NMOS tube MN14 and the drain electrode of the NMOS tube MN15, the source electrode of the NMOS tube MN15 is connected with the drain electrode of the NMOS tube MN16, The grid electrode of the PMOS tube MP13 is connected with the grid electrode of the PMOS tube MP14, the grid electrode of the PMOS tube MP16, the drain electrode of the PMOS tube MP13 and the drain electrode of the NMOS tube MN17, the drain electrode of the PMOS tube MP14 is connected with the source electrode of the PMOS tube MP15, the drain electrode of the PMOS tube MP16 is connected with the source electrode of the PMOS tube MP17, the grid electrode of the PMOS tube MP15 is connected with the grid electrode of the PMOS tube MP17, the drain electrode of the NMOS tube MP15, the grid electrode of the NMOS tube MN18, the grid electrode of the NMOS tube MN20 and the drain electrode of the NMOS tube MN18, The source electrode of the NMOS tube MN18 is connected with the drain electrode of the NMOS tube MN19, the grid electrode of the NMOS tube MN19 and the grid electrode of the NMOS tube MN21, and the source electrode of the NMOS tube MN20 is connected with the drain electrode of the NMOS tube MN 21; The grid electrode of the NMOS tube MN7 and the grid electrode of the NMOS tube MN16 are connected with the N-type first bias voltage, and the grid electrode of the NMOS tube MN6 and the grid electrode of the NMOS tube MN15 are connected with the N-type second bias voltage; the drain of NMOS tube MN11 and the drain of PMOS tube MP17 generate compensation current In, and the drain of PMOS tube MP10 and the drain of NMOS tube MN20 generate compensation current Ip.
3. The self-contained process error compensated voltage follower of claim 2 wherein the voltage follower main circuit comprises: PMOS tube MP0-MP2, NMOS tube MN0-MN2 and resistor R0; the source electrode of the PMOS tube MP0 and the drain electrode of the NMOS tube MN0 are connected with a power supply together, and the drain electrode of the PMOS tube MP2 and the source electrode of the NMOS tube MN2 are grounded together; the drain electrode of the PMOS tube MP0 is connected with the source electrode of the PMOS tube MP1, and the drain electrode of the PMOS tube MP1 is connected with the source electrode of the PMOS tube MP2, one end of the resistor R0 and the compensation current In; the drain electrode of the NMOS tube MN2 is connected with the source electrode of the NMOS tube MN1, and the grid electrode of the NMOS tube MN0 is connected with the other end of the resistor R0 and the compensation current Ip; the grid electrode of the NMOS tube MN1 is connected with the N-type second bias voltage, and the grid electrode of the NMOS tube MN2 is connected with the N-type first bias voltage; the grid electrode of the PMOS tube MP1 is connected with the P-type second bias voltage, and the grid electrode of the PMOS tube MP0 is connected with the P-type first bias voltage; the grid electrode of the PMOS tube MP2 is connected with an input voltage Vin, and the source electrode of the NMOS tube MN0 and the drain electrode of the NMOS tube MN1 are used for outputting a voltage Vout.
4. The self-contained process error compensated voltage follower of claim 1 wherein the reference current source comprises: PMOS tube MP18-MP27, NMOS tube MN22-MN29 and resistor R5; the source of the PMOS transistor MP18, the source of the PMOS transistor MP20, the source of the PMOS transistor MP22, the source of the PMOS transistor MP24, and the source of the PMOS transistor MP26 are connected to a power supply, and the source of the NMOS transistor MN23, the source of the NMOS transistor MN25, the source of the NMOS transistor MN26, the lower end of the resistor R5, and the source of the NMOS transistor MN29 are grounded; the grid electrode of the PMOS tube MP18 is connected with the drain electrode of the PMOS tube MP18 and the source electrode of the PMOS tube MP19 to generate a P-type first bias voltage; the grid electrode of the PMOS tube MP19 is connected with the drain electrode of the PMOS tube MP19 and the drain electrode of the NMOS tube MN22 to generate a P-type second bias voltage; the source electrode of the NMOS tube MN22 is connected with the drain electrode of the NMOS tube MN23, the grid electrode of the NMOS tube MN22 is connected with the grid electrode of the NMOS tube MN24, the drain electrode of the NMOS tube MN24 and the drain electrode of the PMOS tube MP21, and the grid electrode of the NMOS tube MN23 is connected with the grid electrode of the NMOS tube MN25, the drain electrode of the NMOS tube MN25 and the source electrode of the NMOS tube MN 24; the drain electrode of the PMOS tube MP20 is connected with the source electrode of the PMOS tube MP21, the grid electrode of the PMOS tube MP20 is connected with the grid electrode of the PMOS tube MP22, the grid electrode of the PMOS tube MP24, the drain electrode of the PMOS tube MP24, the grid electrode of the PMOS tube MP26 and the source electrode of the PMOS tube MP25, the grid electrode of the PMOS tube MP21 is connected with the grid electrode of the PMOS tube MP23, the grid electrode of the PMOS tube MP25, the grid electrode of the PMOS tube MP27 and the drain electrode of the NMOS tube MN27, the drain electrode of the PMOS tube MP22 is connected with the source electrode of the PMOS tube MP23, the drain electrode of the NMOS tube MN26 and the grid electrode of the NMOS tube MN27 are connected together, the source electrode of the NMOS tube MN27 is connected with one end of the resistor R5, and the drain electrode of the PMOS tube MP26 is connected with the source electrode of the PMOS tube MP 27; the drain electrode of the PMOS tube MP27 is connected with the grid electrode of the NMOS tube MN28 and the drain electrode of the NMOS tube MN28 to generate an N-type second bias voltage, and the source electrode of the NMOS tube MN28 is connected with the grid electrode of the NMOS tube MN29 and the drain electrode of the NMOS tube MN29 to generate an N-type first bias voltage.
5. A voltage following method based on a self-contained process error compensated voltage follower according to any of claims 1 to 4, characterized in that it comprises the following specific steps:
the compensation generating circuit is used for detecting the process angle change and outputting two compensation currents Ip and In which are equal In size and opposite In direction and correspond to the process angle change, the compensation current Ip is generated by the PMOS tube MP10 and the NMOS tube MN20, the compensation current In is generated by the PMOS tube MP17 and the NMOS tube MN11, and the magnitudes of the compensation currents Ip and In are as follows:
，
In the method, in the process of the invention, The current through resistors R1 and R2 respectively,For the gate voltage of NMOS transistor MN4,The gate voltage of the NMOS transistor MN 13;
In the main circuit of the voltage follower, a compensation resistor R0 is introduced, compensation current Ip flows In from one end of the R0, compensation current In flows In from the other end of the R0, and as Ip is equal to In, the current values of other MOS tubes In the circuit cannot change, the original working state of the circuit is unchanged, so that the compensation resistor R0 is equal to a resistor R1 and a resistor R2, a resistor R3 is equal to a resistor R4, the following from an input voltage to an output voltage is realized, the output voltage is not influenced by the process angle change, namely, the voltage change from Vin to Vout satisfies the following conditions:
，
In the method, in the process of the invention, Is the voltage difference between the source electrode and the grid electrode of the PMOS tube MP2,As the voltage difference between the gate and source of NMOS transistor MN0,To compensate for the voltage drop across resistor R0,AndThreshold voltages of all PMOS tubes and all NMOS tubes respectively, andIs a negative value, and is a positive value,Positive values.
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| JPH0520889A (en) * | 1991-03-01 | 1993-01-29 | Yokogawa Electric Corp | Track hold circuit |
| JPH07146727A (en) * | 1993-11-24 | 1995-06-06 | Nec Corp | Low-voltage reference voltage generation circuit |
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