CN116938235A - Digital conversion method of LVDT/RVDT signals - Google Patents
Digital conversion method of LVDT/RVDT signals Download PDFInfo
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Abstract
The invention discloses a digital conversion method of LVDT/RVDT signals, which comprises the following steps that a signal conditioning circuit receives linear displacement/linear rotation signals, and carries out signal conditioning on the signals to convert the signals into standard sine signals with effective values of 2V; analog theta and digital angle determined by standard sine signal through error detection circuitComparing to generate an error voltage; the error voltage signal generated by the error detection circuit is further amplified by an error amplifying circuit; determining the phase of an alternating current error signal according to the phase of a reference voltage through a phase-sensitive rectifying circuit, and performing full-wave rectification to obtain a direct current error voltage signal with positive and negative polarities; and an integrating link is connected in series in the tracking loop through the integrating circuit, so that the order of the error degree of the tracking loop is improved. The invention adopts a second-order tracking methodThe highest 14-bit resolution and linearity are realized, the conversion accuracy is not more than 0.2 per mill, and the conversion accuracy is not more than + -5 LSB and Wen Piao ppm/DEG C.
Description
Technical Field
The invention belongs to the field of analog signal to digital conversion, and particularly relates to a digital conversion method of an LVDT/RVDT signal.
Background
The LVDT/RVDT sensor is used for detecting angle, elongation, vibration frequency, vibration amplitude, object thickness degree and expansion degree, is suitable for various automatic control and automatic measurement systems, and is mainly applied to the fields of machinery, electric power, electronics, automobiles, aerospace, metallurgy, coal, petroleum, traffic, light industry, textile, building materials, water conservancy and the like. The output signal of the LVDT/RVDT sensor is an analog quantity, a digital processor cannot directly process the output signal, the signal type of the LVDT/RVDT sensor needs to be converted, and the currently commonly used digital conversion method of the LVDT/RVDT signal generally comprises the steps of comparing, filtering and amplifying the input and output signal of the LVDT/RVDT sensor, converting the input and output signal into a direct-current voltage quantity, and then converting the direct-current voltage quantity into a digital quantity through D/A conversion. This conversion method has the following disadvantages: the conversion method is subjected to secondary conversion, and the conversion accuracy is low; the conversion method is open loop control, has no feedback link, and has low conversion accuracy and large temperature drift.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the digital conversion method of the LVDT/RVDT signal, which has the advantages of reasonable design, high resolution, high precision, good linearity and small temperature drift.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a digital conversion method of LVDT/RVDT signals is characterized in that the digital conversion method comprises the following steps,
(1) The signal conditioning circuit receives a linear displacement/linear rotation signal with the voltage of more than 2Vrms and the frequency of 50 Hz-8 kHz, and conditions the signal to convert the signal into a standard sinusoidal signal with the effective value of 2V;
(2) Analog theta determined by standard sine signal with effective value of 2V and digital angle output by reversible counter through error detection circuitComparing to generate an error voltage;
(3) The error voltage signal generated by the error detection circuit is further amplified by an error amplifying circuit;
(4) Determining the phase of an alternating current error signal according to the phase of a reference voltage through a phase-sensitive rectifying circuit, and performing full-wave rectification to obtain a direct current error voltage signal with positive and negative polarities;
(5) An integrating link is connected in series in the tracking loop through an integrating circuit, so that the order of the error degree of the tracking loop is improved;
(6) Generating clock pulse according to the magnitude of the input DC error voltage by a voltage-controlled oscillator, outputting digital angle by a reversible counterAs an integral of the output frequency of the voltage controlled oscillator with respect to time, the frequency of the voltage controlled oscillator is proportional to the input control voltage.
The technical problem to be solved by the invention can also be realized by the following technical scheme that in the step (1), the signal conditioning process is that after the addition and subtraction operation is carried out on linear displacement/linear rotation signals such as three-wire/two-wire LVDT/RVDT signals by an operational amplifier, standard sine signals with the maximum effective value of 2V are output; the signal conditioning input and output relationships are as follows:
V A ，V B ——V A ，V B the induced voltage value generated for the LVDT or RVDT sensor;
V Anull ,V Bnull ——V A and V is equal to B Voltage values at equal time;
SIN, COS-standard sine signal after regulating by the regulating circuit;
for signal V A Sum signal V B Performs addition operation, and finally outputs sum voltage (V A +V B ) The effective value of the proportional relation is 2Vrms of the reference signal.
The technical problem to be solved by the invention can also be realized by the following technical proposal, the working process of the error detection circuit in the step (2) is that,
the analog angle theta angle A theta Sin omega t (wherein theta is more than or equal to 0 DEG and less than or equal to 90 DEG) and the digital angle phi are subjected to difference to obtain an error signal A (theta-phi) Sin omega t output,
when the angle theta-phi is less than or equal to 0.0027 DEG, the analog angle theta and the digital angle phi are approximately equal in the error range, and the loop is in a stable state; when |theta-phi| > 0.0027 DEG, the digital angle phi will change until |theta-phi| < 0.0027 DEG is satisfied;
wherein the digital angleThe high 2 bits (Bit 1 and Bit 2) of (1) are used as overflow indication signals, the conversion circuit normally works in the first quadrant, namely the Bit1 and the Bit2 are both in low level, when the input signal exceeds the normal range, the conversion circuit works in one of the second quadrant or the third quadrant or the fourth quadrant, and at the moment, the Bit1 and the Bit2 signals must have one high level; therefore, the high and low levels of Bit1 and Bit2 can be used to characterize whether the input LVDT/RVDT signal is out of normal range.
The technical problem to be solved by the invention can also be realized by the following technical proposal that the output form of the error signal is voltage, namely
K in the formula 1 For the sensitivity of the comparator, θ is the analog angle determined by the standard sine and cosine signal,for the digital angle in the reversible counter,
the transfer function of the circuit is as follows:
the technical problem to be solved by the invention can be realized by the following technical scheme, and the transfer function of the error amplifying circuit in the step (3) is as follows:
wherein: u (U) i An error voltage output by the comparator; u (U) o Outputting a voltage for the amplifying circuit; the transfer coefficient of the alternating current amplifier is K 2 The dimension is the output voltage value of each microampere, R is taken 3 =150kΩ, then K 2 ＝0.15V/μA。
The technical problem to be solved by the invention can be realized by the following technical scheme, and the transfer function of the phase-sensitive demodulation link in the step (4) is as follows: w (W) 3 (s)＝K 3 ＝0.9。
The technical problem to be solved by the invention can be realized by the following technical scheme, and the transfer function of the integrating circuit in the step (5) is as follows:
wherein the integrating circuit gain isThe integration link adopts an active network, and has +.>Amplified and inverted by a factor of two.
The technical problem to be solved by the invention can be realized by the following technical scheme, and the transfer function of the voltage controlled oscillator in the step (6) is as follows:
wherein 1.25V is the threshold voltage of the comparator in the voltage-controlled oscillator, A 2 Sensitivity for voltage controlled oscillators:
the technical problem to be solved by the invention can be realized by the following technical scheme that the circuit for realizing the digital conversion method consists of a signal conditioning circuit, an error detection circuit, an error amplifying circuit, a phase-sensitive rectifying circuit, an integrating circuit, a voltage-controlled oscillator and a reversible counter, and a complete second-order tracking loop is formed by the error detection circuit, the error amplifying circuit, the phase-sensitive rectifying circuit, the voltage-controlled oscillator and the reversible counter;
the technical problem to be solved by the invention can also be realized by the following technical scheme that the signal conditioning circuit comprises a three-wire LVDT/RVDT signal conditioning circuit and a two-wire LVDT/RVDT signal conditioning circuit, wherein the three-wire LVDT/RVDT signal conditioning circuit and the two-wire LVDT/RVDT signal conditioning circuit are respectively provided with an operational amplifier N1, an operational amplifier N3 and an operational amplifier N2 and an operational amplifier N4 for adding signals;
the error detection circuit comprises a quadrant switch, a reversible counter and a multiplication type D/A converter, wherein the input end of the quadrant switch is respectively connected with the output end of the signal conditioning circuit and the output end of the reversible counter, the output end of the quadrant switch is connected with the input end of the multiplication type D/A converter,
the error amplifying circuit is composed of an operational amplifier A1, an operational amplifier A2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a voltage-stabilizing diode BG1 and a voltage-stabilizing diode BG2, wherein the operational amplifier A1, the resistor R2, the capacitor C1 and the operational amplifier A2 are connected in series, the resistor R1 is connected with the operational amplifier A1 in parallel, the resistor R3, the capacitor C2 is connected with the operational amplifier A2 in parallel, and the voltage-stabilizing diode BG1 and the voltage-stabilizing diode BG2 are connected in series and then connected in parallel on a circuit between the capacitor C1 and the operational amplifier A2;
the phase-sensitive rectifying circuit is composed of an operational amplifier A3, a resistor R4, a resistor R5, a capacitor C3, a CMOS switch and a switch driver, wherein the resistor R4, the operational amplifier A3 and the CMOS switch are connected in series, the resistor R5 and the capacitor C3 are connected with the operational amplifier A3 in parallel, the switch driver is connected with the CMOS switch, and the switch driver receives a reference signal;
the integrating circuit consists of a resistor R6, a resistor R7, a capacitor C4, a capacitor C5 and an operational amplifier A4, wherein the resistor R6 is connected with the operational amplifier A4 in series, and the resistor R7 is connected with the capacitor C4 in series and then connected with the capacitor C5 and the operational amplifier A4 in parallel;
the voltage-controlled oscillator is provided with a charge-discharge circuit and a control circuit, the charge-discharge circuit is composed of a resistor R8, an operational amplifier A5, an operational amplifier A6, a capacitor C6 and a capacitor C7, one end of the resistor R8 is connected with the integrating circuit, the other end of the resistor R8 is connected with the negative input end of the operational amplifier A5, the output end of the operational amplifier A5 is connected with the input end of the control circuit, the output end of the operational amplifier A5 is also connected with a switch K2 through the capacitor C6, the positive input end of the operational amplifier A6 is connected with the negative input end of the operational amplifier A6, the output end of the operational amplifier A6 is connected with the control circuit through a switch K1, the circuit between the switch K1 and the switch K2 is connected with one end of the switch K3 through the capacitor C7, and the other end of the switch K3 is connected with the S2 port of the control circuit.
The technical problem to be solved by the invention can be also realized by the following technical scheme that the working process of the voltage-controlled oscillator is that,
the false zero detection signal and the TP digital control signal are transmitted to the control circuit, the digital control signal is input, the voltage-controlled oscillator does not oscillate when the high voltage is applied, the false zero detection signal generates pulses when the false zero occurs, so that the voltage-controlled oscillator oscillates, the occurrence of the false zero phenomenon is avoided, and the DIR direction signal output end and the control circuit are arranged on the control circuitEnd (S)>The end provides a clock for the counter;
the TP position number control signal and the false zero detection signal can both change the control signal S1 to control the oscillation of the oscillator, and when the TP position number control signal and the false zero detection signal are invalid, the control circuit is arranged in the operational amplifier A 5 When the output voltage is greater than V+ or less than V-, S1 is enabled to output a pulse with the width fixed to 1 clk period, and the control oscillator is enabled to discharge and the discharge time is controlled;
in the charged state, K 1 Closing, K 2 Disconnection, K 3 Selection and U e Polarity-dependent, speed voltage positive K 3 Selecting V-, K when the speed voltage is negative 3 Selecting V+ to make capacitor C 7 Pre-charging; capacitor C 6 Charging according to the speed voltage of the error voltage, wherein the charging time is in direct proportion to the speed voltage; resistor R 8 Adjusting the charging time;
when the capacitor C 6 When the charging voltage reaches a preset value, the charging voltage enters a discharging state; the control circuit makes K1 open, K2 closed, K 3 Selection and U e Polarity-dependent, speed voltage positive K 3 Selecting K when the velocity voltage is negative 3 Selecting V-, accelerating capacitor C 7 Discharging and charging processes; capacitor C 6 The charge will be equal to the capacitance C 7 The charge in (a) is counteracted and the rest is charged into the capacitor C 7 . Capacitor C 6 The upper voltage is lower than a preset value, and the circuit enters a charging state.
Compared with the prior art, the invention forms a complete second-order tracking loop by arranging the error detection circuit, the error amplification circuit, the phase-sensitive rectifying circuit, the voltage-controlled oscillator and the reversible counter, and adopts a second-order tracking method to realize digital conversion of LVDT/RVDT signals, and has the characteristics of closed loop, high conversion precision, good linearity, good stability, small temperature drift, high reliability and the like. The method can realize the highest 14-bit resolution, the linearity of less than or equal to 0.2 per mill, the conversion precision of less than or equal to +/-5 LSB and Wen Piao ppm/DEG C.
Drawings
Figure 1 is a block diagram of an LVDT/RVDT signal to digital conversion circuit;
figure 2 is a three wire LVDT/RVDT signal conditioning circuit;
FIG. 3 is a two-wire LVDT/RVDT signal conditioning circuit;
FIG. 4 is a graph of input versus output for a signal conditioning circuit;
FIG. 5 is a diagram of an error detection circuit;
FIG. 6 is an error amplifying circuit diagram;
FIG. 7 is a phase sensitive rectifying circuit diagram;
FIG. 8 is an integrating circuit diagram;
FIG. 9 is a voltage controlled oscillator charge-discharge circuit;
FIG. 10 is a voltage controlled oscillator control circuit;
FIG. 11 is a timing diagram of a clock generation circuit;
FIG. 12 is a timing diagram of a delay circuit;
FIG. 13 is a block diagram of an integrator circuit transfer function;
FIG. 14 is a block diagram of an integration-link transfer function;
fig. 15 is a circuit diagram of an integration section.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
In the description of the present invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The LVDT/RVDT signal to digital conversion method includes signal conditioning circuit, error detecting circuit, error amplifying circuit, phase-sensitive rectifying circuit, integrating circuit, voltage controlled oscillator and reversible counter.
1. Signal conditioning circuit
The signal conditioning circuit receives three-wire or two-wire LVDT/RVDT signals, the voltage range of the receivable signals is 2 Vrms-115 Vrms, and the receivable frequency range is 50 Hz-8 kHz. The converter needs to be subjected to signal conditioning before error processing, and the LVDT/RVDT signals with different signal amplitudes are converted into sine signals with the amplitude of 2Vrms at maximum, which are convenient for the subsequent error detection circuit to process.
The three-wire LVDT/RVDT signal conditioning circuit is shown in FIG. 2. After the three-wire LVDT/RVDT signal is subjected to addition and subtraction operation by the operational amplifier, a standard sine signal with the maximum amplitude of 2V is output, and the signal V can be realized by the operational amplifier N2 A Sum signal V B And finally outputs a sum voltage (V A +V B ) The effective value of the proportional relation is 2Vrms of the reference signal. The signal conditioning front-to-back relationship is as follows:
wherein:
V A ，V B ——V A ，V B the induced voltage value generated for the LVDT or RVDT sensor;
V Anull ,V Bnull ——V A and V is equal to B Voltage values at equal time;
SIN, COS-standard voltage regulated by the conditioning circuit.
The two-wire LVDT/RVDT signal conditioning circuit is shown in FIG. 3, the circuit principle is similar to that of a three-wire LVDT/RVDT signal conditioning circuit, and the signal conditioning relation is as follows:
wherein:
V A ，V B ——V A ，V B the induced voltage value generated for the LVDT or RVDT sensor;
V Anull ,V Bnull ——V A and V is equal to B Voltage values at equal time;
SIN, COS-standard voltage regulated by the conditioning circuit.
Fig. 4 shows the input signal versus output signal of the signal conditioning circuit.
2. Error detection circuit
A specific implementation of the error detection circuit is shown in fig. 5. Wherein the output form of the error detection circuit is voltage, i.eK in the formula 1 For the sensitivity of the comparator, θ is the analog angle determined by the standard sine and cosine signal, ++>For the digital angle in the reversible counter, the upper 2 bits (Bit 1 and Bit 2) are applied to the quadrant selection switch, and the conversion circuit normally operates in the first quadrant, i.e. Bit1 and Bit2 are both low, and the rest (Bit 3-Bit 16) is supplied to the digital input of the multiplication D/A.
When the loop is in the tracking stateThe above can thus be written as:
the input and output of the link are voltage quantity, and the feedback quantity is LSB, so that the transfer function of the error processing part is as follows:
in the above, the denominator is determined by the number of bits of the subdivision circuit, and when the number of bits is different, the controllable amplifying links of the comparing, amplifying and phase-sensitive links make corresponding compensation, so that the K value is certain.
3. Error amplifying circuit
The specific implementation of the error amplifying circuit is shown in fig. 6. A first-stage amplifier is arranged between the error detection and execution element, so that the closed loop system has high enough sensitivity to meet the design value of an ideal transfer function, namely, the required open loop amplitude-phase characteristic, closed loop step response and stability requirements of the system.
When θ is at the first quadrant, the actual current direction is as in fig. 6 at the positive peak interval of the reference signal. I out1 And I out2 The former flows in and the latter flows out. If I out1 ≠I out2 Then I out1 And I out2 The difference value is passed through capacitor C 18 Coupled to, flow through R 3 Obtaining an output current U O 。
Since the error voltage is ac, a dc blocking capacitive coupling may be used to isolate the dc component. C (C) 2 For A 2 Is stable.
Voltage stabilizing diode BG 1 And BG 2 The respective voltage stabilizing value is 4.7V, which is used for protecting the CMOS switch. Because the subsequent connection of the ac amplifier to the phase sensitive rectifying circuit is implemented by a CMOS "single pole double throw" switch. The power supply voltage of the CMOS is +/-6.8V, and the signal voltage needs to be ensured not to exceed the power supply voltage at any time.
The transfer function of the error amplifying circuit is as follows:
wherein:
U i -an error voltage output by the comparator;
U 0 -amplifying the circuit output voltage.
The transfer coefficient of the alternating current amplifier is K 2 The dimension is the output voltage value per microampere. R is taken 3 =150kΩ, then
K 2 ＝1μA×150KΩ/μA＝150mV/μA＝0.15V/μA
4. Phase-sensitive rectifying circuit
The phase-sensitive rectifying circuit is embodied in fig. 7. The phase-sensitive link determines the phase of the alternating current error according to the phase of the reference voltage, and full-wave rectification is carried out to obtain the direct current error voltage with positive and negative polarities.
AC amplifier A 2 The output AC error voltage is directly applied to the single-pole double-throw CMOS switchAnd the end A is subjected to inverting operation and amplification to obtain an inverted voltage with the phase difference of 180 DEG, and the inverted voltage is added to the end B. The C terminal is controlled by the combination of the 180 DEG sign bit and the reference signal, and is connected to the A terminal and the B terminal according to the excitation power frequency. The reference signal is a control square wave of the same frequency as the ac error signal. If the sign bit 180 DEG and the reference signal are combined for a positive half cycle to connect C to A, then the negative half cycle must have C connected to B, and the waveform at C point is a positive full wave rectified voltage waveform. Changing the input error voltage phase 180 deg., or changing the sign bit of 180 deg., will become a negative waveform.
Let the error voltage be V e1 ＝V em Sin ωt, i.e. V e2 ＝V em ·sin(ωt+π)
The average value is as follows:
thus, the transfer function of the phase sensitive demodulation element is: w (W) 3 (s)＝K 3 ＝0.9。
I.e. the dc average value of the phase sensitive rectified output is 0.9 times the effective value of the ac error voltage.
5. Integrating circuit
The specific implementation of the integrating circuit is shown in fig. 8. Circuit routing operational amplifier A 4 Resistance R 6 、R 7 Capacitor C 4 、C 5 Composition is prepared.
Referring to fig. 13, the integrating circuit transfer function is:
order theC 1 ＝10C 2 ＝C BW ，R 2 ＝R b ，/>Then
Wherein the integrating circuit gain is
As can be seen from the above: the integration link has direct current due to the adoption of an active networkThe amplification and phase inversion of the power are multiplied, and the capacitor C4 and the resistor R7 form an RC serial network to have a correction effect on the tracking loop.
The series integration link in the tracking loop can improve the "order" of the error degree of the loop. I.e. the tracking loop of the first order becomes a second order, i.e. a tracking loop without speed error, after being strung into an integration link.
6. Voltage controlled oscillator
Wherein the voltage controlled oscillator can generate clock pulses according to the magnitude of the input dc error voltage. The output voltage of the integrating circuit formed by the voltage-controlled oscillator and the reversible counter is the integral of the charging current generated by the input voltage through the input resistor to the integrating capacitor. Digital angle in reversible counterIs the integral of the voltage controlled oscillator output frequency with time, and the voltage controlled oscillator frequency is proportional to the input control voltage. The voltage controlled oscillator together with the up-down counter thus constitutes an integration stage, as shown in fig. 14 and 15.
Wherein due to outputSince the integration of the voltage-controlled oscillator output frequency f with respect to time is:
due to conservation of charge during charge and discharge:
substituting the above formula, the following can be obtained:
wherein 1.25V is the threshold voltage of the comparator in the controlled oscillator, A 2 Sensitivity for voltage controlled oscillators:
i.e. the input voltage of the voltage-controlled oscillator changes by 1V, the output changes
The voltage-controlled oscillator mainly comprises a charge-discharge part and a control part.
The voltage-controlled oscillator charge-discharge section is embodied in fig. 9. Wherein C is 6 50pF, C 7 25pF. V.+ -. 1.25V. TP is a set-point control signal, and is the voltage-controlled oscillator does not oscillate when high. The false zero detection signal generates pulses when the false zero occurs, so that the voltage-controlled oscillator oscillates, and the occurrence of the false zero phenomenon is avoided. The DIR is the direction signal output and,a clock is provided for the counter.
In the charged state, K 1 Closing, K 2 Disconnection, K 3 Selection and U e Polarity-dependent, speed voltage positive K 3 Selecting V-, K when the speed voltage is negative 3 Selecting V+ to make capacitor C 7 And (5) precharging. Capacitor C 6 According to errorThe speed voltage of the differential voltage is charged, and the charging time is proportional to the speed voltage. Resistor R 8 The charging time may be adjusted.
When the capacitor C 6 And when the charging voltage reaches a preset value, entering a discharging state. The control circuit makes K1 open, K2 closed, K 3 Selection and U e Polarity-dependent, speed voltage positive K 3 Selecting K when the velocity voltage is negative 3 Selecting V-, accelerating capacitor C 7 Discharge and charge processes. Capacitor C 6 The charge will be equal to the capacitance C 7 The charge in (a) is counteracted and the rest is charged into the capacitor C 7 . Capacitor C 6 The upper voltage is lower than a preset value, and the circuit enters a charging state. The above process enables the whole circuit to complete charging and discharging.
The voltage controlled oscillator control electronics is shown in fig. 10. In the figure, clk is a reference clock, and the output A5 is the output A5 in fig. 9. V.+ -. 1.25V. TP and the false zero detection signal can change the control signal S1 to control the oscillation of the controlled oscillator. When TP and false zero detection signals are invalid, the control circuit is in A 5 When the output voltage is greater than V+ or less than V-, S1 is enabled to output a pulse with the width fixed to 1 clk period, and the control oscillator is enabled to discharge and control the discharge time. The clock generation circuit timing diagram is shown in fig. 11.
The delay circuit timing diagram is shown in fig. 12, where the signal at point b is delayed to point R by a nor gate and an inverter than the signal directly to point S1. This part of the circuit is kept active.
S1 is exclusive-or with DIR after inversion, so that the switch K3 is ensured to change along with the polarity difference of the input error voltage Ue. Wherein the counter is a digit controllable 16-bit reversible counter,a clock is provided for the counter. The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.
Claims (10)
1. A digital conversion method of LVDT/RVDT signal is characterized in that the digital conversion method comprises the following steps,
(1) The signal conditioning circuit receives a linear displacement/linear rotation signal with the voltage of more than 2Vrms and the frequency of 50 Hz-8 kHz, and conditions the signal to convert the signal into a standard sinusoidal signal with the effective value of 2V;
(2) The error detection circuit is used for determining the analog theta determined by the standard sinusoidal signal with the effective value of 2V and the digital angle output by the reversible counterComparing to generate an error voltage;
(3) The error voltage signal generated by the error detection circuit is further amplified by an error amplifying circuit;
(4) Determining the phase of an alternating current error signal according to the phase of a reference voltage through a phase-sensitive rectifying circuit, and performing full-wave rectification to obtain a direct current error voltage signal with positive and negative polarities;
(5) An integrating link is connected in series in the tracking loop through an integrating circuit, so that the order of the error degree of the tracking loop is improved;
(6) Generating clock pulse according to the magnitude of the input DC error voltage by a voltage-controlled oscillator, outputting digital angle by a reversible counterAs an integral of the output frequency of the voltage controlled oscillator with respect to time, the frequency of the voltage controlled oscillator is proportional to the input control voltage.
2. The digital conversion method of LVDT/RVDT signal according to claim 1, wherein in step (1), the signal conditioning process is that after the addition and subtraction of linear displacement/linear rotation signals such as three-wire/two-wire LVDT/RVDT signals by operational amplifier, the standard sine signal with the maximum effective value of 2V is output; the signal conditioning input and output relationships are as follows:
wherein:
V A ，V B ——V A ，V B the induced voltage value generated for the LVDT or RVDT sensor;
V Anull ,V Bnull ——V A and V is equal to B Voltage values at equal time;
SIN, COS-standard sine signal after regulating by the regulating circuit;
for signal V A Sum signal V B Adding, and finally outputting sum voltage V A +V B The effective value of the proportional relation is 2Vrms of the reference signal.
3. The method of claim 1, wherein the error detection circuit in step (2) is operated by,
the analog angle theta, theta Sinωt and the digital angle phi are differenced, wherein theta is more than or equal to 0 degree and less than or equal to 90 degrees, the error signal A (theta-phi) Sinωt is obtained and output,
when the angle theta-phi is less than or equal to 0.0027 DEG, the analog angle theta and the digital angle phi are approximately equal in the error range, and the loop is in a stable state; when |theta-phi| > 0.0027 DEG, the digital angle phi will change until |theta-phi| < 0.0027 DEG is satisfied;
wherein the digital angleThe high 2 bits (Bit 1 and Bit 2) of (1) are used as overflow indication signals, the conversion circuit normally works in the first quadrant, namely the Bit1 and the Bit2 are both in low level, when the input signal exceeds the normal range, the conversion circuit works in one of the second quadrant or the third quadrant or the fourth quadrant, and at the moment, the Bit1 and the Bit2 signals must have one high level; therefore, the high and low levels of Bit1 and Bit2 can be used to characterize whether the input LVDT/RVDT signal is out of normal range.
4. A method for digital conversion of LVDT/RVDT signals according to claim 3, wherein said error detection signal is output in the form of a voltage
K in the formula 1 For the sensitivity of the comparator, θ is the analog angle determined by the standard sine and cosine signal,for the digital angle in the reversible counter,
the transfer function of the circuit is as follows:
5. the method of digital conversion of LVDT/RVDT signals according to claim 1, wherein the transfer function of the error amplifying circuit in step (3) is:
wherein: u (U) i An error voltage output by the comparator; u (U) o Outputting a voltage for the amplifying circuit; the transfer coefficient of the alternating current amplifier is K 2 The dimension is the output voltage value of each microampere, R is taken 3 =150kΩ, then K 2 ＝0.15V/μA。
6. The digital conversion method of LVDT/RVDT signals according to claim 1, wherein the transfer function of the phase sensitive demodulation step in step (4) is: w (W) 3 (s)＝K 3 ＝0.9。
7. The method of digital conversion of LVDT/RVDT signals according to claim 1, wherein in step (5) the integrating circuitThe transfer function is:
wherein the integrating circuit gain isThe integration link adopts an active network, and has +.>Amplified and inverted by a factor of two.
8. The method of digital conversion of LVDT/RVDT signals according to claim 1, wherein the transfer function of the voltage controlled oscillator in step (6) is:
wherein 1.25V is the threshold voltage of the comparator in the voltage-controlled oscillator, A 2 Sensitivity for voltage controlled oscillators:
9. the digital conversion method of LVDT/RVDT signal according to claim 1, wherein the circuit for realizing the digital conversion method is composed of a signal conditioning circuit, an error detection circuit, an error amplifying circuit, a phase-sensitive rectifying circuit, an integrating circuit, a voltage-controlled oscillator and a reversible counter, and a complete second-order tracking loop is composed of the error detection circuit, the error amplifying circuit, the phase-sensitive rectifying circuit, the voltage-controlled oscillator and the reversible counter;
the signal conditioning circuit comprises a three-wire LVDT/RVDT signal conditioning circuit and a two-wire LVDT/RVDT signal conditioning circuit, wherein the three-wire LVDT/RVDT signal conditioning circuit and the two-wire LVDT/RVDT signal conditioning circuit are respectively provided with an operational amplifier N1 and an operational amplifier N4 for adding and subtracting signals, an operational amplifier N2 for adding signals and an operational amplifier N3 for following signals;
the error detection circuit comprises a quadrant switch, a reversible counter and a multiplication type D/A converter, wherein the input end of the quadrant switch is respectively connected with the output end of the signal conditioning circuit and the output end of the reversible counter, and the output end of the quadrant switch is connected with the input end of the multiplication type D/A converter;
the error amplifying circuit is composed of an operational amplifier A1, an operational amplifier A2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a voltage-stabilizing diode BG1 and a voltage-stabilizing diode BG2, wherein the operational amplifier A1, the resistor R2, the capacitor C1 and the operational amplifier A2 are connected in series, the resistor R1 is connected with the operational amplifier A1 in parallel, the resistor R3, the capacitor C2 is connected with the operational amplifier A2 in parallel, and the voltage-stabilizing diode BG1 and the voltage-stabilizing diode BG2 are connected in series and then connected in parallel on a circuit between the capacitor C1 and the operational amplifier A2;
the phase-sensitive rectifying circuit is composed of an operational amplifier A3, a resistor R4, a resistor R5, a capacitor C3, a CMOS switch and a switch driver, wherein the resistor R4, the operational amplifier A3 and the CMOS switch are connected in series, the resistor R5 and the capacitor C3 are connected with the operational amplifier A3 in parallel, the switch driver is connected with the CMOS switch, and the switch driver receives a reference signal;
the integrating circuit consists of a resistor R6, a resistor R7, a capacitor C4, a capacitor C5 and an operational amplifier A4, wherein the resistor R6 is connected with the operational amplifier A4 in series, and the resistor R7 is connected with the capacitor C4 in series and then connected with the capacitor C5 and the operational amplifier A4 in parallel;
the voltage-controlled oscillator is provided with a charge-discharge circuit and a control circuit, the charge-discharge circuit is composed of a resistor R8, an operational amplifier A5, an operational amplifier A6, a capacitor C6 and a capacitor C7, one end of the resistor R8 is connected with the integrating circuit, the other end of the resistor R8 is connected with the negative input end of the operational amplifier A5, the output end of the operational amplifier A5 is connected with the input end of the control circuit, the output end of the operational amplifier A5 is also connected with a switch K2 through the capacitor C6, the positive input end of the operational amplifier A6 is connected with the negative input end of the operational amplifier A6, the output end of the operational amplifier A6 is connected with the control circuit through a switch K1, the circuit between the switch K1 and the switch K2 is connected with one end of the switch K3 through the capacitor C7, and the other end of the switch K3 is connected with the S2 port of the control circuit.
10. The method of claim 9, wherein the voltage controlled oscillator operates by,
the false zero detection signal and the TP digital control signal are transmitted to the control circuit, the digital control signal is input, the voltage-controlled oscillator does not oscillate when the high voltage is applied, the false zero detection signal generates pulses when the false zero occurs, so that the voltage-controlled oscillator oscillates, the occurrence of the false zero phenomenon is avoided, and the DIR direction signal output end and the control circuit are arranged on the control circuitEnd (S)>The end provides a clock for the counter;
the TP position number control signal and the false zero detection signal can both change the control signal S1 to control the oscillation of the oscillator, and when the TP position number control signal and the false zero detection signal are invalid, the control circuit is arranged in the operational amplifier A 5 When the output voltage is greater than V+ or less than V-, S1 is enabled to output a pulse with the width fixed to 1 clk period, and the control oscillator is enabled to discharge and the discharge time is controlled;
in the charged state, K 1 Closing, K 2 Disconnection, K 3 Selection and U e Polarity-dependent, speed voltage positive K 3 Selecting V-, K when the speed voltage is negative 3 Selecting V+ to make capacitor C 7 Pre-charging; capacitor C 6 Charging according to the speed voltage of the error voltage, wherein the charging time is in direct proportion to the speed voltage; resistor R 8 Adjusting the charging time;
when the capacitor C 6 When the charging voltage reaches a preset value, the charging voltage enters a discharging state; the control circuit makes K1 open, K2 closed, K 3 Selection and U e Polarity-dependent, speed voltage positive K 3 Selecting K when the velocity voltage is negative 3 Selecting V-, accelerating capacitor C 7 Discharging and charging processes; capacitance deviceC 6 The charge will be equal to the capacitance C 7 The charge in (a) is counteracted and the rest is charged into the capacitor C 7 Capacitance C 6 The upper voltage is lower than a preset value, and the circuit enters a charging state.
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