CN116932047A - Data transmission method, device, electronic equipment and readable storage medium - Google Patents

Data transmission method, device, electronic equipment and readable storage medium Download PDF

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Publication number
CN116932047A
CN116932047A CN202310891427.4A CN202310891427A CN116932047A CN 116932047 A CN116932047 A CN 116932047A CN 202310891427 A CN202310891427 A CN 202310891427A CN 116932047 A CN116932047 A CN 116932047A
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China
Prior art keywords
register
signal
clock
data transmission
back pressure
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CN202310891427.4A
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Inventor
陈鹏斌
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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Priority to CN202310891427.4A priority Critical patent/CN116932047A/en
Publication of CN116932047A publication Critical patent/CN116932047A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134Register stacks; shift registers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • G06F9/543User-generated data transfer, e.g. clipboards, dynamic data exchange [DDE], object linking and embedding [OLE]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/54Indexing scheme relating to G06F9/54
    • G06F2209/543Local

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

The application discloses a data transmission method, a data transmission device, electronic equipment and a readable storage medium, and belongs to the technical field of data transmission. The data transmission method is applied to a first register, the first register is connected with a second register and a third register, the second register is an upstream register of the first register, the third register is a downstream register of the first register, and the data transmission method comprises the following steps: acquiring a preset clock of a line blanking signal output by a first register; in the case that the first register receives the first target signal from the second register and the second target signal from the third register, the first register transmits a first back pressure signal to the second register according to a preset clock, so that the first register can output a line blanking signal of the preset clock to the third register.

Description

Data transmission method, device, electronic equipment and readable storage medium
Technical Field
The application belongs to the technical field of data transmission, and particularly relates to a data transmission method, a data transmission device, electronic equipment and a readable storage medium.
Background
Pipeline design is an indispensable implementation in chip design or FPGA (Field Programmable Gate Array, field-programmable gate array) design. The design of the pipeline refers to that a register is inserted into the combinational logic with larger delay, and the larger combinational logic is split into a plurality of clock cycles to finish the design, so that the maximum clock frequency of the system is improved.
In the related art, a pipeline for processing image data generally has functions of maintaining valid data and clearing bubbles, and the pipeline can take HBLANK (line blanking) data in the image data as bubble clearing, so that the HBLANK data is lost.
Disclosure of Invention
An object of an embodiment of the present application is to provide a data transmission method, apparatus, electronic device, and readable storage medium, which implement that a register of pipeline design can actively back-pressure to an upstream register, thereby regenerating a line blanking signal, and ensuring that the line blanking signal is not lost.
In a first aspect, an embodiment of the present application provides a data transmission method applied to a first register, where the first register is connected to a second register and a third register, the second register is an upstream register of the first register, and the third register is a downstream register of the first register, where the data transmission method includes: acquiring a preset clock of a line blanking signal output by a first register; in the case that the first register receives the first target signal from the second register and the second target signal from the third register, the first register transmits a first back pressure signal to the second register according to a preset clock, so that the first register can output a line blanking signal of the preset clock to the third register.
In a second aspect, an embodiment of the present application provides a data transmission device applied to a first register, where the first register is connected to a second register and a third register, the second register is an upstream register of the first register, and the third register is a downstream register of the first register, where the data transmission device includes: the acquisition module is used for acquiring a preset clock of a line blanking signal output by the first register; and the transmission module is used for transmitting a first back pressure signal to the second register according to the preset clock under the condition that the first register receives the first target signal from the second register and the second target signal from the third register, so that the first register can output a line blanking signal of the preset clock to the third register.
In a third aspect, embodiments of the present application provide an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, the program or instructions implementing the steps of the method as in the first aspect when executed by the processor.
In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor perform the steps of the method as in the first aspect.
In a fifth aspect, embodiments of the present application provide a chip comprising a processor and a communication interface coupled to the processor for running a program or instructions implementing the steps of the method as in the first aspect.
In a sixth aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement a method as in the first aspect.
In the embodiment of the application, when the first register detects the first target signal transmitted by the upstream second register and the second target signal transmitted by the downstream third register, the first counter-pressure signal is output to the upstream second register so as to generate the line blanking signal, and the line blanking signal is transmitted to the downstream third register of the first register, so that the problem that the line blanking signal is lost due to the elimination of the line blanking signal in the image data by a pipeline for processing the image data is avoided, the counter-pressure of the register designed by the pipeline can be actively generated to the upstream second register so as to regenerate the line blanking signal, ensure that the line blanking signal is not lost, and improve the integrity of data in the data transmission process.
Drawings
Fig. 1 illustrates one of flow diagrams of a data transmission method according to some embodiments of the present application;
FIG. 2 illustrates a schematic diagram of a first register provided in some embodiments of the application;
FIG. 3 illustrates one of the signal transmission timing diagrams of the first register provided in some embodiments of the application; FIG. 4 is a second diagram illustrating a signal transmission timing of a first register according to some embodiments of the present application;
fig. 5 shows a schematic block diagram of a data transmission device according to an embodiment of the present application;
FIG. 6 shows a block diagram of an electronic device according to an embodiment of the application;
fig. 7 is a schematic diagram of a hardware structure of an electronic device according to some embodiments of the present application.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or otherwise described herein, and that the objects identified by "first," "second," etc. are generally of a type not limited to the number of objects, for example, the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The data transmission method, the data transmission device, the electronic equipment and the readable storage medium provided by the embodiment of the application are described in detail below with reference to fig. 1 to 7 through specific embodiments and application scenarios thereof.
In some embodiments of the present application, a data transmission method is provided and applied to a first register, where the first register is connected to a second register and a third register, the second register is an upstream register of the first register, and the third register is a downstream register of the first register, and fig. 1 shows one of flow diagrams of the data transmission method provided in some embodiments of the present application. As shown in fig. 1, the data transmission method includes:
step 102, obtaining a preset clock of a line blanking signal output by a first register;
in the embodiment of the application, the preset clock is the clock required in the transmission process of the line blanking signal. The preset clock is set according to the number of line mute data required for the downstream register of the first register.
Illustratively, the output requirement of the downstream register of the first register for the first register to output the line blanking signal is: hblank=3, i.e. the number of line blanking signals is 3, the preset clock is determined to be 3 clocks.
Step 104, in the case that the first register receives the first target signal from the second register and the second target signal from the third register, the first register transmits the first back-pressure signal to the second register according to the preset clock, so that the first register can output the line blanking signal of the preset clock to the third register.
In the embodiment of the application, the first target signal is used for triggering the first register to trigger back pressure on the upstream second register, namely when the first register receives the first target signal transmitted by the upstream second register and the first register receives the second target signal transmitted by the downstream third register, the first back pressure signal is transmitted to the upstream second register according to the preset clock, so that the second register pauses transmitting data to the first register in the preset clock. At this time, the first register continuously transmits a blank signal to the downstream register, generates a line blank signal matched with a preset clock, and transmits the line blank signal to the downstream register. FIG. 2 shows a schematic diagram of a first register provided in some embodiments of the present application, as shown in FIG. 2, including lsof_in channel, leof_in channel, dvld_in channel, din channel, drdy_in channel, lsof_out channel, leof_out channel, dvld_out channel, dout channel, drdy_out channel. The first register receives signals transmitted from the upstream register through the lsof_in channel, the leof_in channel, the dvld_in channel and the din_in channel, and transmits signals to the downstream register through the lsof_out channel, the leof_out channel, the dvld_out channel and the din_out channel, and the first register transmits signals to the upstream register through the drdy_in channel and receives signals transmitted from the downstream register through the drdy_out channel. Wherein the lsof_in channel and lsof_out channel are used for transmitting line head signals, the leof_in channel and leof_out channel are used for transmitting line tail signals, the dvld_in channel and dvld_out channel are used for transmitting valid identification signals, the din channel and dout channel are used for transmitting data signals, and the drdy_in channel and drdy_out channel are used for transmitting back pressure signals.
In the embodiment of the application, the first target signal is a signal transmitted by the second register upstream of the first register, when the first register receives the first target signal, the second register upstream is determined to complete the transmission of a section of signal, and a data signal comprising a line blanking signal needs to be transmitted to the downstream register of the first register, at this time, the first register starts to transmit a first back pressure signal to the second register upstream, so that the second register pauses outputting a signal to the first register, and the first register generates the line blanking signal and transmits the line blanking signal to the second register. When the first register receives the second target signal, it can be determined that the third register can receive the signal transmitted by the first register at the moment.
In the embodiment of the present application, the third register is a third register downstream of the first register, that is, the first register is capable of transmitting the line head signal, the line tail signal, the valid identification signal and the data signal to the third register.
Fig. 3 illustrates one of signal transmission timing diagrams of a first register provided in some embodiments of the present application, where in the case of blast=3, when the leof_in channel, the dvld_in channel, and the drdy_out channel are simultaneously 1, it is determined that the first target signal is received by the first register, and when the leof_in channel, the dvld_in channel are 1, it is determined that the second target signal is received by the first register, and when the drdy_out channel is 1, as shown in fig. 3. At this time, the signal of the drdy_in channel starts to be pulled down, and the first back pressure signal is output to the second register at the upstream. The first back-pressure signal is output starting at the 8 th clock cycle, and the first back-pressure signal is stopped starting at the 11 th clock cycle. As shown in fig. 3, BLANK data is generated in the data signal transmitted in the din channel, so that the effect of generating the line blanking signal by transmitting the first back-pressure signal to the upstream second register is achieved. Wherein lsof_in_tmp, leof_in_tmp, dvld_in_tmp, din_tmp, drdy_in_tmp represent temporary variables in lsof_in channel, leof_in channel, dvld_in channel, din channel, drdy_in channel, respectively, and drdy_in_tmp remains at 1 during the transfer of the first back pressure signal from the first register to the upstream second register.
In the embodiment of the application, when the first register detects the first target signal transmitted by the upstream second register and the second target signal transmitted by the downstream third register, the first counter-pressure signal is output to the upstream second register so as to generate the line blanking signal, and the line blanking signal is transmitted to the downstream third register of the first register, so that the problem that the line blanking signal is lost due to the elimination of the line blanking signal in the image data by a pipeline for processing the image data is avoided, the counter-pressure of the register designed by the pipeline can be actively generated to the upstream second register so as to regenerate the line blanking signal, ensure that the line blanking signal is not lost, and improve the integrity of data in the data transmission process.
In some embodiments of the present application, the first register transmits a first backpressure signal to the second register according to a preset clock, including: the first register transmits a first back pressure signal to the second register; acquiring a first clock of a first back pressure signal output by a first register; and under the condition that the first clock is matched with the preset clock, the first register stops transmitting the first back pressure signal to the second register.
In the embodiment of the application, after the first register starts to transmit the first back pressure signal to the second register, the first register starts to time the output of the first back pressure signal, and when the first clock of the first register for transmitting the first back pressure signal reaches the preset clock corresponding to the line blanking signal, the transmission of the first back pressure signal to the second register is stopped, so that the upstream second register continues to transmit the signal to the first register, and the clock occupied by the generated line blanking signal in the transmitted data signal is ensured to be matched with the preset clock.
The first register is provided with a counter, which is capable of counting the clock taken up by the first register transfer signal, and the counter starts counting when the first register starts transferring the first counter-pressure signal to the upstream second register. For example: and when BLANK=3, the first counter-pressure signal is transmitted to the first register for 3 clock cycles, and the first register stops outputting the first counter-pressure signal, so that the first clock occupied by BLANK data in the transmitted data signal is ensured to be consistent with the preset clock, and the accuracy of the BLANK data in the data signal transmission process is improved.
In the embodiment of the application, the first register is used for timing the first back pressure signal transmitted to the upstream second register, so that the first clock of the line blanking signal generated by the first register through transmitting the first back pressure signal is matched with the preset clock, and the accuracy of the line blanking signal in the data signal transmitted by the first register to the downstream third register is further ensured.
In some embodiments of the application, the first clock to obtain the first backpressure signal output by the first register comprises: in case the first register does not receive the second backpressure signal from the third register, the first clock is started to be acquired.
In the embodiment of the present application, when the downstream third register transmits the second back pressure signal to the first register, the first register pauses transmitting the signal to the downstream third register, and at this time, if the first register transmits the back pressure signal to the upstream second register, the first register cannot generate the line blanking signal, and cannot transmit the signal to the downstream third register. Thus, when the first register transmits the first backpressure signal to the upstream second register, it is necessary to determine that the downstream third register is not transmitting the second backpressure signal to the first register at this time. If the downstream third register transmits the second back pressure signal to the first register when the first register transmits the first back pressure signal to the upstream second register, the first register stops counting clock cycles of the transmitted first back pressure signal until the downstream third register stops transmitting the second back pressure signal to the first register, and the first clock corresponding to the first back pressure signal is acquired by counting the clock cycles of the transmitted first back pressure signal.
Fig. 4 shows a second signal transmission timing diagram of the first register according to some embodiments of the present application, where, as shown in fig. 4, when the lean_in channel, the dvld_in channel, and the drdy_out channel are simultaneously 1 in the output signal, it is determined that the first target signal and the second target signal are received, and at this time, the signal of the drdy_in channel starts to be pulled down, and the first back-pressure signal is output to the second register. The first back pressure signal is output at the 8 th clock period, the clock counter of the first register temporarily does not count at the moment when the second back pressure signal of the third register is received at the drdy_out channel of the first register at the 8 th clock period, the clock counter of the first register starts to count when the third register at the 11 th clock period stops outputting the second back pressure signal, and the first register stops transmitting the first back pressure signal after the count reaches 3 clock periods. It can be seen that the blank signals from the 8 th clock to the 11 th clock are generated in the data signal transmitted in the din channel of the first register, wherein the transmission signals from the 8 th clock to the 11 th clock cannot be transmitted to the downstream third register due to the second back-pressure signal, i.e. the data signal transmitted from the 11 th clock to the 14 th clock includes the line blank signals from 3 clock cycles. Wherein lsof_in_tmp, leof_in_tmp, dvld_in_tmp, din_tmp, drdy_in_tmp represent temporary variables in lsof_in channel, leof_in channel, dvld_in channel, din channel, drdy_in channel, respectively.
It should be noted that, when the drdy_out channel is 1, it is determined that the first register receives the second target signal transmitted by the downstream third register, and when the drdy_out channel is 0, it is determined that the first register receives the second back pressure signal transmitted by the downstream third register.
In the embodiment of the present application, after the last beat of the data signal of the first line of data of the first register is received by the downstream third register, the clock counter of the first register counts the clock cycles of the output first back pressure signal. During the counting process, the downstream third register remains not transmitting the second counter-pressure signal to the first register, thereby ensuring the validity of the counting process of the first register transmitting the clock cycles of the first counter-pressure signal.
In the embodiment of the application, under the condition that the first register receives the second back pressure signal transmitted by the downstream third register, the clock period for transmitting the first back pressure signal is not counted, so that the situation that the line blanking signal generated by the first register is lost due to the back pressure of the third register is avoided, and the accuracy of the line blanking signal in the data signal transmitted by the downstream third register by the first register is further ensured.
In some embodiments of the present application, before the first register receives the first target signal from the second register, the first register transmits the first backpressure signal to the second register according to a preset clock, the method further includes:
the first register receives a transmission signal from the second register, wherein the transmission signal of the second register comprises at least one of: a line head signal, a line tail signal, a valid identification signal and a data signal.
In the embodiment of the present application, before the first register transmits the first backpressure signal to the upstream second register, the first register can receive at least one of a line head signal, a line tail signal, a valid identification signal and a data signal transmitted from the upstream second register.
Illustratively, the first register includes an lsof_in channel, a leof_in channel, a dvld_in channel, and a din channel. The first register receives a line head signal from an upstream second register through an lsof_in channel, the first register receives a line tail signal from the upstream second register through a leof_in channel, the first register receives a valid identification signal from the upstream second register through a dvld_in channel, and the first register receives a data signal from the upstream second register through a din channel.
In some possible embodiments, the first register is connected to a third register downstream, the first register being capable of receiving a second backpressure signal transmitted from the third register.
For example: the first register comprises a drdy_out channel, an lsof_out channel, a leof_out channel, a dvld_out channel and a dout channel, and stops transmitting a line head signal, a line tail signal, an effective identification signal and a data signal to the third register after receiving a second back pressure signal from the downstream third register through the drdy_out channel.
In the embodiment of the application, the first register can receive the signal transmitted by the second register at the upstream, so that the first register can stably receive the signal from the second register when the first counter-pressure signal is not transmitted to the second register at the upstream.
In some embodiments of the application, the first target signal comprises: the line tail signal and the valid identification signal, and the second target signal comprises: a signal may be transmitted.
In the embodiment of the application, the first target signal is the line tail signal and the effective identification signal transmitted to the first register by the upstream second register, when the first register receives the line tail signal and the effective identification signal of the upstream second register, the upstream second register is determined to have finished receiving the complete line transmission signal, and the first back pressure signal is transmitted to the upstream second register at the moment, so that the problem of discontinuous received signals can be avoided, and the first back pressure signal is transmitted to the upstream second register when the line tail signal is received because the line blanking signal is usually at the end of a line data signal, so that the position of the generated line blanking signal can be ensured to be accurate.
Illustratively, when the leof_in channel and the dvld_in channel are 1, then it is determined that the first register receives the valid identification signal and the end-of-line signal transmitted by the second register upstream.
In the embodiment of the present application, the second target signal is a transmissible signal transmitted from the downstream third register to the first register, for example: when the downstream third register does not transmit the second back pressure signal to the first register, it is determined that the first register receives the transmittable signal.
Illustratively, when the drdy_out channel is 1, then it is determined that the first register receives the transmissible signal transmitted by the downstream third register. When the drdy_out channel is 0, it is determined that the first register receives the second back pressure signal transmitted by the downstream third register.
In the embodiment of the application, the first target signal comprises the line tail signal and the effective identification signal, so that the generated line blanking signal can be ensured to be accurate in position, and the second target signal comprises the transmissible signal, so that the third register at the downstream can receive the line blanking signal when the first register generates the line blanking signal, and the generated line blanking signal is prevented from being lost.
According to the data transmission method provided by the embodiment of the application, the execution main body can be a data transmission device. In the embodiment of the present application, a data transmission device executes a data transmission method as an example, which describes the data transmission device provided in the embodiment of the present application.
In some embodiments of the present application, a data transmission device is provided, and the data transmission device is applied to a first register, where the first register is connected to a second register and a third register, the second register is an upstream register of the first register, and the third register is a downstream register of the first register, and fig. 5 shows a schematic block diagram of the data transmission device provided by the embodiment of the present application, and as shown in fig. 5, the data transmission device 500 includes:
an obtaining module 502, configured to obtain a preset clock of a line blanking signal output by the first register;
the transmission module 504 is configured to, when the first register receives the first target signal from the second register and the second target signal from the third register, transmit the first back-pressure signal to the second register according to the preset clock, so that the first register can output the line blanking signal of the preset clock to the third register.
In the embodiment of the application, when the first register detects the first target signal transmitted by the upstream second register and the second target signal transmitted by the downstream third register, the first counter-pressure signal is output to the upstream second register so as to generate the line blanking signal, and the line blanking signal is transmitted to the downstream third register of the first register, so that the problem that the line blanking signal is lost due to the elimination of the line blanking signal in the image data by a pipeline for processing the image data is avoided, the counter-pressure of the register designed by the pipeline can be actively generated to the upstream second register so as to regenerate the line blanking signal, ensure that the line blanking signal is not lost, and improve the integrity of data in the data transmission process.
In some embodiments of the application, the transmission module is configured to transmit the first backpressure signal to the second register by the first register;
an obtaining module 502, configured to obtain a first clock of a first back pressure signal output by a first register;
the transmission module 504 is configured to stop the first register from transmitting the first backpressure signal to the second register when the first clock matches with the preset clock.
In the embodiment of the application, the first register is used for timing the first back pressure signal transmitted to the upstream second register, so that the first clock of the line blanking signal generated by the first register through transmitting the first back pressure signal is matched with the preset clock, and the accuracy of the line blanking signal in the data signal transmitted by the first register to the downstream register is further ensured.
In some embodiments of the present application, the acquiring module 502 is configured to start acquiring the first clock if the first register does not receive the second backpressure signal from the third register.
In the embodiment of the application, under the condition that the first register receives the second back pressure signal transmitted by the downstream third register, the clock period for transmitting the first back pressure signal is not counted, so that the situation that the line blanking signal generated by the first register is lost due to the back pressure of the third register is avoided, and the accuracy of the line blanking signal in the data signal transmitted by the downstream third register by the first register is further ensured.
In some embodiments of the present application, the data transmission apparatus 500 further includes:
the receiving module is used for receiving the transmission signal from the second register by the first register, wherein the transmission signal of the second register comprises at least one of the following: a line head signal, a line tail signal, a valid identification signal and a data signal.
In the embodiment of the application, the first register can receive the signal transmitted by the second register at the upstream, so that the first register can stably receive the signal from the second register when the first counter-pressure signal is not transmitted to the second register at the upstream.
In some embodiments of the application, the first target signal comprises: the line tail signal and the valid identification signal, and the second target signal comprises: a signal may be transmitted.
In the embodiment of the application, the first target signal comprises the line tail signal and the effective identification signal, so that the generated line blanking signal can be ensured to be accurate in position, and the second target signal comprises the transmissible signal, so that the third register at the downstream can receive the line blanking signal when the first register generates the line blanking signal, and the generated line blanking signal is prevented from being lost.
The data transmission device in the embodiment of the application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices than a terminal. Illustratively, the electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a mobile internet appliance (Mobile Internet Device, MID), an augmented reality (augmented reality, AR)/Virtual Reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), or the like, and may also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a Television (TV), a teller machine, a self-service machine, or the like.
The data transmission device in the embodiment of the application can be a device with an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, and the embodiment of the present application is not limited specifically.
The data transmission device provided by the embodiment of the present application can implement each process implemented by the above method embodiment, and in order to avoid repetition, details are not repeated here.
Optionally, the embodiment of the present application further provides an electronic device, which includes the data transmission device in any one of the embodiments, so that the electronic device has all the beneficial effects of the data transmission device in any one of the embodiments, and will not be described in detail herein.
Optionally, an electronic device is further provided in the embodiment of the present application, fig. 6 shows a block diagram of a structure of the electronic device according to the embodiment of the present application, as shown in fig. 6, the electronic device 600 includes a processor 602, a memory 604, and a program or an instruction stored in the memory 604 and capable of running on the processor 602, where the program or the instruction implements each process of the above-mentioned data transmission method embodiment when executed by the processor 602, and the process can achieve the same technical effect, and is not repeated herein.
The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.
Fig. 7 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.
The electronic device 700 includes, but is not limited to: radio frequency unit 701, network module 702, audio output unit 703, input unit 704, sensor 705, display unit 706, user input unit 707, interface unit 708, memory 709, and processor 710.
Those skilled in the art will appreciate that the electronic device 700 may also include a power source (e.g., a battery) for powering the various components, which may be logically connected to the processor 710 via a power management system so as to perform functions such as managing charge, discharge, and power consumption via the power management system. The electronic device structure shown in fig. 7 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.
The processor 710 is configured to obtain a preset clock of the line blanking signal output by the first register;
the processor 710 is configured to, when the first register receives the first target signal from the second register and the second target signal from the third register, transmit a first back-pressure signal to the second register according to a preset clock, so that the first register can output a line blanking signal of the preset clock to the third register.
In the embodiment of the application, when the first register detects the first target signal transmitted by the upstream second register and the second target signal transmitted by the downstream third register, the first counter-pressure signal is output to the upstream second register so as to generate the line blanking signal, and the line blanking signal is transmitted to the downstream third register of the first register, so that the problem that the line blanking signal is lost due to the elimination of the line blanking signal in the image data by a pipeline for processing the image data is avoided, the counter-pressure of the register designed by the pipeline can be actively generated to the upstream second register so as to regenerate the line blanking signal, ensure that the line blanking signal is not lost, and improve the integrity of data in the data transmission process.
In some embodiments of the application, the processor 710 is configured to transmit a first backpressure signal from the first register to the second register;
a processor 710 for acquiring a first clock of a first backpressure signal output by the first register;
the processor 710 is configured to stop the first register from transmitting the first back-pressure signal to the second register if the first clock matches the predetermined clock.
In the embodiment of the application, the first register is used for timing the first back pressure signal transmitted to the upstream second register, so that the first clock of the line blanking signal generated by the first register through transmitting the first back pressure signal is matched with the preset clock, and the accuracy of the line blanking signal in the data signal transmitted by the first register to the downstream register is further ensured.
In some embodiments of the present application, the processor 710 is configured to begin acquiring the first clock if the first register does not receive the second backpressure signal from the third register.
In the embodiment of the application, under the condition that the first register receives the second back pressure signal transmitted by the downstream third register, the clock period for transmitting the first back pressure signal is not counted, so that the situation that the line blanking signal generated by the first register is lost due to the back pressure of the third register is avoided, and the accuracy of the line blanking signal in the data signal transmitted by the downstream third register by the first register is further ensured.
In some embodiments of the present application, processor 710 is configured to receive a transmission signal from a second register, wherein the transmission signal of the second register comprises at least one of: a line head signal, a line tail signal, a valid identification signal and a data signal.
In the embodiment of the application, the first register can receive the signal transmitted by the second register at the upstream, so that the first register can stably receive the signal from the second register when the first counter-pressure signal is not transmitted to the second register at the upstream.
In some embodiments of the application, the first target signal comprises: the line tail signal and the valid identification signal, and the second target signal comprises: a signal may be transmitted.
In the embodiment of the application, the first target signal comprises the line tail signal and the effective identification signal, so that the generated line blanking signal can be ensured to be accurate in position, and the second target signal comprises the transmissible signal, so that the third register at the downstream can receive the line blanking signal when the first register generates the line blanking signal, and the generated line blanking signal is prevented from being lost.
It should be appreciated that in embodiments of the present application, the input unit 704 may include a graphics processor (Graphics Processing Unit, GPU) 7041 and a microphone 7042, with the graphics processor 7041 processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The display unit 706 may include a display panel 7061, and the display panel 7061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 707 includes at least one of a touch panel 7071 and other input devices 7072. The touch panel 7071 is also referred to as a touch screen. The touch panel 7071 may include two parts, a touch detection device and a touch controller. Other input devices 7072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.
The memory 709 may be used to store software programs as well as various data. The memory 709 may mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 709 may include volatile memory or nonvolatile memory, or the memory 709 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (ddr SDRAM), enhanced SDRAM (Enhanced SDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DRRAM). Memory 709 in embodiments of the application includes, but is not limited to, these and any other suitable types of memory.
Processor 710 may include one or more processing units; optionally, processor 710 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, and the like, and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 710.
The embodiment of the application also provides a readable storage medium, and the readable storage medium stores a program or an instruction, which when executed by a processor, implements each process of the above method embodiment, and can achieve the same technical effects, so that repetition is avoided, and no further description is provided herein.
The processor is a processor in the electronic device in the above embodiment. Readable storage media include computer readable storage media such as computer readable memory ROM, random access memory RAM, magnetic or optical disks, and the like.
The embodiment of the application further provides a chip, the chip comprises a processor and a communication interface, the communication interface is coupled with the processor, the processor is used for running programs or instructions, the processes of the data transmission method embodiment can be realized, the same technical effects can be achieved, and the repetition is avoided, and the description is omitted here.
It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.
Embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the above-described data transmission method embodiments, and achieve the same technical effects, and for avoiding repetition, a detailed description is omitted herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in part in the form of a computer software product stored on a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method of the embodiments of the present application.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims (12)

1. A data transmission method, characterized in that it is applied to a first register, the first register is connected with a second register and a third register, the second register is an upstream register of the first register, and the third register is a downstream register of the first register, the data transmission method comprises:
acquiring a preset clock of a line blanking signal output by the first register;
in the case that the first register receives a first target signal from the second register and a second target signal from the third register, the first register transmits a first back-pressure signal to the second register according to the preset clock so that the first register can output a line blanking signal of the preset clock to the third register.
2. The method of claim 1, wherein the first register transmits a first backpressure signal to the second register according to the preset clock, comprising:
the first register transmits a first back pressure signal to the second register;
acquiring a first clock of the first back pressure signal output by the first register;
And under the condition that the first clock is matched with the preset clock, the first register stops transmitting a first back pressure signal to the second register.
3. The method of claim 2, wherein the first clock for obtaining the first backpressure signal output by the first register comprises:
the first clock is started to be acquired if the first register does not receive the second back pressure signal from the third register.
4. A data transmission method according to any one of claims 1 to 3, wherein, in a case where the first register receives a first target signal from the second register and a second target signal from the third register, the first register further includes, before transmitting a first back-pressure signal to the second register according to the preset clock:
the first register receives a transmission signal from the second register, wherein the transmission signal of the second register includes at least one of: a line head signal, a line tail signal, a valid identification signal and a data signal.
5. A data transmission method according to any one of claims 1 to 3, wherein the first target signal comprises: a row tail signal and a valid identification signal, the second target signal comprising: a signal may be transmitted.
6. A data transmission device, characterized in that it is applied to a first register, the first register is connected with a second register and a third register, the second register is an upstream register of the first register, the third register is a downstream register of the first register, the data transmission device comprises:
the acquisition module is used for acquiring a preset clock of the line blanking signal output by the first register;
and the transmission module is used for transmitting a first back pressure signal to the second register according to the preset clock under the condition that the first register receives a first target signal from the second register and a second target signal from the third register, so that the first register can output a line blanking signal of the preset clock to the third register.
7. The data transmission device of claim 6, wherein,
the transmission module is used for transmitting a first back pressure signal to the second register by the first register;
the acquisition module is used for acquiring a first clock of the first back pressure signal output by the first register;
And the transmission module is used for stopping the first register from transmitting a first back pressure signal to the second register under the condition that the first clock is matched with the preset clock.
8. The data transmission apparatus according to claim 7, wherein the acquiring module is configured to start acquiring the first clock if the first register does not receive the second back-pressure signal from the third register.
9. The data transmission apparatus according to any one of claims 6 to 8, characterized by further comprising:
a receiving module, configured to receive, by the first register, a transmission signal from the second register, where the transmission signal of the second register includes at least one of: a line head signal, a line tail signal, a valid identification signal and a data signal.
10. The data transmission apparatus according to any one of claims 6 to 8, wherein the first target signal includes: a row tail signal and a valid identification signal, the second target signal comprising: a signal may be transmitted.
11. An electronic device, comprising:
a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method of any one of claims 1 to 5.
12. A readable storage medium having stored thereon a program or instructions which when executed by a processor implement the steps of the method according to any of claims 1 to 5.
CN202310891427.4A 2023-07-20 2023-07-20 Data transmission method, device, electronic equipment and readable storage medium Pending CN116932047A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117713799A (en) * 2024-02-05 2024-03-15 此芯科技(北京)有限公司 Pipeline back-pressure logic circuit and electronic equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117713799A (en) * 2024-02-05 2024-03-15 此芯科技(北京)有限公司 Pipeline back-pressure logic circuit and electronic equipment
CN117713799B (en) * 2024-02-05 2024-04-30 此芯科技(北京)有限公司 Pipeline back-pressure logic circuit and electronic equipment

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