CN116916100A

CN116916100A - Display system and reference monitor

Info

Publication number: CN116916100A
Application number: CN202310701520.4A
Authority: CN
Inventors: 王伟; 夏建龙
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2023-06-13
Filing date: 2023-06-13
Publication date: 2023-10-20

Abstract

The application discloses a display system and a reference monitor, which are used for improving the working efficiency, wherein the system comprises: the SDI-HDMI adapter plate is used for receiving video data sent by the input device, converting the video data from a digital component serial interface SDI signal into a high-definition multimedia interface HDMI signal and then sending the signal to the FPGA; the FPGA is used for receiving the HDMI signal sent by the signal adapter plate, analyzing the HDMI signal into a digital signal, performing image processing on the digital signal, and sending the digital signal to the display screen for display; the FPGA comprises: the interrupt source module is used for collecting at least one type of interrupt signals; the MCU kernel control unit is used for triggering error correction instructions corresponding to the type interrupt signals according to the type of the interrupt signals in the interrupt source module; a control register for storing an error correction instruction; and the reset control module is used for executing the reset operation corresponding to the latest error correction instruction when the error correction instruction in the control register changes.

Description

Display system and reference monitor

Technical Field

The application relates to the technical field of display, in particular to a display system and a reference monitor.

Background

In order to improve the display effect of images or videos, a reference monitor is gradually proposed in the prior art, and is different from a common display, and the reference monitor has extremely strict requirements on brightness, contrast, color gamut, product reliability and the like, and is the basis for professional people to measure, judge and decide images. Therefore, the reference monitor is also known in the industry as a "Miyuan device" in the field of image quality, and is a single-rod image quality scale.

Disclosure of Invention

The embodiment of the application provides a display system and a reference monitor, which are used for realizing independent detection and error correction classification of each path of input signals so as to perform corresponding reset operation, and avoiding more time consumption caused by unified reset of all input signals as one type, thereby shortening the integral time required by the restoration of a picture and improving the working efficiency.

In a first aspect, an embodiment of the present application provides a display system, including:

the SDI-HDMI adapter plate is used for receiving video data sent by the input device, converting the video data from a digital component serial interface SDI signal into a high-definition multimedia interface HDMI signal and then sending the high-definition multimedia interface HDMI signal to the FPGA;

the FPGA is used for receiving the HDMI signal sent by the signal adapter plate, analyzing the HDMI signal into a digital signal, performing image processing on the digital signal, and sending the digital signal to a display screen for display;

wherein, the FPGA includes:

the HDMI signal receiving and processing module is used for receiving the HDMI signal sent by the signal adapter plate and analyzing the HDMI signal into a digital signal;

the video signal sending processing module is used for sending the digital signal to a display screen for display after carrying out image processing on the digital signal;

The interrupt source module is used for collecting at least one type of interrupt signals;

the MCU kernel control unit is used for triggering error correction instructions corresponding to the type interrupt signals according to the type of the interrupt signals in the interrupt source module;

a control register for storing the error correction instruction;

and the reset control module is used for executing the reset operation corresponding to the latest error correction instruction when the error correction instruction in the control register changes.

It can be seen that, in the display system provided by the embodiment of the application, at least one type of interrupt signal is collected through the interrupt source module, and then the MCU kernel control unit triggers the error correction instruction corresponding to the type of interrupt signal according to the type of interrupt signal in the interrupt source module, the control register stores the error correction instruction, and finally, when the error correction instruction in the control register changes, the reset control module executes the reset operation corresponding to the latest error correction instruction, so that independent detection and error correction classification for each path of input signal are realized, corresponding reset operation is performed, and more time is consumed due to the fact that all input signals are integrally reset as one type, thereby shortening the overall time required for recovering the picture to be normal, and improving the working efficiency.

In a second aspect, an embodiment of the present application provides a reference monitor, including the display system.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of an application scenario of a reference monitor according to an embodiment of the present application;

fig. 2 is a schematic diagram of an overall structure of a display system according to an embodiment of the present application;

fig. 3 is a schematic diagram of a specific structure of a display system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a specific structure of a reference monitor according to an embodiment of the present application;

fig. 5 is a schematic diagram of the overall structure of an FPGA according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a specific structure of a reference monitor according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an error correction mechanism of a reference monitor according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a startup control flow provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of a fault prompting flow provided in an embodiment of the present application;

FIG. 10 is a schematic diagram of an interrupt detection flow provided in an embodiment of the present application;

FIG. 11 is a schematic diagram of a display system according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a display system according to an embodiment of the present application;

FIG. 13 is a schematic workflow diagram of a display system according to an embodiment of the present application;

fig. 14 is a schematic diagram of an abnormal error correction process in an SDI-HDMI adapter provided in an embodiment of the present application;

fig. 15 is a schematic workflow diagram of SPI data configuration reading and switching of an FPGA according to an embodiment of the present disclosure;

FIG. 16 is a schematic diagram of a "field-like" arrangement provided by an embodiment of the present application;

FIG. 17 is a schematic diagram of a "Chuan-type" arrangement according to an embodiment of the present application;

FIG. 18 is a schematic diagram of a pixel cross arrangement according to an embodiment of the present application;

FIG. 19 is a schematic diagram of a test card according to an embodiment of the present application;

FIG. 20 is a schematic diagram of a pixel cross arrangement error according to an embodiment of the present application;

FIG. 21 is a schematic diagram of a "Chuan-type" arrangement error provided by an embodiment of the present application;

FIG. 22 is a schematic diagram of a "field-type" arrangement error according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The embodiment of the application provides a display system and a reference monitor, which are used for realizing independent detection of each path of input signals and corresponding reset operation, and avoiding more time consumption caused by integral reset of all input signals, thereby shortening the integral time required by picture restoration and improving the working efficiency.

The display system and the reference monitor are based on the same application conception, and because the principles of solving the problems are similar, the implementation of the display system and the reference monitor can be mutually referred to, and the repetition is not repeated.

The terms first, second and the like in the description and in the claims of embodiments of the application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The following examples and embodiments are to be construed as illustrative only. Although the specification may refer to "an", "one", or "some" example or embodiment(s) at several points, this does not mean that each such reference is related to the same example or embodiment, nor that the feature is applicable to only a single example or embodiment. Individual features of different embodiments may also be combined to provide further embodiments. Furthermore, terms such as "comprising" and "including" should be understood not to limit the described embodiments to consist of only those features already mentioned; such examples and embodiments may also include features, structures, units, modules, etc. that are not specifically mentioned.

Various embodiments of the application are described in detail below with reference to the drawings attached to the specification. It should be noted that, the display sequence of the embodiments of the present application only represents the sequence of the embodiments, and does not represent the advantages or disadvantages of the technical solutions provided by the embodiments.

Fig. 1 is a schematic diagram of an application scenario according to some embodiments of the present application, intended to illustrate a class of scenarios in which multiple reference monitors are present, including but not limited to devices with data transceiving and processing functions and image display and/or sound output functions, and a server that may communicate with the reference monitors. In the scenario shown in fig. 1, a control device 100, a reference monitor 200, a mobile device 300, and a server 400 are included.

Based on the internet of things technology, communication connection can be established between a plurality of reference monitors in the above scenario, such as communication between the mobile device 300 and the reference monitor 200, so as to project a screen displayed on the mobile device 300 onto the reference monitor 200. The number of similar terminal devices is not limited herein.

In some embodiments, control between different display devices may be achieved by control device 100. As shown in fig. 1, a user can control or operate the reference monitor 200 to switch a display mode, switch a data receiving function, and the like by the control device 100.

In some embodiments, the control device 100 may be a remote control, and the communications between the remote control and the reference monitor 200 may include infrared protocol communications or bluetooth protocol communications, and other short-range communications, and the reference monitor 200 may be controlled by wireless or wired means. The user can control the reference monitor 200 by inputting a user instruction through a key on the remote controller, a voice input, a control panel input, a key on the reference monitor 200, or the like.

In some embodiments, the user may switch the display function of the reference monitor 200 by controlling the apparatus 100, thereby implementing the display of the media data in the display mode corresponding to the display function.

The 8K ultra-large screen display can enable a viewer to see clearer image quality and wider viewing angle and see texture and details far exceeding 4K, so as to obtain realism and immersion feeling like the feeling of being in the scene.

The embodiment of the application supports a display scheme that multiple paths of signals are spliced into an 8K image, ensures the cooperative work of multiple paths of input signals, ensures the stable receiving and displaying of the input signals in a switching-on and switching-off stage and an input signal switching process, and provides a corresponding error correction mechanism aiming at the conditions of abnormal display and the like caused by power-on and switching-off, input signal source switching, signal frame rate switching, front-end signal sequence disorder and the like, for example: the input signal source switching and the signal frame rate switching can cause unstable clocks, thereby causing the work disorder of an internal analysis module of an FPGA (Field Programmable Gate Array ) and causing image wiredrawing flickering or screen blacking. The front-end signal is connected in sequence and disordered, so that the image dislocation can be caused, or the normal display can not be realized.

The overall frame of the display system provided by the embodiment of the application is shown in fig. 2, and adopts a system architecture of 'SDI-HDMI adapter plate+FPGA+display screen'.

Referring to fig. 3, the video data is transmitted from the input device to the SDI-to-HDMI adapter plate, the SDI (Serial Digital Interface, digital component serial interface) signal is converted into a signal in the form of HDMI (High Definition Multimedia Interface ) and is sent to the FPGA, the HDMI phy module and the HDMI ctrl module parse the video signal into a digital signal and send the digital signal to the functional module, and the functional module performs image quality processing such as high dynamic range (High Dynamic Range Imaging, HDR) on the signal. The processed signals are sent to the back end through the VBO TX ctrl module and the VBO TX phy module, and finally, the processed signals are displayed on a display. The HDMI phy module is used for completing data serial-parallel conversion, namely converting a high-speed serial signal into a low-speed parallel signal; the HDMI ctrl module analyzes the parallel HDMI signals into VGA data signals (comprising R, G, B, HS, VS, DE signals, namely red, green and blue three primary color signals and time sequence signals). The VBO TX ctrl module converts common VGA data (R, G, B, HS, VS, DE signal) into parallel data of the VBO protocol. And the VBO TX phy module converts the parallel VBO protocol data into serial VBO data.

Aiming at the problems, a micro control unit (Micro Controller Unit, MCU) reads the time sequence parameters of the time sequence detection module, compares the time sequence parameters with preset parameters, and resets the HDMI phy module and the HDMI ctrl module in the FPGA as a whole if an error occurs. If the data detected by the time sequence detection module is detected to be normal after the resetting is carried out for a plurality of times, the MCU stops resetting and the image is displayed normally. If the data detected by the timing detection module detects an abnormality after a plurality of resets, and the detection time has exceeded a preset time. The MCU will stop the reset operation and the machine is in the error display state.

Therefore, according to the technical scheme, all signals are input as a whole, and the HDMI phy module and the HDMI ctrl module are reset integrally without distinguishing error types. The method is simple and rough and consumes more time. Sometimes, a good path is changed after reset, and the reset is often needed again to recover. When all signals are reset repeatedly and all paths are normal at the same time, the reset is stopped and then the display is carried out, so that the scheme has a plurality of unnecessary operations and wastes time and resources.

Therefore, the embodiment of the application provides a technical scheme for classifying various errors and adopting different measures for different errors. And each path of signal is independently detected, so that compared with a conventional method, misoperation is avoided, and the overall signal recovery time is shortened.

And when the encountered errors cannot be automatically solved, the user is reminded of the reasons of the errors, and the user is assisted to solve the non-machine problem. Such as line loss, poor contact, etc. Previous conventional solutions rely on experience to determine, which often wastes a lot of time due to poor contact of a wire. The design can help the user to check out the reason of the problem, and help the user to quickly locate the problem.

The specific structure of a display system provided by the embodiment of the application is shown in fig. 4, and includes: SDI changes HDMI keysets, FPGA etc. wherein:

SDI changes HDMI keysets, realizes the conversion of SDI signal to HDMI signal. The SDI-to-HDMI adapter plate increases the number of input interfaces, and includes 4 SDI-to-HDMI chips, such as SDI2hdmi_1, SDI2hdmi_2, SDI2hdmi_3, and SDI2hdmi_4 shown in fig. 4 (corresponding to one SDI-to-HDMI channel, referred to as channels or channels, respectively). Each SDI-to-HDMI chip can support at most 4 SDI inputs and at most 16 SDI signals, and facilitates the access of professional playing equipment. Each output HDMI2.0 signal can support a maximum resolution of 4K, and then 4 HDMI can transmit 8K image data.

The SDI-HDMI adapter plate also comprises an MCU control chip, and the MCU control chip has the main function of performing control operations such as initialization and the like on the SDI-HDMI chip.

In some embodiments, the HDMI RX module (i.e., HDMI signal receiving and processing module) described in the embodiments of the present application includes: an HDMI phy module and an HDMI ctrl module; similarly, the VBO TX module (i.e., video signal transmission processing module) includes: a VBO TX ctrl module and a VBO TX phy module.

In some embodiments, the HDMI phy module described in the embodiments of the present application includes: and the phy1, phy2, phy3 and phy4 modules are respectively used for processing one path of HDMI signal.

In some embodiments, the HDMI ctrl module described in the embodiments of the present application includes: and the ctrl1, ctrl2, ctrl3 and ctrl4 modules are respectively used for processing one path of HDMI signal.

With further reference to fig. 5, the fpga specifically includes: a clock system, a signal receiving system, a signal processing system, a signal transmitting system, an MCU control system and the like. Wherein:

a clock system: the device comprises a crystal oscillator 1 and a crystal oscillator 2, and is used for providing an operating clock for the FPGA. The crystal oscillator 2 is a special differential clock and provides a reference clock for the high-speed serial-parallel conversion interface. The rx_out_clk clock recovered from the HDMI phy module is the synchronous clock of the front-end video signal. Each HDMI signal has a signal synchronization clock. In order to facilitate signal processing, the video signal synchronous clocks are unified to the clock analyzed by the first path of signals through the buffer modules of buf1, buf2, buf3, buf4 and the like.

The VBO TX phy module recovers the data synchronization clock tx_out_clk according to the front-end input signal and the reference clock of the crystal oscillator 2. The input data clock RX_out_clk and the video signal of the output data clock TX_out_clk are synchronized by the DDR read module and the DDR write module.

Signal receiving system: the HDMI comprises an HDMI phy module and an HDMI ctrl module, wherein the HDMI phy module comprises a phy1 module, a phy2 module, a phy3 module and a phy4 module, and the HDMI ctrl module comprises a ctrl1 module, a ctrl2 module, a ctrl3 module and a ctrl4 module. The HDMI phy module mainly performs serial-parallel conversion of HDMI signals, and the HDMI ctrl module converts the HDMI signals into parallel signals in RGB or YUV forms.

A signal processing system: the device mainly comprises a functional module, wherein the functional module is used for carrying out image quality processing such as color and the like on an input signal.

Signal transmission system: including a VBO TX ctrl module and a VBO TX phy module.

MCU control system: the device comprises an MCU kernel control unit, an interrupt source module and various registers. The MCU core control unit is an MCU built in the FPGA and can run software programs. The interrupt source module collects various interrupt signals. And various registers, including a reference register, an auxiliary information register, a control register and the like, are used for storing parameter information required by the operation of the system.

In some embodiments, the display system provided in the embodiments of the present application further includes:

external storage device: such as DDR (Double Data Rate) and FLASH (FLASH memory). The DDR is used for caching video data, and the FLASH is used for storing parameter data.

In some embodiments, referring to fig. 6, the FPGA provided in the embodiment of the present application further includes:

and the data arrangement and combination module is used for: the method is used for arranging and combining four paths of input data, each path of data is 4k image data, and then 4 paths of 4k image cards are spliced into 8k images according to the arrangement sequence.

and the data selection module is used for selecting which path of signals are displayed on the rear-end display screen.

In some embodiments, referring to fig. 6, the SDI-to-HDMI adapter board provided by the embodiment of the present application further includes:

and the power supply control module is used for realizing a power supply control function and respectively controlling different power supplies (power supplies 1-4) to supply power under the control of the MCU module. Therefore, each path of SDI to HDMI path is realized, independent circuit control is adopted, and power can be independently supplied and discharged. In addition, the HDMI_5V voltage signal of the output port of the SDI-to-HDMI adapter plate can also be independently controlled.

As shown in fig. 7, an error correction mechanism of the FPGA provided by the embodiment of the present application is shown, specifically:

the SDI-HDMI adapter plate can monitor the connection condition of SDI signals in real time and the conversion condition of the SDI signals to HDMI signals. If the SDI signal is switched, disconnected or converted abnormally, the interrupt signal INT_SDI signal is triggered in time.

Whether the HDMI_5V signal is present or not represents the physical connection between the SDI-to-HDMI adapter plate and the FPGA, if the HDMI_5V signal is present, otherwise, the HDMI_5V signal is not present.

The SDI-to-HDMI chip (i.e., a switch chip on the SDI-to-HDMI switch board, not shown in fig. 7) may parse the auxiliary information of the SDI signal in real time (i.e., the auxiliary data obtained by parsing the SDI when the SDI-to-HMDI signal), for example, includes: data bit width, frame rate, RGB or YUV, full or Limit, etc., and stores these auxiliary information in a reference register in real time.

In addition, the HDMI ctrl module also parses the auxiliary information of the video signal in real time and stores the auxiliary information in the auxiliary information register. The auxiliary information analyzed by the HDMI ctrl module is written into an auxiliary information register through the MCU core control unit. The MCU kernel control unit can access any module by default. The auxiliary information of the video signal is obtained by analyzing the HDMI signal.

And the comparison module is used for comparing the auxiliary information of the SDI signal obtained by analyzing the SDI-HDMI chip with the auxiliary information of the video signal obtained by analyzing the HDMI ctrl module. When the auxiliary information of the video signal obtained by the analysis of the HDMI ctrl module is found to be abnormal, feedback is carried out in the form of an interrupt signal. For example: the auxiliary information of the front end SDI signal is taken as a reference basis, the judgment is carried out based on the resolution, the auxiliary information of the SDI signal is the auxiliary information analyzed by the 3840x2160,HDMI ctrl module, namely 3333x2222, the two auxiliary information are inconsistent, the data are the same as the theoretical front and rear signals, if the two auxiliary information are inconsistent, the data must be consistent, if the two auxiliary information are inconsistent, a high-level signal can be fed back as an abnormal interrupt signal of the auxiliary information to an interrupt source module or a high-pulse signal to an interrupt source according to convention, and the HDMI ctrl module is prompted to analyze abnormal conditions.

The HDMI phy module parses the synchronous clock signal contained in the HDMI signal, and the parsed clock signal is sent to a PLL (phase locked loop) for use. When the change of the lock signal PLL_lock signal of the PLL is unstable, the clock signal is represented as unstable. Therefore, if the analyzed synchronous clock signal is unstable, the clock locking signal pll_lock is unstable, and the pll_lock interrupt signal is fed back to the interrupt source module for prompting that the data synchronous clock of the HDMI signal is abnormal.

The HDMI ctrl module analyzes an HPD signal in the HDMI signal, the HPD signal is a hot plug signal representing the HDMI signal, the HDMI signal contains the HPD signal, the HPD signal is from the HDMI ctrl module, when the HDMI line is connected with the FPGA, the HPD signal is pulled up and becomes a high-level signal, the high-level signal is fed back to a signal transmitting end (namely a transmitting end of an SDI-HDMI adapter plate), if the HPD signal is low level, the connection of the HDMI line and the FPGA is abnormal, and no HDMI signal is connected, the high-level signal is fed back to the interrupt source module.

The time sequence detection module is used for: parameters parsed by the HDMI RX module, such as a row valid signal, a field valid signal, and whether HDMI parsed data are all 0, are detected in real time. Wherein:

row valid signal: representing how many active pixels are in each row, and how many pixels are actually displayed, etc.

Field effective signal: how many active lines are per frame and how many lines are actually displayed.

The timing sequence detection module calculates real line effective signal parameters by counting signals analyzed by the HDMI RX module, for example, counting the line effective signals.

For example, the standard 4k signal resolution is 3840x2160, but some signal generators may send a custom resolution of 3280x2060, etc., which may be referred to as a non-standard resolution. Therefore, these custom resolution data are then referred to as non-standard data. Because the auxiliary information analyzed by the HDMI ctrl module is inaccurate when nonstandard data is input, at this time, the timing detection module needs to compare the data information analyzed by the HDMI ctrl module (for example, 3840x2160 line effective signal=3840, field effective signal=2160) with the information in the reference register sent by the front-end SDI-to-HDMI adapter board, to confirm whether the HDMI signal is analyzed correctly, and if not, to feed back the timing error interrupt signal to the interrupt source module.

In some embodiments, the timing detection module may be further configured to detect an arrangement of the input graphics card, and feed back the detected error information to the MCU core control unit. The input graphics card is designed according to requirements, can be designed by a computer, can be generated in an FPGA and is provided for a user. The error information is red, green, blue and white in sequence from left to right and from top to bottom if the four-split screen data are received. However, when the front end plays red, green, blue and Bai Tuka, but the back end displays green, red, blue and white, two channels of the upper half screen are illustrated, and the positions of the channel 1 and the channel 2 are wrong due to the inversion of red and green.

The VBO TX module detects the connection condition of a port (namely a transmitting end) for transmitting signals to the rear-end display screen by the FPGA, and if the transmitting end cannot be locked, the connection condition is fed back to the interrupt source module through a TX_lock interrupt signal sent by the VBO TX module. The FPGA is connected with the rear-end display screen, wherein the sending end refers to a port for sending signals to the rear-end display screen by the FPGA.

In summary, interrupt types include:

INT_SDI interrupt signal: indicating that the front end SDI2HDMI (including SDI2hdmi_1, SDI2hdmi_2, SDI2hdmi_3, SDI2 hdmi_4) is in error, the error always indicates no signal access.

Hdmi_5v interrupt signal (i.e.): and the HDMI line is disconnected, and no signal is connected.

Pll_lock interrupt signal: the clock rx_out_clk analyzed by the HDMI phy module is not stable.

HPD interrupt signal (i.e., HPD signal at low level from HDMI ctrl block): indicating no HDMI signal access.

Comparing interrupt signals sent by the modules: indicating that the HDMI RX parse data is incorrect.

Interrupt signal sent by time sequence detection module: indicating that the HDMI RX parse data is incorrect.

Tx_lock interrupt signal: indicating that the VBO TX module is transmitting a signal anomaly.

Through the various interrupt types, the system state is monitored in real time, abnormal conditions are classified, and different abnormal types are determined. The MCU kernel control unit controls the reset control module through the control register so as to perform corresponding reset operation or adopts power-on and power-off operation to control the corresponding module or circuit to recover to a normal state, specifically:

if the front end SDI signal is plugged, an INT_SDI interrupt signal is triggered, at this time, the MCU core control unit resets the HDMI phy module, the HDMI ctrl module and the like through the control register and the reset control module according to the starting sequence. The control register is used for receiving a data instruction of the MCU core control unit. The reset control module is used for detecting that the control register data instruction changes and resetting the module corresponding to the control register data instruction.

If the output signal of the plugged SDI-HDMI adapter plate is abnormal, resetting or restarting the SDI-HDMI chip, and eliminating the unstable signal state caused by the abnormal condition. Specifically, control may be performed by a GPIO (General Purpose Input/Output) interface signal as shown in FIG. 7. The MCU kernel control unit can control the reset control module to reset the SDI-HMDI chip. The MCU kernel control unit sends out GPIO interface signals to control restarting operations such as power on and power off.

If the clock analyzed by the HDMI phy module is unstable, a PLL_lock interrupt signal is triggered, and the reset control module resets the HDMI phy module and the HDMI ctrl module.

And if the signal is a time sequence error interrupt signal, resetting the HDMI ctrl module.

If the signal is TX_lock interrupt signal, the VBO TX module is reset.

Referring to fig. 7, the embodiment of the application further provides an input signal state prompting module in the FPGA, and when an abnormal problem occurs in the input signal at the front end, the input signal state prompting module displays the occurring problem to the rear end, prompts the manual operation, and eliminates the problem. The prompt characters displayed at the rear end are stored in the character storage module in a preset picture mode. For example: in signal detection, channel 1 has no signal access, channel 2 has weak signal, and the like.

In some embodiments, the input signal status prompting module includes: the device comprises a character storage module, a time sequence generation module, a data reading module, an address selection module and a data merging module. Wherein,,

the address selection module is used for selecting a corresponding address space in the character storage module according to the information read from the control register, so that the data reading module reads the prompt characters stored in the character storage module from the address space;

the time sequence generation module generates independent data transmission time sequence according to the external crystal oscillator (namely the crystal oscillator 1 in fig. 1). When the front-end timing analysis is abnormal, the timing replaces the front-end abnormal timing, and state prompt data are sent to the screen for display. Specifically, the timing generation module uses a separate timing signal that can send the graphics card or data to the back-end display. When the front-end data is found to be wrong, the data displayed at the back end is switched to the correct data channel through the data selection module. The state prompt data is prompt characters sent to the back end to be displayed in a picture mode. For example: in signal detection, channel 1 has no signal access, channel 2 has weak signal, and the like.

And a data reading module: and reading different prompt characters from the character storage module according to different types of faults and control of the address selection module. For example: if the HDMI_5V signal is always low, then no signal is asserted. The MCU kernel control unit sends an instruction to the address selection module, and the address selection module translates the corresponding instruction into a reading command and sends the reading command to the data reading module to read character data without signal access. That is, in a specific control process, the MCU core control unit analyzes the interrupt type and sends a corresponding error correction instruction to the address selection module, so that the address selection module controls the data reading module to read different prompt characters.

And a data merging module: and splicing the corresponding prompt characters and the pure blue base map into an 8K picture, and sending the 8K picture to the rear end for display.

The following describes the flow of the method provided by the embodiment of the application.

The normal startup control flow provided by the embodiment of the application, as shown in fig. 8, includes:

s501, starting up;

s502, powering up the system;

s503, loading a netlist by the FPGA, and initializing each IP.

S504, detecting connection conditions of the HDMI signals.

S505, stability of the HDMI phy module reference clock is detected.

S506, if the HDMI phy module reference clock is stable, resetting the HDMI phy module.

S507, after the HDMI phy module is reset, a reset completion flag (RST_DONE) is pulled high, namely the HDMI phy module is prompted to be reset;

and S508, after the HDMI phy module finishes resetting, the HDMI RX module resumes clock locking.

S509, the HDMI ctrl module analyzes correct data and sends the correct data to the back end.

S510, resetting the VBO TX phy module at the rear end.

S511, the display screen displays normal input signals.

The fault prompting flow provided by the embodiment of the application, as shown in fig. 9, includes:

s601, determining that an abnormal state occurs in an input signal.

S602, triggering an interrupt signal.

S603, the MCU kernel control unit judges the interrupt type.

S604, an input signal state prompting module selects a prompting character corresponding to the current interrupt type;

s605, the data selection module switches the picture output by the VBO TX module to a state prompt picture.

S606, displaying a character prompt picture with a blue background on the display screen, and avoiding abnormal conditions such as image wiredrawing and flickering caused by signal abnormality.

The interrupt detection flow provided by the embodiment of the application, as shown in fig. 10, includes:

s701, when the interrupt signal is triggered, the MCU core control unit detects the input signals one by one. When an abnormality occurs in a certain input signal, the abnormality type is analyzed first, for example, whether a signal is accessed is judged, if the HDMI_5V signal and the HPD signal are always low, no signal access is determined, and a corresponding channel displays "channel no signal access".

S702, if a signal is accessed, further judging whether an INT_SDI interrupt signal is triggered, if yes, executing step S703, otherwise executing step S704.

S703, if the INT_SDI interrupt signal is triggered, which indicates that the SDI2HDMI module is abnormal, resetting the SDI2HDMI module, attempting to eliminate the abnormal state, judging whether the restart is overtime, if so, the abnormal state cannot be eliminated, displaying that the input signal is abnormal, and if not, returning to the step S702.

S704, detecting whether the data synchronization clock RX_out_clk analyzed by the HDMI phy module is stable, if not, executing step S705, and if so, executing step S706.

S705, resetting the HDMI phy module and the HDMI ctrl module in sequence, judging whether the resetting of the HDMI phy module and the HDMI ctrl module is overtime, if yes, namely, the RX_out_clk signal still cannot be locked through resetting the HDMI phy module and the HDMI ctrl module, carrying out power-on and power-off operation on the HDMI_5V signal again, otherwise, returning to the step S704. When the hdmi_5v signal is powered up and down again, it is further determined whether the power up and down operation is overtime, if yes, step S703 is executed again (i.e. if the rx_out_clk still cannot be locked, the SDI2HDMI module is reset and restarted, and an attempt is made to clear the abnormal situation.

S706, judging whether the timing signal (RX_timing for short, the timing signal of the input end) of the HDMI RX module is correct, if so, executing step S708, otherwise, executing step S707;

s707, the abnormal interrupt triggered by the timing detection module and the data comparison module can be classified as RX_timing abnormal condition, when RX_timing abnormal condition is detected, resetting the HDMI ctrl module, judging whether the reset is overtime, if yes, returning to execute step S705 (i.e. if normal RX_timing still cannot be recovered after the HDMI ctrl module is overtime, operating according to an unstable reset flow of RX_out_clk), otherwise, returning to execute step S706;

s708, judging whether all input path signals are normal, if so, executing step S709, otherwise, executing step S710.

S709, after all the input signals are detected to be normal, the detection of whether the TX_lock signal is locked is continued, and if the TX_lock signal is locked, the data selection module switches the back-end display signal to the input signal. If the TX_lock signal is not locked, the VBO TX module is reset, attempting to lock the TX_lock signal. If the TX_lock signal still cannot be locked by resetting, no signal is sent to the back end, and the back end displays a black screen or no information is displayed.

S710, if some channel signals are normal and some signals are abnormal, if the detection is overtime, displaying normal channel signals and marking and displaying abnormal signal channels. If the detection is not timed out, the process returns to the step S701, and the anomaly detection is performed on the undetected path.

In addition, considering that the front-end SDI-HDMI adapter plate may have errors, when the front-end adapter plate is unstable, the input signal line of the SDI-HDMI adapter plate can be plugged in and plugged out again, so that signals are input and locked again. However, the operation is too simple and rough, and the SDI-to-HDMI adapter plate needs to be manually plugged and unplugged, so that the working efficiency is low.

In some embodiments, as shown in fig. 11, the SDI-HDMI adapter exists as a single unit, if the error condition occurring in the front SDI-HDMI adapter is not classified, when a certain path or a local error occurs in the SDI-HDMI adapter, it is common practice to reset or power up and down the whole SDI-HDMI adapter again, so as to clear the local error condition, and to restore the signal to normal, so that many unnecessary operations exist and much time is consumed. And if the SDI-HDMI adapter plate is locally wrong, the FPGA does not find the wrong type in time, and the wrong content of the front end can be sent to the screen end to be displayed, so that the problems of wire drawing, flickering, residual shadow and the like are caused. And the SDI-HDMI adapter plate is used as a part of the whole system, if the part is treated as a single whole, the signal flow control and the stability are relatively weak, the system stability is poor, and a local data flow uncontrollable state is easy to occur.

Therefore, as shown in fig. 12, a preferred implementation scheme is that each channel of the SDI-to-HDMI patch panel is independently controlled. Secondly, the state information of each module on the path can be collected independently, and each module can be controlled independently. The states of all the chip modules in the SDI-HDMI adapter plate can be transmitted to an MCU core control unit in the FPGA in real time. The MCU kernel control unit is used as a core control part of the whole system, and can independently collect information from each part of the whole data flow from the input end to the display end, comprehensively analyze and independently control the information. The SDI-HDMI adapter plate is completely integrated into the whole system, so that the controllability and stability of all parts of the display system are ensured.

Referring to fig. 12, inside the SDI-to-HDMI patch panel, there are included:

an SDI equalizing chip (e.g., SDI equalizing chip 1, SDI equalizing chip 2, SDI equalizing chip 3, SDI equalizing chip 4);

SDI2HDMI chip (e.g., SDI2hdmi_1, SDI2hdmi_2, SDI2hdmi_3, SDI2 hdmi_4);

HDMI equalizing chips (e.g., HDMI equalizing chip 1, HDMI equalizing chip 2, HDMI equalizing chip 3, HDMI equalizing chip 4);

each channel comprises three main chips, for example, channel 1 comprises an SDI equalization chip 1, an SDI2HDMI_1 and an HDMI equalization chip 1;

SDI equalization chip: the method has the main effects of converting the single-ended SDI signal into a differential SDI signal, removing the jitter of the single-ended SDI input signal and increasing the signal strength.

SDI2HDMI chip: and the main conversion chip is used for completing the conversion from the SDI signal to the HDMI signal.

HDMI equalization chip: and the jitter of the output HDMI signal is removed, and the signal strength is increased.

MCU chip: power-on initialization initializes each chip through the daisy-chain SPI path.

A voltage conversion module: and finishing voltage conversion and providing required voltage values for each chip.

HDMI_5V_EN control module: and receiving an SDI2HDMI_LOCK signal from the SDI2HDMI chip, an FPGA_5V_EN control signal from the FPGA and an HDMI hot plug signal, and controlling the output of HDMI_5V signals of all paths of HDMI signals according to the signals.

The first voltage control module sw1, the second voltage control module sw2, the third voltage control module sw3 and the fourth voltage control module sw4 are four-way HDMI_5V voltage control modules. And according to the control signal output by the HDMI_5V_EN control module, controlling the high and low of the HDMI_5V signal and outputting the HDMI_5V signal to the FPGA.

In the normal operation, each SDI equalizing chip outputs an sdi_lock signal as a flag for the normal operation of the chip. When the SDI_LOCK signal goes high, it marks that the chip starts to work normally. When the sdi_lock signal is pulled down or toggled up or down, which indicates that the chip is abnormal in operation and cannot normally LOCK the front-end signal, in some embodiments, the signal may be connected to an indicator light, to indicate the presence or absence of an input signal and the operating state of the chip. In some embodiments, the sdi_lock signal may be used as the highest priority interrupt signal. When the SDI_LOCK signal is out of LOCK, the input signal is marked to be abnormal, the rear end is required to be informed of blue screen shielding in time, and error image data display is avoided.

Regarding each SDI2HDMI chip, it is important to detect and control the working state as a main conversion chip. When the SDI2HDMI chip enters the working state, an SDI2HDMI_LOCK signal is given, the signal LOCK represents that the SDI2HDMI chip finishes conversion from the SDI signal to the HDMI signal, and the HDMI signal can be normally output. The SDI2hdmi_lock signal is locked, and can be used as a control signal for the hdmi_5v signal, representing that the HDMI signal can be normally output. If the SDI2HDMI_LOCK signal is out of LOCK, the SDI2HDMI chip is abnormal.

In some embodiments, each SDI2HDMI chip has an independent reset control signal: SDI2hdmi_rst.

In some embodiments, each SDI2HDMI chip has an independent fpga_spi data communication interface. When the signal switching occurs to the SDI signal input by the front end, for example, the frame rate switching, the SDI2HDMI chip needs to be reset again, a corresponding register is configured through the FPGA_SPI data channel according to the switching state, and when normal display occurs, parameter data analyzed by the SDI2HDMI chip can be read. That is, if the state switching of the input signal of the SDI2HDMI chip (i.e., SDI input signal) occurs, for example: from 8K@60Hz, YUV420, switch to 8K@50Hz, YUV422. At this time, the SDI2HDMI chip needs to be adjusted with configuration parameters. And configuring a parameter register inside the SDI2HDMI chip through the FPGA_SPI. When the SDI2HDMI chip is switched to enter the working state. The FPGA can read parameters of the SDI signal analyzed by the SDI2HDMI chip through the FPGA_SPI data channel. That is, the SDI2HDMI chip also analyzes the parameters of the SDI signal before converting the SDI signal into the HDMI signal, and buffers the parameters in an internal register.

Regarding each HDMI equalizing chip, the main function is to remove jitter of the output HDMI signal, enhance signal quality, and the chip has an independent reset signal: HDMI equalization_rst. The HDMI equalization_rst reset signal may cut off the HDMI signal output to the FPGA. And enabling an HDMI RX module in the FPGA to receive the HDMI input signal again, so that the re-locking of the HDMI input signal is completed, and the uncertain state caused by the abnormal HDMI data is eliminated.

Regarding FPGA:

the HDMI RX module in the FPGA is, as described above, a master module for HDMI signal analysis, where the HDMI RX modules on each path work independently, and send an HDMI hot plug signal (i.e., an HPD signal, which may also be referred to herein as an hdmi_hpd signal) to the hdmi_5v_en control module in the SDI-to-HDMI adapter board, and an SDI interrupt module, such as the HDMI1_hpd sent by the HDMI1_rx module, the HDMI2_hpd sent by the HDMI2_rx module, the HDMI3_hpd sent by the HDMI3_rx module, and the HDMI4_hpd sent by the HDMI4_rx module shown in fig. 12, according to the received data.

And the reset control module: resetting different modules according to the abnormal signal state (or called signal type), for example, when any SDI2HDMI chip is abnormal (namely, the SDI2HDMI_LOCK signal sent by the SDI2HDMI chip is out of LOCK), sending the SDI2HDMI_RST signal to the abnormal SDI2HDMI chip; when any HDMI equalizing chip is abnormal (by comparing the time sequence information of the SDI signal stored in the reference register with the auxiliary information stored in the auxiliary information register, if the time sequence information is inconsistent with the auxiliary information, the HDMI equalizing chip on the access is abnormal and/or the HDMI RX module is abnormal), an HDMI equalizing_RST signal is sent to the abnormal HDMI equalizing chip, so that different chips on any access can be independently controlled to reset, not all the chips on the whole access are reset, unnecessary operation is avoided, and the working efficiency is improved.

SDI interrupt module: and collecting and analyzing the interrupt signals related to the SDI-HDMI adapter plate, namely the interrupt source module. Specifically, for example: receiving the sdi_lock signal sent by any one of the SDI equalization chips (i.e., a first indication signal for indicating whether the SDI equalization chip is operating normally), receiving the SDI2hdmi_lock signal sent by any one of the SDI2HDMI chips (i.e., a second indication signal for indicating whether the SDI2HDMI chip is operating normally), and receiving the hdmi_hpd signal sent by any one of the HDMI RX modules, and so on.

SPI module: and configuring and reading the register data of each SDI2HDMI chip, and storing the time sequence information obtained by analyzing the SDI2HDMI chip into a reference register. That is, the SDI2HDMI chip parses the parameter information of the SDI input signal while performing data conversion. For example, a line valid signal, a field valid signal of one image, and store these data in a register inside the SDI2HDMI chip. And the SPI module reads parameter information from the SDI2HDMI internal register through an SPI line, and the time sequence parameter data read from the SDI2HDMI chip by the SPI module can write the parameter information into the parameter register through writing operation.

Comparison module: the function is the same as that of the comparison module, auxiliary information obtained by analysis of the HDMI RX module is compared with information in a reference register, and the comparison result is fed back to the SDI interrupt module.

Auxiliary information register: and the function is the same as that of the auxiliary information register, and the HDMI auxiliary information analyzed by the HDMI RX module is stored.

The DDR read-write module comprises a DDR read module and a DDR write module, and the DDR read-write operation is completed.

An input signal state prompting module: the function is the same as that of the input signal state prompt module, and different prompt messages are provided according to error conditions.

Functional module: the function is the same as the function module, and image quality processing is performed.

And a data selection module: the function is the same as that of the data selection module, and the data output by the selection module is from an input end (namely the data output by the function module) or from the input signal state prompting module.

VBO TX module (i.e., video signal transmission processing module): the VBO TX module has the same functions as the VBO TX module, and comprises the VBO TX ctrl module and the VBO TX phy module, and the VBO signals are transmitted to the rear end for display after parallel-serial conversion.

The workflow of the display system shown in fig. 12, as shown in fig. 13, includes:

s131, starting up;

s132, powering up the system;

And S133, initializing each chip on the SDI-to-HDMI adapter plate by the MCU in the SDI-to-HDMI adapter plate through the daisy chain SPI.

S134, SDI_LOCK signal locking of an SDI equalization chip, which represents stable signal input;

s135, resetting and resetting the SDI2HDMI chip, and starting normal operation;

after the S136, SDI2hdm_lock signal is locked, it indicates that the SDI2HDMI chip completes data conversion, works normally, and can send a normal HDMI signal.

S137, resetting and resetting the HDMI equalization chip.

S138, supplying power to an HDMI_5V power supply;

s139, loading the FPGA netlist.

S1310, resetting and resetting the HDMI RX module.

S1311, VBO TX module resets and de-resets.

S1312, powering on backlight of a display screen end;

s1313, displaying the image normally.

Fig. 14 shows an abnormal error correction processing flow in the SDI-HDMI adapter, specifically executed by the MCU core control unit, where the flow includes:

s141, in the normal display process, when the trigger signal of the SDI interrupt module is received, the data selection module controls the display screen to be switched to blue screen display, and image abnormality is avoided.

S142, firstly detecting whether the SDI_LOCK signal is locked or not, if not, executing step S143, and when the SDI_LOCK signal is detected to be locked, executing step S144;

S143, detecting whether the SDI_LOCK signal is always out of LOCK;

if the lock is always lost, no signal is accessed, the input signal state prompting module prompts no signal receiving income;

if SDI_LOCK is high-low, the signal line connection is represented, but the signal is unstable, and the input signal state prompting module prompts that the signal is weak, which may be caused by poor contact or signal line damage.

And S144, when the SDI_LOCK signal is detected to be locked, further, detecting the working state of the SDI2HDMI chip, namely detecting whether the SDI2DHMI_LOCK signal is locked or not. If there is no lock, representing that the SDI2HDMI is not working properly, S145 is performed; otherwise, S146 is performed.

S145, resetting the SDI2HDM chip. If the SDI2HDMI_LOCK signal cannot be locked by resetting, the resetting time and the number of times exceed the preset value. Then the data cannot be parsed from the SDI2HDMI signal, and the input SDI signal may be a nonstandard SDI signal, so the control input signal state prompting module prompts the nonstandard SDI signal to be input.

S146, if the SDI_LOCK signal is locked, continuously detecting the state of the HDMI_HPD signal, namely judging whether the HDMI_HPD signal is unlocked, if so, executing S147, otherwise, executing S148;

S147, if the hdmi_hpd signal is detected to be out of lock, there are two possibilities: one is that the HDMI RX is not ready to receive HDMI data, at which point the HDMI RX is reset, clearing the error condition. Attempts to have HDMI RX receive HDMI data. Another case is: the failure of the FPGA to normally receive the hdmi_5v signal may be caused by disconnection of the HDMI connection between the SDI-HDMI adapter board and the FPGA.

In some embodiments, when the preset reset time of the HDMI RX is exceeded, the input signal status prompting module may be further controlled to output a prompting error message: the HDMI RX end is abnormal, not ready to receive the front-end HDMI data, or the HDMI signal line is disconnected.

S148, after detecting hdmi_hpd lock, only one interrupt trigger condition remains: the comparison module detects that the data is inconsistent, namely that the time sequence signal analyzed by the SDI2HDMI chip is inconsistent with the auxiliary information analyzed by the HDMI RX module, and at the moment, the data analyzed by the HDMI RX module is determined to be abnormal.

S149, controlling the reset control module to reset the HDMI equalization chip, so that the HDMI signal of the HDMI equalization chip is disconnected and retransmitted. And controlling the HDMI_5V to be powered down and powered up again, and clearing the abnormal state of the circuit related to the HDMI_5V signal. And finally, resetting the HDMI RX module, and judging whether the data comparison is consistent or not through the comparison module under the condition that the resetting is not overtime. If the reset is overtime, the data is still inconsistent, and the HDMI RX module is prompted to be incapable of correctly analyzing the data. If the data comparison of the comparison modules is consistent through the operation, the data selection module switches the data displayed at the rear end from the input signal state prompting module to the input data channel, namely, the display screen normally displays the data input at the front end.

The MCU on the SDI-HDMI adapter plate can initialize each chip on the SDI-HDMI adapter plate through the daisy chain SPI data channel. The main reasons for adopting the daisy chain SPI connection mode are as follows: the number of SPI ports on the MCU is limited to be insufficient. The disadvantage of the daisy-chain SPI connection is the slow serial communication speed of all chips. In order to accelerate the processing speed of the abnormal situation, the parallel SPI communication channel is led out from the FPGA end in the embodiment of the application.

The working flow of SPI data configuration reading and switching of the FPGA is shown in FIG. 15, and comprises the following steps:

s151, starting up;

s152, powering up the system;

s153, the MCU initializes each chip on the SDI-HDMI adapter plate through the daisy chain SPI data channel.

S154, normal display;

and S155, switching an SPI channel of the SDI2HDMI chip to an SPI module in the FPGA.

S156, resetting an SDI2HDMI chip;

and S157, after the reset of the SDI2HDMI chip is detected, the SPI module in the FPGA can reconfigure data for the SDI2HDMI chip. That is, after the SDI2HDMI chip is reset, the internal parameters of the chip are cleared, and if the SDI2HDMI chip is required to be re-operated, the parameter data needs to be reconfigured for the SDI2HDMI chip.

S158, triggering and locking SDI interruption;

and S159, after the SDI interrupt is triggered and locked, the SPI module in the FPGA reads the time sequence signal of the SDI2HDMI chip and stores the time sequence signal into a reference register for use by the comparison module.

In addition, when the sequence of the multiple signal lines is wrong, the state of the display image can be checked by virtue of the experience of a user, and the input signal line sequence is manually exchanged, but in an extreme case, the signal display can be made normal only by trying all the input signal line arrangements and combinations. Therefore, the embodiment of the application further provides that when the sequence of the input signal lines is wrong, the signal line sequence is input by adopting a one-key adjustment mode of playing the preset detection chart card, so that a great deal of manpower is saved, and the user experience is improved. Specific examples are as follows:

after all channel signals are normal, the problem of image display dislocation caused by inconsistent signal splitting and sending modes of an SDI-HDMI adapter plate (hereinafter referred to as an adapter plate) and an FPGA combined receiving mode also exists; or, the display image is dislocated due to the line sequence disorder of the input signal lines. Because the display system provided by the embodiment of the application is formed by splicing multiple paths of signals into one 8K image for display, the signal splitting and transmitting modes of the adapter plate and the signal combining and receiving modes of the FPGA are as follows:

The "field-like" arrangement shown in fig. 16: four signal channels (SDI_1, SDI_2, SDI_3, SDI_4, respectively), each channel transmitting 1/4 picture. The four pictures are arranged in an up-down and left-right manner to form a complete 8K image.

The arrangement of "Chinese character's" as shown in fig. 17: four channels (SDI_1, SDI_2, SDI_3, SDI_4, respectively), each transmitting 1/4 picture. The four pictures are sequentially arranged from left to right to form a complete 8K image.

The pixel cross arrangement is as shown in fig. 18: channel 1 transmits the 1 st, 2 nd pixels of the first line (i.e., the pictures of the first two pixels of the first line are both picture 1), and channel 2 transmits the 3 rd, 4 th pixels of the first line (i.e., the pictures of the 3 rd, 4 th pixels of the first line are both picture 2). Channel 3 transmits the 1 st and 2 nd pixels of the second line (i.e., the pictures of the first two pixels of the second line are both picture 3), and channel 4 transmits the 3 rd and 4 th pixels of the second line (i.e., the pictures of the 3 rd and 4 th pixels of the second line are both picture 4). Similarly, four channels cross-transmit an 8K image through pixels.

Based on the above arrangement, there are the following common errors:

a common first error: the split sending mode of the front-end input equipment is inconsistent with the receiving and combining mode of the FPGA, so that the display image is abnormal or misplaced. For example, the front end performs split transmission according to a "Chinese character ' tian ' type, and the FPGA performs reception and combination according to a" Chuan ' type. Then the back-end image will naturally show up unparallel.

A second type of error is common: the input signal lines are disordered, so that abnormal display is caused, for example, when the line sequence of the input signal lines is incorrect in a split combination mode of Chinese character 'Chuan' shape and Chinese character 'Tian' shape, the situation that 1/4 images of each path are misplaced can occur; under the pixel cross splitting combination mode, when the line sequence of the input signal line is incorrect, the problem of image display saw-tooth can occur. Take the example of displaying four input signals: four paths of input signals are used for calculating 24 connection input modes according to arrangement and combination. Especially when the pixels are arranged in a crossed manner, the problem of the disorder of the input signals occurs, and the error is difficult to be found by naked eyes, and if the arrangement and the combination are tried according to the arrangement in the step 24, a great deal of time is required for adjusting the signals normally. Moreover, when the transmission line of the input device is too long to confirm the sequence, it is more difficult to adjust the images correctly.

In order to solve the two types of errors, avoid consuming complicated manpower and improve the working efficiency, the embodiment of the application provides a method for automatically adjusting the input mode and the line sequence of image signals. As shown in fig. 19, the image card is a card integrating all of the arrangement pattern features (pixel cross feature, chinese character pattern arrangement feature), and the image card is divided into 8 total areas of 1 to 8. The upper left corner of each of the 8 regions contains a pixel cross arrangement split combination mode identification mark. Channel 1 transmits red pixels (R), channel 2 transmits green pixels (G), channel 3 transmits blue pixels (B), and channel 4 transmits yellow pixels (Y). The correct arrangement of the four channels in the upper left corner of each of the 8 regions, as shown in the "pixel cross feature" region of fig. 19, should be R, R, G, G, B, B, Y, Y for the 8 pixels, respectively, in left to right and top to bottom order.

When playing the test chart, the above-mentioned timing sequence detection module is further used for: firstly, whether a pixel image splitting and combining mode is a pixel cross arrangement mode is detected. Confirmation was made by detecting the upper left 8 pixels of each region. If the arrangement order of 8 pixels is disordered, as shown in fig. 20, the red positions of the channel 1 and the green positions of the channel 2 are changed, then the split combination mode of the image is first confirmed to be the pixel cross arrangement combination mode. In comparison with the standard graphic card shown in fig. 19, the positions of the green pixels and the red pixels are changed. It is judged that the order of the channel 1 and the channel 2 is wrong. The MCU core control unit will readjust the transfer sequence registers (i.e. control registers) of channel 1 and channel 2. In the embodiment of the application, how the data of each channel are transmitted, combined, arranged and combined, and the like are controlled by a single register, and the MCU controls the registers. Referring to fig. 20, the data arrangement merge module is used to swap the display positions of channel 1 and channel 2 according to the modified register, thereby displaying the correct image as shown in fig. 19.

If the pixel crossing arrangement mode is detected to be correct, the time sequence detection module can continuously detect whether the arrangement of the 'Chinese character' is correct. As shown in fig. 19, zones 1 and 5, zones 2 and 6, zones 3 and 7, and zones 4 and 8 constitute four "chinese character" feature areas. Regions 1 and 5 are images transmitted by channel 1: 1/4 red plus 3/4 black; regions 2 and 6 are images transmitted by channel 2: 1/2 red plus 1/2 black; regions 3 and 7 are images transmitted by channel 3: 3/4 blue plus 1/4 black; regions 2 and 6 are images transmitted by channel 4: all red.

As shown in fig. 21, the channel 1 and channel 2 positions are changed. The timing detection module first confirms that the split combination mode of the image is a 'Chinese character' type arrangement combination mode. And because of the areas 1 and 5, the positions of the display images are changed compared with the positions of the display images in the areas 2 and 6, and the channel 1 and the channel 2 are judged to be connected in sequence and wrong. The MCU core control unit will readjust the transfer sequence registers of channel 1 and channel 2. The data arrangement merge module swaps the display positions of channel 1 and channel 2 according to the modified registers, thereby displaying the correct image as shown in fig. 19.

If the pixel cross arrangement mode and the arrangement of the Chinese character 'Chuan' are detected to be correct, the time sequence detection module can continuously detect whether the arrangement of the Chinese character 'Tian' is correct or not. As shown in fig. 19, zones 1 and 2, zones 3 and 4, zones 5 and 6, zones 7 and 8, respectively, constitute four "field-like" feature areas. Region 1 and region 2 show images transmitted by channel 1; areas 3 and 4 display the images transmitted by the channel 2, and areas 5 and 6 display the images transmitted by the channel 3; areas 7 and 8 display images transmitted by channel 4.

As shown in fig. 22, the positions of the display images of the 1 and 2 areas and the 3 and 4 areas are changed. The timing detection module confirms that the split combination mode of the image is a 'field-shaped' arrangement combination mode. And the display image positions of the area 1, the area 2, the area 3 and the area 4 are changed, and the order of the channel 1 and the channel 2 is judged to be wrong, so that the MCU kernel control unit can readjust the transmission order register of the channel 1 and the channel 2. The data arrangement merge module swaps the display positions of channel 1 and channel 2 according to the modified registers, thereby displaying the correct image as shown in fig. 19.

Under the condition of uncertain arrangement and combination modes and line sequences, the method can be started through specific keys (for example, virtual option keys on a menu or physical keys on a machine, and the specific implementation mode is not limited), images can be quickly and correctly adjusted, the adjustment sequence can be stored in FLASH, and if equipment and an input mode are not replaced, the sequence is still memorized and processed according to the sequence after the next startup. If other equipment is replaced or the input line connection mode is replaced, the method can be used for line sequence adjustment, and the method can be called one-key adjustment.

In summary, the process for automatically adjusting the image display mode and the line sequence provided by the embodiment of the application comprises the following steps:

s231, after all channels are normally connected, the MCU kernel control unit controls the playing of the detection graphics card;

s232, firstly, the MCU kernel control unit detects whether the image pixel arrangement is correct according to the image card, and if not, the step S233 is executed; if so, step S234 is performed;

s233, the MCU core control unit controls the time sequence detection module to detect the pixel arrangement error sequence, and the correct arrangement parameters are written into the control register. The MCU kernel control unit controls the data arrangement merging module to rearrange the image pixel positions according to the newly configured pixel arrangement parameters, and outputs the rearranged image pixel positions to the rear-end display screen, so that the image display is normal.

In some embodiments, the MCU core control unit also stores new pixel arrangement parameters into FLASH.

Wherein the pixel arrangement parameter is an input data arrangement parameter. For example:

register name = mechanical order [7:0];

taking the Sichuan arrangement order as an example, if the mechanical_order=1;

the transmission sequence from left to right is as follows: channel 1, channel 2, channel 3, channel 4;

chanel_order＝2；

the transmission sequence from left to right is as follows: channel 4, channel 3, channel 2, channel 1;

and so on.

S234, if the arrangement of the detected pixels is correct, the MCU kernel control unit continuously controls the time sequence detection module to detect whether the arrangement of the 'Chuan' is correct, and if not, the step S235 is executed; if so, executing step S236;

s235, the time sequence detection module detects whether each 1/4 column data is complete, if so, the time sequence detection module detects the wrong arrangement order of the Sichuan fonts, and writes the correct arrangement parameters into the control register. The MCU kernel control unit controls the data arrangement and combination module to rearrange the image positions according to the newly configured Sichuan style data transmission adjustment parameters, and outputs a rear-end display screen to realize normal image display.

In some embodiments, the MCU core control unit stores the new Sichuan style arrangement parameters into FLASH. If every 1/4 column of data is incomplete, executing step S238;

S236, if the arrangement of the 'Chinese character' is detected to be correct, the MCU core control unit continuously controls the time sequence detection module to detect whether the arrangement of the 'Chinese character' is correct, and if so, the step S237 is executed; otherwise, step S238 is performed.

And S237, if the field font arrangement is correct, maintaining the default setting and displaying a correct image.

S238, if the arrangement of the 'Sichuan' is detected to be incorrect and 1/4 columns are also abnormal, or when the arrangement sequence of the 'Sichuan' is correct but the arrangement of the 'Tian' is detected to be incorrect, the time sequence detection module detects the arrangement error sequence of the Tian 'and writes the correct Tian' arrangement parameters into the control register. The MCU kernel control unit controls the data arrangement and combination module to rearrange the image positions according to the newly configured field font adjustment parameters, and the back-end image display is normal.

In some embodiments, the MCU core control unit stores the new field-type arrangement parameters into FLASH.

Accordingly, in some embodiments, an FPGA provided by the embodiment of the present application includes:

the MCU kernel control unit is used for controlling the judgment of the current display image of the display screen according to the preset graphics card in the following aspects: whether the pixel arrangement is correct, whether the Sichuan character pattern arrangement is correct, and whether the Tian character pattern arrangement is correct; when any aspect is incorrect, image adjustment is carried out according to the preset graphic card control, and the output is controlled to display the correct image.

In some embodiments, the FPGA further comprises: a timing detection module;

and the MCU kernel control unit is used for controlling the time sequence detection module to judge the current display image of the display screen.

In some embodiments, the FPGA further comprises: a control register;

the MCU kernel control unit is also used for controlling the timing sequence detection module to write correct image parameters into a control register according to the preset graphic card based on the judgment result of the timing sequence detection module.

In some embodiments, the FPGA further comprises: a data arrangement and combination module;

the MCU kernel control unit controls the data arrangement and combination module to read the correct image parameters from the control register;

and the data arrangement and combination module adjusts the image according to the correct image parameters and outputs the adjusted image to a display screen for display.

In some embodiments, the FPGA further comprises: FLASH;

the MCU kernel control unit is also used for writing the correct image parameters into the FLASH.

It should be noted that, in the embodiment of the present application, the division of the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice. In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Embodiments of the present application provide a computing device, which may be specifically a desktop computer, a portable computer, a smart phone, a tablet computer, a personal digital assistant (Personal Digital Assistant, PDA), and the like. The computing device may include a central processing unit (Center Processing Unit, CPU), memory, input/output devices, etc., the input devices may include a keyboard, mouse, touch screen, etc., and the output devices may include a display device, such as a liquid crystal display (Liquid Crystal Display, LCD), cathode Ray Tube (CRT), etc.

The memory may include Read Only Memory (ROM) and Random Access Memory (RAM) and provides the processor with program instructions and data stored in the memory. In the embodiment of the present application, the memory may be used to store a program of any of the methods provided in the embodiment of the present application.

The processor is configured to execute any of the methods provided by the embodiments of the present application according to the obtained program instructions by calling the program instructions stored in the memory.

Embodiments of the present application also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the method of any of the above embodiments. The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

An embodiment of the present application provides a computer readable storage medium storing computer program instructions for use in an apparatus provided in the embodiment of the present application, where the computer program instructions include a program for executing any one of the methods provided in the embodiment of the present application. The computer readable storage medium may be a non-transitory computer readable medium.

The computer-readable storage medium can be any available medium or data storage device that can be accessed by a computer, including, but not limited to, magnetic storage (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical storage (e.g., CD, DVD, BD, HVD, etc.), and semiconductor storage (e.g., ROM, EPROM, EEPROM, nonvolatile storage (NAND FLASH), solid State Disk (SSD)), etc.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A display system, the display system comprising:

wherein, the FPGA includes:

a control register for storing the error correction instruction;

2. The display system of claim 1, wherein the SDI-to-HDMI adapter plate is further configured to: monitoring the connection condition of the SDI signal and the conversion condition of converting the SDI signal into the HDMI signal in real time, and generating an INT_SDI interrupt signal and transmitting the INT_SDI interrupt signal to the interrupt source module when the conditions of abnormal SDI signal switching, SDI signal disconnection or SDI signal conversion exist;

the MCU kernel control unit triggers an error correction instruction corresponding to the type interrupt signal according to the type of the interrupt signal in the interrupt source module, and comprises the following steps: when the INT_SDI interrupt signal exists in the interrupt source module, generating an error correction instruction for controlling an SDI2HDMI module in the SDI-to-HDMI adapter plate to reset, and sending the error correction instruction to the control register.

3. The display system according to claim 1, wherein the HDMI signal receiving and processing module includes an HDMI phy module, and the HDMI phy module is configured to parse a synchronous clock signal included in the HDMI signal, and generate a pll_lock interrupt signal and send the pll_lock interrupt signal to the interrupt source module when the synchronous clock signal is unstable;

the MCU kernel control unit triggers an error correction instruction corresponding to the type interrupt signal according to the type of the interrupt signal in the interrupt source module, and comprises the following steps: and when the PLL_lock interrupt signal exists in the interrupt source module, generating an error correction instruction for controlling the HDMI signal receiving processing module to reset and sending the error correction instruction to the control register.

4. The display system of claim 1, wherein the FPGA further comprises: a reference register, an auxiliary information register and a comparison module;

the SDI-to-HDMI adapter plate is further configured to: analyzing the auxiliary information of the SDI signal in real time, and storing the auxiliary information of the SDI signal into the reference register in real time;

the HDMI signal receiving and processing module comprises an HDMI ctrl module, wherein the HDMI ctrl module is used for analyzing auxiliary information of video signals contained in the HDMI signals and sending the auxiliary information to the auxiliary information register for storage;

the comparison module is used for comparing the auxiliary information of the SDI signal stored in the reference register with the auxiliary information stored in the auxiliary information register, and generating an interrupt signal with abnormal auxiliary information and sending the interrupt signal to the interrupt source module when the auxiliary information is inconsistent;

the MCU kernel control unit triggers an error correction instruction corresponding to the type interrupt signal according to the type of the interrupt signal in the interrupt source module, and comprises the following steps: and when the interrupt source module is determined to have the interrupt signal with the abnormal auxiliary information, generating an error correction instruction for controlling the HDMI ctrl module to reset and sending the error correction instruction to the control register.

5. The display system of claim 4, wherein the FPGA further comprises:

the timing detection module is used for detecting timing parameters, comparing the timing parameters with the auxiliary information of the SDI signals stored in the reference register, judging whether the HDMI signals are resolved correctly or not, and generating timing error interrupt signals and sending the timing error interrupt signals to the interrupt source module when the HDMI signals are not resolved correctly;

the MCU kernel control unit triggers an error correction instruction corresponding to the type interrupt signal according to the type of the interrupt signal in the interrupt source module, and comprises the following steps: and when the time sequence error interrupt signal exists in the interrupt source module, generating an error correction instruction for controlling the HDMI ctrl module to reset and sending the error correction instruction to the control register.

6. The display system of claim 4, wherein the HDMI ctrl module is further to: analyzing an HPD signal in the HDMI signal and sending the HPD signal to the interrupt source module;

the MCU core control unit is further used for: and when the HPD signal existing in the interrupt source module is determined to be at a low level, controlling the display screen to display no-signal input prompt information.

7. The display system of claim 1, wherein the video signal transmission processing module is further configured to: detecting the connection condition of a port for sending signals to the display screen by the FPGA, and generating a TX_lock interrupt signal and sending the TX_lock interrupt signal to the interrupt source module when the connection is abnormal;

the MCU kernel control unit triggers an error correction instruction corresponding to the type interrupt signal according to the type of the interrupt signal in the interrupt source module, and comprises the following steps: and when the TX_lock interrupt signal exists in the interrupt source module, generating an error correction instruction for controlling the video signal transmission processing module to reset and sending the error correction instruction to the control register.

8. The display system of claim 1, wherein the SDI-to-HDMI adapter plate is further configured to: transmitting an HDMI_5V signal to the interrupt source module;

the MCU core control unit is further used for: and when the interrupt source module is determined to have the HDMI_5V signal at the low level, controlling a display screen to display no-signal input prompt information.

9. The display system of claim 1, wherein the FPGA further comprises:

and the input signal state prompting module is used for outputting corresponding prompting information to a display screen for display according to the error correction instruction.

10. A reference monitor, characterized in that it comprises the display system of any of claims 1-9.