CN116645908A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN116645908A CN116645908A CN202310798478.2A CN202310798478A CN116645908A CN 116645908 A CN116645908 A CN 116645908A CN 202310798478 A CN202310798478 A CN 202310798478A CN 116645908 A CN116645908 A CN 116645908A
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- 238000010586 diagram Methods 0.000 description 19
- 230000009286 beneficial effect Effects 0.000 description 11
- 239000002184 metal Substances 0.000 description 10
- 239000010409 thin film Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The embodiment of the invention discloses a display panel and a display device, wherein the display panel comprises a display area and a non-display area surrounding the display area, the area adjacent to the display area comprises an invalid display area, and the invalid display area comprises a plurality of dummy sub-pixels. The display panel further comprises at least one signal bus line which at least partially overlaps the inactive display area in a direction perpendicular to the plane of the display panel. According to the technical scheme, at least one signal bus is arranged in the invalid display area, so that the at least one signal bus and the invalid display area are at least partially overlapped, the occupied space of the signal bus to the non-display area is reduced, and the narrow frame is facilitated to be realized.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
The existing display panel is usually provided with a plurality of groups of driving circuits, a signal bus connected with the driving circuits is usually arranged in a non-display area, the occupied space of the non-display area is large, the conventional mode at present is to realize a narrow frame by the process capability of compression cutting and packaging, but the process capability of compression cutting and packaging can cause loss to a certain extent on the yield of products.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for reducing the occupied space of at least one signal bus to a non-display area and are beneficial to realizing a narrow frame of the display panel.
In a first aspect, an embodiment of the present invention provides a display panel, where the display panel includes a display area and a non-display area surrounding the display area, and an area of the display area adjacent to the non-display area includes an inactive display area, and the inactive display area includes a plurality of dummy sub-pixels;
at least one signal bus line, along the direction perpendicular to the plane of the display panel, at least one signal bus line at least partially overlaps the inactive display area.
In a second aspect, an embodiment of the present invention further provides a display apparatus, including the display panel in the first aspect.
The display panel provided by the invention comprises a display area and a non-display area surrounding the display area, wherein the area adjacent to the non-display area comprises an invalid display area, and the invalid display area comprises a plurality of dummy sub-pixels. The display panel further comprises at least one signal bus line which at least partially overlaps the inactive display area in a direction perpendicular to the plane of the display panel. Therefore, at least one signal bus is arranged in the invalid display area between the display area and the non-display area, namely, along the direction perpendicular to the plane where the display panel is positioned, the at least one signal bus at least partially overlaps with the invalid display area, so that the occupied space of the signal bus to the non-display area is reduced, and the narrow frame of the display panel is facilitated to be realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, a brief description will be given below of the drawings required for the embodiments or the description of the prior art, and it is obvious that although the drawings in the following description are specific embodiments of the present invention, it is obvious to those skilled in the art that the basic concepts of the device structure, the driving method and the manufacturing method, which are disclosed and suggested according to the various embodiments of the present invention, are extended and extended to other structures and drawings, and it is needless to say that these should be within the scope of the claims of the present invention.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is an enlarged schematic view of area A of FIG. 1;
FIG. 3 is another enlarged schematic view of area A of FIG. 1;
FIG. 4 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view taken along the BB' direction in FIG. 3;
fig. 6 is a circuit diagram of a first pixel circuit according to an embodiment of the present invention;
fig. 7 is a circuit diagram of another first pixel circuit according to an embodiment of the present invention;
fig. 8 is a circuit diagram of another first pixel circuit according to an embodiment of the present invention;
fig. 9 is a circuit diagram of another first pixel circuit provided in an embodiment of the invention;
FIG. 10 is a circuit diagram of another first pixel circuit provided in an embodiment of the invention;
fig. 11 is a circuit diagram of another first pixel circuit according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described by means of implementation examples with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the basic concepts disclosed and suggested by the embodiments of the present invention are within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and fig. 2 is an enlarged schematic diagram of a region a in fig. 1. Referring to fig. 1 and 2, the display panel includes a display area AA and a non-display area BB surrounding the display area AA, and an area adjacent to the display area AA and the non-display area BB includes an inactive display area CC including a plurality of dummy sub-pixels 10. The display panel further comprises at least one signal bus 20, the at least one signal bus 20 at least partially overlapping the inactive display area CC in a direction perpendicular to the plane of the display panel.
Specifically, as shown in fig. 1 and 2, the display panel includes a display area AA and a non-display area BB. The display area AA includes an effective display area (not shown) and an ineffective display area CC. The effective display area may include a plurality of subpixels 30 for display, a plurality of gate lines, and a plurality of data lines (not shown in the above figures). The sub-pixels 30 may be arranged in an array, a plurality of gate lines may extend in the first direction X, a plurality of data lines may extend in the second direction Y, and orthographic projections of the plurality of gate lines and the plurality of data lines on the substrate may cross to form a plurality of circuit regions, and one pixel circuit may be disposed in each circuit region. The plurality of data lines are electrically connected to the plurality of pixel circuits, and the plurality of data lines may be configured to supply data signals to the plurality of pixel circuits. The plurality of gate lines are electrically connected to the plurality of pixel circuits, and the plurality of gate lines may be configured to provide gate control signals to the plurality of pixel circuits. The gate control signal may include a scan signal, or may include a scan signal and a light emission control signal. And further the sub-pixels 30 are driven to emit light by the pixel circuits in the sub-pixels 30. The ineffective display area CC is located in an area adjacent to the non-display area BB in the display area AA, that is, the ineffective display area CC is located between the effective display area and the non-display area BB, and the ineffective display area CC includes a plurality of dummy sub-pixels 10, and the plurality of dummy sub-pixels 10 are not used for display.
Note that, the pixel circuit may be disposed in the ineffective display area CC, but the pixel circuit is not electrically connected to the light emitting element in the dummy sub-pixel 10, or the light emitting element in the dummy sub-pixel 10 is not disposed with a light emitting layer, so that the dummy sub-pixel 10 is ensured not to be used for display.
The non-display area BB surrounds the display area AA in which various circuit structures and wirings are disposed, and in particular, the non-display area BB may include an upper frame area, a lower frame area, a left frame area, and a right frame area. Power supply traces, such as PVEE signal lines, may be disposed in the non-display area BB, and the PVEE signal lines are disposed around the display area AA to provide negative power supply signals for the display panel; a plurality of data fanout lines can be arranged in the lower frame area of the non-display area BB, and can be electrically connected with a plurality of data lines of the display area AA so as to provide data signals for a plurality of pixel circuits through the data fanout lines; virtual wiring can be further arranged in the lower frame area of the non-display area BB, so that the balance of wiring of the film layer where the whole display area AA is connected with the wiring is ensured, and reflection difference or film layer flatness difference caused by unbalanced wiring are avoided.
The display panel further includes a plurality of signal buses 20, and in one embodiment, the signal buses 20 may be reference signal buses, where the reference signal buses are electrically connected to the pixel circuits of the effective display area, so as to provide reference signals for the sub-pixels 30 of the effective display area through the reference signal buses. In the prior art, the signal bus is located in the left frame area and the right frame area of the non-display area BB, so that the signal bus occupies a larger space in the non-display area BB, which is not beneficial to realizing the narrow frame of the display panel.
Therefore, in the embodiment of the present invention, at least one signal bus 20 is disposed along the direction perpendicular to the plane where the display panel is located, so as to at least partially overlap the inactive display area CC, so that the signal bus located in the non-display area BB in the prior art is disposed in the inactive display area CC of the display area AA, where the inactive display area CC includes a plurality of dummy sub-pixels 10 that are not used for display, and further the signal bus 20 does not affect the inactive display area CC, and the occupation space of the signal bus 20 on the non-display area BB is reduced, thereby being beneficial to implementing a narrow frame of the display panel.
It should be noted that, the signal bus 20 is exemplified by the signal bus 20 as a reference signal bus in the above embodiment, but this is not limited thereto, and in other embodiments, the signal bus 20 may be a bias signal adjustment bus, and those skilled in the art may set the bias signal adjustment bus as required.
In summary, in an embodiment of the present invention, a display panel includes a display area and a non-display area surrounding the display area, where an area adjacent to the display area includes an inactive display area, and the inactive display area includes a plurality of dummy sub-pixels. The display panel further comprises at least one signal bus line which at least partially overlaps the inactive display area in a direction perpendicular to the plane of the display panel. Therefore, at least one signal bus is arranged in the invalid display area, the invalid display area is not used for displaying, the setting of the signal bus can not influence the invalid display area, the occupied space of the signal bus to the non-display area is reduced, and the narrow frame of the display panel is facilitated to be realized.
In yet another embodiment, fig. 3 is another enlarged schematic view of the area a in fig. 1, and referring to fig. 1 and 3, the signal bus 20 completely overlaps the inactive display area CC in a direction perpendicular to the plane of the display panel. Specifically, in an embodiment, the signal bus 20 may be completely disposed in the inactive display area CC, that is, along a direction perpendicular to the plane where the display panel is located, where the inactive display area CC covers the signal bus 20, so that the signal bus 20 and the inactive display area CC completely overlap, which can further reduce the space occupied by the signal bus 20 on the non-display area BB, and is beneficial to realizing a narrow frame of the panel.
On the basis of the above embodiment, fig. 4 is a schematic structural diagram of another display panel provided in the embodiment of the present invention, and referring to fig. 4, the non-display area BB includes a first frame BB1 and a second frame BB2, where the first frame BB1 and the second frame BB2 are disposed opposite to each other. The ineffective display area CC includes a first ineffective display area CC1 and a second ineffective display area CC2, the first ineffective display area CC1 is adjacent to the first frame BB1, and the second ineffective display area CC2 is adjacent to the second frame BB 2. The signal bus 20 includes a first signal bus 210 and a second signal bus 220, the first signal bus 210 at least partially overlapping the first inactive display area CC1 in a direction perpendicular to a plane in which the display panel is located, and the second signal bus 220 at least partially overlapping the second inactive display area CC 2.
Specifically, the non-display area BB includes a first frame BB1 and a second frame BB2, where the first frame BB1 may be a left frame area of the non-display area BB, the second frame BB2 may be a right frame area of the non-display area BB, the first frame BB1 and the second frame BB2 are oppositely disposed, and a scan driving circuit may be disposed in the first frame BB1 and the second frame BB2, so that scan signals and light emission control signals are provided for the pixel circuits through a plurality of gate lines. The invalid display area CC includes a first invalid display area CC1 and a second invalid display area CC2, wherein the first invalid display area CC1 is adjacent to the first frame BB1, that is, the first invalid display area CC1 is located between the valid display area and the first frame BB 1; the second ineffective display area CC2 is adjacent to the second frame BB2, that is, the second ineffective display area CC2 is located between the effective display area and the second frame BB2, and neither the first ineffective display area CC1 nor the second ineffective display area CC2 is used for display. The signal bus 20 includes a first signal bus 210 and a second signal bus 220, that is, along a direction perpendicular to a plane where the display panel is located, where the first signal bus 210 at least partially overlaps the first ineffective display area CC1, that is, the first signal bus 210 is located in the first ineffective display area CC1, since the first ineffective display area CC1 is not used for displaying, the arrangement of the first signal bus 210 does not affect the first ineffective display area CC1, and the occupied space of the first signal bus 210 on the first frame BB1 is reduced; similarly, the second signal bus 220 at least partially overlaps the second ineffective display area CC2, that is, the second signal bus 220 is located in the second ineffective display area CC2, and since the second ineffective display area CC2 is not used for displaying, the arrangement of the second signal bus 220 does not affect the second ineffective display area CC2, and reduces the occupied space of the second signal bus 220 on the second frame BB2, so that, by arranging the first signal bus 210 at least partially overlaps the first ineffective display area CC1 along the direction perpendicular to the plane where the display panel is located, the occupied space of the signal bus 20 on the first frame BB1 and the second frame BB2 can be reduced, which is beneficial to realizing the left and right narrow frames of the display panel.
Optionally, in an embodiment, along a direction perpendicular to the plane of the display panel, the first signal bus 210 completely overlaps the first inactive display area CC1, and the second signal bus 220 completely overlaps the second inactive display area CC2, so that the occupied space of the signal bus 20 on the first frame BB1 and the second frame BB2 can be further reduced, which is beneficial to realizing the left and right narrow frames of the panel.
For example, fig. 5 is a schematic cross-sectional view along BB' in fig. 3, and as shown in fig. 3 and 5, the display area AA includes a plurality of sub-pixels 30, the sub-pixels 30 include a first pixel circuit 310 and a first light emitting element 320, the first pixel circuit 310 is electrically connected to the first light emitting element 320, the first pixel circuit 310 is used to drive the first light emitting element 320 to emit light, the dummy sub-pixel 10 includes a second pixel circuit 110 and a second light emitting element 120, and the second pixel circuit 110 is not connected to the second light emitting element 120.
Specifically, as shown in fig. 3 and 5, the display area AA includes a plurality of sub-pixels 30, the plurality of sub-pixels 30 are used for display, and the sub-pixels 30 include a first pixel circuit 310 and a first light emitting element 320. The display panel further includes a substrate 01, and a driving circuit layer 02 on one side of the substrate 01, and the first pixel circuit 310 is located on the driving circuit layer 02. The first pixel circuit 310 is configured to provide a driving current to the first light emitting element 320, where the first pixel circuit 310 includes at least one thin film transistor, and the structure of the thin film transistor may be a top gate structure or a bottom gate structure. Here, the structure of the thin film transistor is not limited. As shown in fig. 5, if the structure of the thin film transistor is a bottom gate structure, the driving circuit layer 02 includes a buffer layer, an active layer, a first metal layer, an insulating layer, and a second metal layer stacked in this order along the direction of the substrate 01 toward the driving circuit layer 02. The first metal layer may be a gate metal layer, the second metal layer may be a source/drain metal layer, a channel of the thin film transistor is located in the active layer, a gate of the thin film transistor is located in the gate metal layer, and a source and a drain of the thin film transistor are located in the source/drain metal layer, so that the first light emitting element 320 is driven to emit light by the thin film transistor in the first pixel circuit 310. Further, the ineffective display area CC includes a plurality of dummy sub-pixels 10, and the dummy sub-pixels 10 are not used for display. The dummy sub-pixel 10 includes a second pixel circuit 110 and a second light emitting element 120, wherein the second pixel circuit 110 is also located in the driving circuit layer 02, and the circuit structure of the second pixel circuit 110 is the same as that of the first pixel circuit 310, but the second pixel circuit 110 is not connected to the second light emitting element 120, so that the driving circuit of the second pixel circuit 110 cannot be provided to the second light emitting element 120, thereby ensuring that the dummy sub-pixel 10 is not used for display.
Note that, the signal bus 20 may be disposed in the inactive display area CC, specifically, may be disposed in the second metal layer of the driving circuit layer 02, but the present invention is not limited thereto, and in other embodiments, the signal bus 20 may be disposed in the third metal layer.
Fig. 6 is a circuit diagram of a first pixel circuit according to an embodiment of the present invention, and as shown in fig. 6, the first pixel circuit 310 includes a first initialization module 311, a second initialization module 312, a driving module 313, a data writing module 314, and a threshold compensation module 315. The control terminal of the driving module 313 is electrically connected to the first node N, the first terminal of the driving module 313 is electrically connected to the first power voltage signal line PVDD, and the second terminal of the driving module 313 is electrically connected to the first electrode of the first light emitting element 320. The control end of the first initialization module 311 is connected to the first scan signal line S1, the first end of the first initialization module 311 is electrically connected to the first reference signal line Vref1, and the second end of the first initialization module 311 is electrically connected to the first node N or the second end of the driving module 313. The control end of the data writing module 314 is electrically connected to the second scan signal line S2, the first end of the data writing module 314 is electrically connected to the data signal line Vdata, and the second end of the data writing module 314 is electrically connected to the first end of the driving module 313. The control end of the threshold compensation module 315 is electrically connected to the third scan signal line S3, the first end of the threshold compensation module 315 is electrically connected to the second end of the driving module 313, and the second end of the threshold compensation module 315 is electrically connected to the first node N. The control end of the second initialization module 312 is electrically connected to the fourth scan signal line S4, the first end of the second initialization module 312 is electrically connected to the second reference signal line Vref2, and the second end of the second initialization module 312 is electrically connected to the first electrode of the first light emitting element 320.
Specifically, the first pixel circuit 310 may be a 7T1C circuit, as shown in fig. 6, and the first pixel circuit 310 includes a first initialization module 311, a second initialization module 312, a driving module 313, a data writing module 314, and a threshold compensation module 315. The driving module 313 may include a third transistor M3, the data writing module 314 may include a second transistor M2, a first end of the second transistor M2 is connected to the data signal line Vdata, the threshold compensating module 315 includes a fourth transistor M4, a control end of the fourth transistor M4 is electrically connected to the third scan signal line S3, the data writing module 314 and the threshold compensating module 315 are both located on a writing path of the data signal, and are used for writing the data signal into the first end of the second transistor M2 to control the working state of the second transistor M2, thereby controlling the magnitude of the driving current and controlling the light emitting brightness of the first light emitting element 320. The first initialization module 311 includes a fifth transistor M5, a control terminal of the fifth transistor M5 is electrically connected to the first scan signal line S1, a first terminal of the fifth transistor M5 is electrically connected to the first reference signal line Vref1, and a second terminal of the fifth transistor M5 is electrically connected to a control terminal of the third transistor M3 for resetting a control terminal potential of the driving module 313. The second initialization module 312 includes a seventh transistor M7, where a control end of the seventh transistor M7 is electrically connected to the fourth scan signal line S4, a first end of the seventh transistor M7 is electrically connected to the second reference signal line Vref2, and a second end of the seventh transistor M7 is electrically connected to the first light emitting element 320, so as to reset an anode of the first light emitting element 320, and avoid that the light emission of the previous frame affects the light emission of the current frame. Further, the first pixel circuit 310 emits light to a control module including a first transistor M1 and a sixth transistor M6. The first transistor M1 and the sixth transistor M6 are located between the first power voltage signal line PVDD and the second power voltage signal line PVEE, the emission control signal line EMIT is electrically connected to the control terminal of the first transistor M1 and the control terminal of the sixth transistor M6, the first pixel circuit 310 is electrically connected to the first light emitting element 320, and the emission control signal outputted through the emission control signal line EMIT controls the operation state of the first light emitting element 320 in the light emitting stage.
With continued reference to fig. 6, the signal bus 20 includes a first reference signal bus 230 and a second reference signal bus 240, the first reference signal line Vref1 is electrically connected to the first reference signal bus 230, and the second reference signal line Vref2 is electrically connected to the second reference signal bus 240.
Specifically, the first signal line Vref1 is electrically connected to the first reference signal bus 230, and the first signal line Vref1 is electrically connected to the first end of the first initialization module 311, and the second end of the first initialization module 311 is electrically connected to the control end of the driving module 313, so that the first reference signal is provided to the control end of the driving module 313 through the first reference signal bus 230 to reset the control end of the driving module 313. The second reference signal line Vref2 is electrically connected to the second reference signal bus 240, and the second reference signal line Vref2 is electrically connected to the first end of the second initialization module 312, and the second end of the second initialization module 312 is electrically connected to the first light emitting element 320, so that the second reference signal is provided to the second initialization module 312 through the second reference signal bus 240 to reset the anode of the first light emitting element 320. On the basis of the above embodiment, the first reference signal bus 230 and the second reference signal bus 240 may be disposed in the inactive display area, so that on the basis of ensuring normal signal transmission, the occupation space of the first reference signal bus 230 and the second reference signal bus 240 on the non-display area may be reduced, which is beneficial to realizing a narrow frame of the display panel.
In yet another embodiment, fig. 7 is a circuit diagram of another first pixel circuit according to an embodiment of the present invention, where, as shown in fig. 7, the signal bus 20 includes a first reference signal bus 230 and a second reference signal bus 240, and the first reference signal line Vref1 and the second reference signal line Vref2 are electrically connected to the same signal bus 20.
Specifically, the first signal line Vref1 is electrically connected to the first end of the first initialization module 311, the second end of the first initialization module 311 is electrically connected to the control end of the driving module 313, the second reference signal line Vref2 is electrically connected to the first end of the second initialization module 312, the second end of the second initialization module 312 is electrically connected to the first light emitting element 320, and by setting the first reference signal line Vref1 and the second reference signal line Vref2 to be both connected to the same signal bus 20 (the first reference signal bus 230 or the second reference signal bus 240), so that the same signal bus 20 provides reference signals for the control end of the driving module 313 and the second initialization module 312, respectively, to reset the control end of the driving module 313 and the anode of the first light emitting element 320, and the control manner is simple. On the basis of the above embodiment, the signal bus 20 (the first reference signal bus 230 or the second reference signal bus 240) electrically connected to the first reference signal line Vref1 and the second reference signal line Vref2 is disposed in the inactive display area, the inactive display area is not used for display, and further the arrangement of the signal bus does not affect the inactive display area, and the occupation space of the signal bus to the non-display area is reduced, which is beneficial to realizing the narrow frame of the display panel.
Fig. 8 is a circuit diagram of another first pixel circuit according to an embodiment of the present invention, and as shown in fig. 8, the first pixel circuit 310 includes a first initialization module 311, a second initialization module 312, a driving module 313, a data writing module 314, a threshold compensation module 315, and a bias adjustment module 316. The control terminal of the driving module 313 is electrically connected to the first node N, the first terminal of the driving module 313 is electrically connected to the first power voltage signal line PVDD, and the second terminal of the driving module 313 is electrically connected to the first electrode of the first light emitting element 320. The control end of the first initialization module 311 is connected to the first scan signal line S1, the first end of the first initialization module 311 is electrically connected to the first reference signal line Vref1, and the second end of the first initialization module 311 is electrically connected to the first node N or the second end of the driving module 313. The control end of the data writing module 314 is electrically connected to the second scan signal line S2, the first end of the data writing module 314 is electrically connected to the data signal line Vdata, and the second end of the data writing module 314 is electrically connected to the first end of the driving module 313. The control end of the threshold compensation module 315 is electrically connected to the third scan signal line S3, the first end of the threshold compensation module 315 is electrically connected to the second end of the driving module 313, and the second end of the threshold compensation module 315 is electrically connected to the first node N. The control end of the second initialization module 312 is electrically connected to the fourth scan signal line S4, the first end of the second initialization module 312 is electrically connected to the second reference signal line Vref2, the second end of the second initialization module 312 is electrically connected to the first electrode of the first light emitting element 320, the control end of the bias adjustment module 316 is electrically connected to the fifth scan signal line S5, the first end of the bias adjustment module 316 is electrically connected to the bias adjustment signal line V0, and the second end of the bias adjustment module 316 is electrically connected to the first end or the second end of the driving module 313.
Specifically, the first pixel circuit 310 may also be an 8T1C circuit, as shown in fig. 8, where the first pixel circuit 310 includes a first initialization module 311, a second initialization module 312, a driving module 313, a data writing module 314, a threshold compensation module 315, and a bias adjustment module 316. The driving module 313 may include a third transistor M3, the data writing module 314 may include a second transistor M2, a first end of the second transistor M2 is connected to the data signal line Vdata, the threshold compensating module 315 includes a fourth transistor M4, a control end of the fourth transistor M4 is electrically connected to the third scan signal line S3, the data writing module 314 and the threshold compensating module 315 are both located on a writing path of the data signal, and are used for writing the data signal into the first end of the second transistor M2 to control the working state of the second transistor M2, thereby controlling the magnitude of the driving current and controlling the light emitting brightness of the first light emitting element 320. The first initialization module 311 includes a fifth transistor M5, a control terminal of the fifth transistor M5 is electrically connected to the first scan signal line S1, a first terminal of the fifth transistor M5 is electrically connected to the first reference signal line Vref1, and a second terminal of the fifth transistor M5 is electrically connected to a control terminal of the third transistor M3 for resetting a control terminal potential of the driving module 313. The second initialization module 312 includes a seventh transistor M7, where a control end of the seventh transistor M7 is electrically connected to the fourth scan signal line S4, a first end of the seventh transistor M7 is electrically connected to the second reference signal line Vref2, and a second end of the seventh transistor M7 is electrically connected to the first light emitting element 320, so as to reset an anode of the first light emitting element 320, and avoid that the light emission of the previous frame affects the light emission of the current frame. The bias adjustment module 316 may include an eighth transistor M8, a first end of the eighth transistor M8 is electrically connected to the bias adjustment signal line V0, a control end of the eighth transistor M8 is electrically connected to the fifth scan signal line S5, and a second end of the eighth transistor M8 is electrically connected to the first end or the second end of the driving module 313, so that the bias adjustment module 316 provides a bias adjustment signal to the driving module 313 to adjust the bias state of the first pixel circuit 310. Further, the first pixel circuit 310 emits light to a control module including a first transistor M1 and a sixth transistor M6. The first transistor M1 and the sixth transistor M6 are located between the first power voltage signal line PVDD and the second power voltage signal line PVEE, the emission control signal line EMIT is electrically connected to the control terminal of the first transistor M1 and the control terminal of the sixth transistor M6, the first pixel circuit 310 is electrically connected to the first light emitting element 320, and the emission control signal outputted through the emission control signal line EMIT controls the operation state of the first light emitting element 320 in the light emitting stage.
Alternatively, with continued reference to fig. 8 based on the above embodiment, the signal bus 20 includes a first reference signal bus 230, a second reference signal bus 240, and a bias adjustment signal bus 250, the first reference signal line Vref1 is electrically connected to the first reference signal bus 230, the second reference signal line Vref2 is electrically connected to the second reference signal bus 240, and the bias adjustment signal line V0 is electrically connected to the bias adjustment signal bus 250.
Specifically, the first signal line Vref1 is electrically connected to the first reference signal bus 230, and the first signal line Vref1 is electrically connected to the first end of the first initialization module 311, and the second end of the first initialization module 311 is electrically connected to the control end of the driving module 313, so that the first reference signal is provided to the control end of the driving module 313 through the first reference signal bus 230 to reset the control end of the driving module 313. The second reference signal line Vref2 is electrically connected to the second reference signal bus 240, and the second reference signal line Vref2 is electrically connected to the first end of the second initialization module 312, and the second end of the second initialization module 312 is electrically connected to the first light emitting element 320, so that the second reference signal is provided to the second initialization module 312 through the second reference signal bus 240 to reset the anode of the first light emitting element 320. The bias adjustment signal line V0 is electrically connected to the bias adjustment signal bus 250, and a first end of the bias adjustment module 316 is electrically connected to the bias adjustment signal line V0, and a second end of the bias adjustment module 316 is electrically connected to the first end or the second end of the driving module 313, so that a bias adjustment signal is provided to the bias adjustment module 316 through the bias adjustment signal bus 250 to adjust the bias state of the first pixel circuit 310. On the basis of the above embodiment, the first reference signal bus 230, the second reference signal bus 240 and the bias adjustment signal bus 250 may be all disposed in an inactive display area, the inactive display area is not used for display, and further, the arrangement of the first reference signal bus 230, the second reference signal bus 240 and the bias adjustment signal bus 250 does not affect the inactive display area, and the occupation space of the first reference signal bus 230, the second reference signal bus 240 and the bias adjustment signal bus 250 on the non-display area is reduced, which is beneficial to realizing the narrow frame of the display panel.
In yet another embodiment, fig. 9 is a circuit diagram of another first pixel circuit according to an embodiment of the present invention, where, as shown in fig. 9, the signal bus 20 includes a reference signal bus 260 and a bias adjustment signal bus 250, and the first reference signal line Vref1 and the second reference signal line Vref2 are electrically connected to the reference signal bus 260, and the bias adjustment signal line V0 is electrically connected to the bias adjustment signal bus 250.
Specifically, the first signal line Vref1 is electrically connected to the first end of the first initialization module 311, the second end of the first initialization module 311 is electrically connected to the control end of the driving module 313, the second reference signal line Vref2 is electrically connected to the first end of the second initialization module 312, the second end of the second initialization module 312 is electrically connected to the first light emitting element 320, and by setting the first reference signal line Vref1 and the second reference signal line Vref2 to be electrically connected to the reference signal bus 260, so that the reference signal bus 260 provides reference signals for the control end of the driving module 313 and the second initialization module 312 respectively, so as to reset the control end of the driving module 313 and the anode of the first light emitting element 320, and the control mode is simple. The bias adjustment signal line V0 is electrically connected to the bias adjustment signal bus 250, a first end of the bias adjustment module 316 is electrically connected to the bias adjustment signal line V0, a second end of the bias adjustment module 316 is electrically connected to the first end or the second end of the driving module 313, and a bias adjustment signal is provided to the bias adjustment module 316 through the bias adjustment signal bus 250 to adjust the bias state of the first pixel circuit 310. On the basis of the above embodiment, the reference signal bus 260 and the bias adjustment signal bus 250 may be both disposed in an inactive display area, where the inactive display area is not used for display, so that the arrangement of the reference signal bus 260 and the bias adjustment signal bus 250 does not affect the inactive display area, and the occupation space of the reference signal bus 260 and the bias adjustment signal bus 250 on the non-display area is reduced, which is beneficial to realizing a narrow frame of the display panel.
Fig. 10 is a circuit diagram of another first pixel circuit according to an embodiment of the present invention, and as shown in fig. 10, a second end of the bias adjustment module 316 is electrically connected to a first end of the driving module 313, and the data writing module 314 is multiplexed into the bias adjustment module 316. Specifically, as shown in fig. 10, the data writing module 314 is multiplexed into the bias adjustment module 316, that is, the second scan signal line S2 can control the on and off of the second transistor M2, so that when the second scan signal line S2 controls the second transistor M2 to be on, a data signal is provided to the driving module 313 through the data signal line Vdata. In addition, the fifth control signal line S5 may also control the on and off of the second transistor M2, so that when the fifth scan signal line S5 controls the second transistor M2 to be turned on, the bias adjustment signal line V0 provides the bias voltage to the driving module 313, and thus, by multiplexing the data writing module 314 into the bias adjustment module 316, the circuit structure is simple, and the control mode is simple.
In yet another embodiment, fig. 11 is a circuit diagram of another first pixel circuit according to an embodiment of the present invention. As shown in fig. 11, a second end of the first initialization module 311 is electrically connected to a second end of the driving module 313, and the first initialization module 311 is multiplexed as the bias adjustment module 316. Specifically, the first initialization module 311 is multiplexed to the bias adjustment module 316, that is, the first scan signal line S1 can control the on and off of the fifth transistor M5, so that when the first scan signal line S1 controls the on of the fifth transistor M5, a reference signal is provided to the second end of the driving module 313 through the first reference signal line Vref 1. In addition, the fifth control signal line S5 may also control the second transistor M2 to be turned on and off, so that the bias voltage is provided to the driving module 313 through the bias adjustment signal line V0 when the fifth scan signal line S5 controls the second transistor M2 to be turned on. Therefore, when the initialization is needed, the fourth transistor M4 and the fifth transistor M5 can be turned on, and when the bias state of the first pixel circuit 310 needs to be adjusted, only the fifth transistor M5 is turned on, and further, the first initialization module 311 is multiplexed into the bias adjustment module 316, so that the circuit has a simple structure and a simple control mode.
Based on the above inventive concept, the embodiment of the invention also provides a display device. Fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 12, the display device includes the display panel 200 in the above-described embodiment. The display device includes the display panel 200 according to any embodiment of the present invention, so the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel 200 provided by the embodiment of the present invention, and will not be described herein. The display device may be, for example, an electronic device such as a mobile phone, a computer, a smart wearable device (e.g., a smart watch), and a vehicle-mounted display device, which is not limited in the embodiment of the present invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (13)
1. A display panel, comprising:
a display region and a non-display region surrounding the display region, the region of the display region adjacent to the non-display region including an inactive display region including a plurality of dummy sub-pixels;
at least one signal bus line, along the direction perpendicular to the plane of the display panel, at least one signal bus line at least partially overlaps the inactive display area.
2. The display panel of claim 1, wherein the signal bus completely overlaps the inactive display region in a direction perpendicular to a plane in which the display panel lies.
3. The display panel of claim 1, wherein the non-display area comprises a first bezel and a second bezel, the first bezel and the second bezel being disposed opposite each other;
the invalid display area comprises a first invalid display area and a second invalid display area, the first invalid display area is adjacent to the first frame, and the second invalid display area is adjacent to the second frame;
the signal buses comprise a first signal bus and a second signal bus, the first signal bus at least partially overlaps the first ineffective display area along the direction perpendicular to the plane where the display panel is located, and the second signal bus at least partially overlaps the second ineffective display area.
4. The display panel according to claim 1, wherein the display region includes a plurality of sub-pixels including a first pixel circuit and a first light emitting element, the first pixel circuit being electrically connected to the first light emitting element, the first pixel circuit being for driving the first light emitting element to emit light;
the dummy sub-pixel includes a second pixel circuit and a second light emitting element, the second pixel circuit being unconnected to the second light emitting element.
5. The display panel of claim 4, wherein the first pixel circuit comprises a first initialization module, a second initialization module, a driving module, a data writing module, and a threshold compensation module;
the control end of the driving module is electrically connected with a first node, the first end of the driving module is electrically connected with a first power supply voltage signal line, and the second end of the driving module is electrically connected with a first electrode of the first light-emitting element;
the control end of the first initialization module is connected with a first scanning signal line, the first end of the first initialization module is electrically connected with a first reference signal line, and the second end of the first initialization module is electrically connected with the first node or the second end of the driving module;
the control end of the data writing module is electrically connected with the second scanning signal line, the first end of the data writing module is electrically connected with the data signal line, and the second end of the data writing module is electrically connected with the first end of the driving module;
the control end of the threshold compensation module is electrically connected with a third scanning signal line, the first end of the threshold compensation module is electrically connected with the second end of the driving module, and the second end of the threshold compensation module is electrically connected with the first node;
the control end of the second initialization module is electrically connected with the fourth scanning signal line, the first end of the second initialization module is electrically connected with the second reference signal line, and the second end of the second initialization module is electrically connected with the first electrode of the first light-emitting element.
6. The display panel of claim 5, wherein the signal bus comprises a first reference signal bus and a second reference signal bus, the first reference signal line being electrically connected to the first reference signal bus, the second reference signal line being electrically connected to the second reference signal bus.
7. The display panel of claim 5, wherein the signal bus comprises a first reference signal bus and a second reference signal bus, the first reference signal line and the second reference signal line each being electrically connected to the same signal bus.
8. The display panel of claim 4, wherein the first pixel circuit comprises a first initialization module, a second initialization module, a driving module, a data writing module, a threshold compensation module, and a bias adjustment module;
the control end of the driving module is electrically connected with a first node, the first end of the driving module is electrically connected with a first power supply voltage signal line, and the second end of the driving module is electrically connected with a first electrode of the first light-emitting element;
the control end of the first initialization module is connected with a first scanning signal line, the first end of the first initialization module is electrically connected with a first reference signal line, and the second end of the first initialization module is electrically connected with the first node or the second end of the driving module;
the control end of the data writing module is electrically connected with the second scanning signal line, the first end of the data writing module is electrically connected with the data signal line, and the second end of the data writing module is electrically connected with the first end of the driving module;
the control end of the threshold compensation module is electrically connected with a third scanning signal line, the first end of the threshold compensation module is electrically connected with the second end of the driving module, and the second end of the threshold compensation module is electrically connected with the first node;
the control end of the second initialization module is electrically connected with a fourth scanning signal line, the first end of the second initialization module is electrically connected with a second reference signal line, and the second end of the second initialization module is electrically connected with the first electrode of the first light-emitting element;
the control end of the offset adjustment module is electrically connected with the fifth scanning signal line, the first end of the offset adjustment module is electrically connected with the offset adjustment signal line, and the second end of the offset adjustment module is electrically connected with the first end or the second end of the driving module.
9. The display panel of claim 8, wherein the signal bus comprises a first reference signal bus, a second reference signal bus, and a bias adjustment signal bus, the first reference signal line electrically connected to the first reference signal bus, the second reference signal line electrically connected to the second reference signal bus, the bias adjustment signal line electrically connected to the bias adjustment signal bus.
10. The display panel of claim 8, wherein the signal bus comprises a reference signal bus and a bias adjustment signal bus, the first reference signal line and the second reference signal line each being electrically connected to the reference signal bus, the bias adjustment signal line being electrically connected to the bias adjustment signal bus.
11. The display panel of claim 8, wherein the second end of the bias adjustment module is electrically connected to the first end of the drive module, and the data writing module is multiplexed as the bias adjustment module.
12. The display panel of claim 8, wherein a second end of the first initialization module is electrically connected to a second end of the driving module, the first initialization module being multiplexed as the bias adjustment module.
13. A display device comprising the display panel according to any one of claims 1 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310798478.2A CN116645908A (en) | 2023-06-30 | 2023-06-30 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310798478.2A CN116645908A (en) | 2023-06-30 | 2023-06-30 | Display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116645908A true CN116645908A (en) | 2023-08-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310798478.2A Pending CN116645908A (en) | 2023-06-30 | 2023-06-30 | Display panel and display device |
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| Country | Link |
|---|---|
| CN (1) | CN116645908A (en) |
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2023
- 2023-06-30 CN CN202310798478.2A patent/CN116645908A/en active Pending
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