CN115941416B - Tracking and receiving control device based on time synchronization - Google Patents
Tracking and receiving control device based on time synchronization Download PDFInfo
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Abstract
The invention belongs to the technical field of signal transmission and discloses a tracking and receiving control device and method based on time synchronization, wherein the device comprises a time service acquisition module, a sampling clock generation module, a sampling clock control module, a channel merging module, a baseband data decoding module, a clock driving module, a display control module which are integrated in an FPGA chip, and a photoelectric conversion receiving module, an amplifying module, a filtering shaping module and a BD/GPS time service receiving module which are arranged outside the FPGA chip.
Description
Technical Field
The invention discloses a tracking reception control device based on time synchronization, belongs to the technical field of signal transmission, and particularly relates to the technical field of tracking reception control devices based on time synchronization.
Background
Secure transmission of signals has historically been one of the most important technologies in the field of communications. In unmanned aerial vehicles, electronic interception and information collection which are commonly used at present, people are further reminded of the safety problem of communication. The security and reliability in data transmission may directly affect the trend or even success or failure of war. From an economic point of view, the secure transmission of signals may have a significant impact on countries, enterprises and individuals.
It has been reported that 2021 worldwide network crimes incur losses in excess of $ 6 trillion. In order to improve the security and reliability of signal transmission, efforts are constantly being made to prevent data from being lost or destroyed by expanding the latest technical means. From the current technical means, it is a common idea to encrypt the signal in transmission and to protect the channel of the transmitted signal, the objective being not to let the other party capture the signal, but to not obtain useful content from the signal even if it is captured.
However, the above-mentioned technology is relatively common, so that an illegal person can intercept information through a fixed code speed, and the synchronous tracking in the transmission process cannot be realized, and the carrier hopping is easy to be captured by the other party, so that the method is very unsafe.
Disclosure of Invention
The invention aims at: the tracking and receiving control device based on time synchronization is provided to solve the problem that the prior information cannot be synchronously tracked in the transmission process, and the carrier hopping is easy to be captured by the other party.
The technical scheme adopted by the invention is as follows:
a tracking reception control device based on time synchronization comprises a tracking reception control device based on time synchronization and a tracking reception control method based on time synchronization;
The tracking and receiving control device based on time synchronization comprises a time service acquisition module, a sampling clock generation module, a sampling clock control module, a channel merging module, a baseband data decoding module, a clock driving module, a display control module, a photoelectric conversion receiving module outside an FPGA chip, an amplifying module, a filtering shaping module and a BD/GPS time service receiving module;
The tracking reception control method based on time synchronization comprises the following steps: a multipath synchronous receiving control method of signals, a control method of baseband sampling frequency signal generation and a baseband digital demodulation control method.
In the technical scheme of the application, the BD/GPS time service receiving module receives the current standard Beijing time downloaded by a satellite, and outputs the time to the time service acquisition module in the FPGA chip, wherein a local time signal generated by an external crystal oscillator clock is continuously refreshed, so that the local time is strictly consistent with the current standard Beijing time, and the control time of baseband data frame demodulation is obtained. In addition, a sampling clock generating module in the FPGA chip generates m (m=1, 2, 3, …) sampling frequency signals required for decoding a baseband data frame, and under the control of the current standard time, the sampling clock controlling module combines the m sampling frequency signals into n (n=1, 2, 3, …) sampling frequency groups, the number of sampling frequencies in each sampling frequency group is j (j=1, 2, 3, …), and one sampling frequency is used as the sampling frequency of the baseband data frame for decoding in different time periods according to the sampling frequency number in turn; a photoelectric conversion receiving module outside an FPGA chip converts line signals distributed to k wireless, FSO or optical fiber carrier frequency bands in turn according to time slots into high-frequency modulation electric signals, the received weak high-frequency modulation electric signals are amplified to a preset value through an amplifying module, the high-frequency carrier waves are removed through a filtering shaping module, baseband data transmission signals acceptable by the FPGA chip are output, the signals are combined into a path of continuous transmission baseband digital signals through a channel combining module in the FPGA chip, and h-bit data are extracted from the signals after the signals are decoded through a baseband data decoding module, so that original data sent by a sending end are restored and output. In addition, in order to monitor the working state of the system conveniently, the clock driving module is utilized to obtain a display driving clock signal by dividing the frequency of the input external crystal oscillator clock, and then the display control module displays the current time of the time synchronization control signal, the baseband sampling frequency number selected by the current time and the currently received data;
The multipath synchronous receiving control method of the signals is that signals received by time slot fragments on k different wireless, FSO or optical fiber carrier frequency band channels are received, amplified, demodulated, filtered and shaped by corresponding k line receiving devices, then changed into intermittent digital baseband modulation signals transmitted by time slot fragments, and then sent to a channel merging module in an FPGA chip, and the digital baseband modulation signals received by time slot fragments input by the channels are integrated by a combiner to be one path of continuous digital baseband modulation signals, and then output to a baseband data decoding module;
the control method for the baseband sampling frequency signal generation includes that firstly, a clock signal output by a crystal oscillator is utilized to generate local base time including time, minute, second, millisecond and the like in an FPGA chip, then a BD/GPS time service receiving module is utilized to obtain standard Beijing time including time, minute, second, millisecond and the like, and the time is output to an FPAG chip as calibration time, so that the time generated by a local circuit is consistent with the standard Beijing time, and because the time is also the control time of a transmitting end, the time scales of a communication receiving end and the transmitting end are completely consistent, and the time is used as a time synchronous control signal for controlling digital carrier waves and sampling frequency selection simultaneously by two communication parties; on the other hand, m (m=1, 2,3, …) different sampling frequency signals are generated by using the FPGA chip, and the m sampling frequency signals are combined into n (n=1, 2,3, …) sampling frequency groups, the number of sampling frequencies in each sampling frequency group is j (j=1, 2,3, …), and the sampling frequencies are numbered in sequence so as to be called and displayed according to the numbers; selecting control signals by using externally input sampling frequency groups, selecting specified sampling frequency groups, and selecting frequencies specified by sampling frequency numbers in the specified groups by using time synchronization control signals in an FPGA chip;
The baseband digital demodulation control method refers to that when the baseband data decoding module does not receive data, a high-level direct current signal which indicates that a transmission line is in an idle state at present is received at ordinary times; when data is received, firstly, the jump characteristic of the input signal from high level to low level is received, then a counter driven by sampling frequency and with the counting range of 8+ (h+1+1) multiplied by 16 pulses is used for determining the position of the sampling signal, sampling and receiving a start bit, h-bit data, a parity check bit and a stop bit are carried out at the midpoint position of each bit of data, and finally, the correct h-bit data is obtained through parity check operation, is stored in a temporary storage and is output to external equipment in parallel, and is simultaneously output to a display control circuit for display.
Furthermore, the time service acquisition module extracts the current time received from the BD/GPS time service receiving module as time service time, and simultaneously generates a local time signal by an external crystal oscillator clock, and then continuously refreshes the local time by using the time service time to ensure that the local time is consistent with the time service time, so as to obtain the control time of demodulating the baseband data frame;
the sampling clock generation module generates various carrier signals required by decoding the baseband data frames;
the sampling clock control module combines m (m=1, 2, 3, …) sampling frequency signals into n (n=1, 2, 3, …) sampling frequency groups under the control of the current standard time, the number of carriers in each sampling frequency group is j (j=1, 2, 3, …), and the sampling frequency groups are alternately decoded as the sampling frequency of the base band data frame in different time periods according to the sampling frequency numbers.
Furthermore, the channel combining module combines k paths of signals which are transmitted according to time slots after the high-frequency demodulation and are input from the outside into one path of continuous transmission baseband digital signals in the FPGA chip.
The baseband data decoding module acquires all bits in a frame through the middle positions of a sampling start bit, a data bit, a parity check bit and a stop bit, extracts h bits of data from the bits, decodes the received baseband data, and restores and outputs original data sent by a sending end;
The clock driving module obtains a display driving clock signal by dividing an input external crystal oscillator clock;
the display control module is used for displaying key signals in the working process of the system, so that the working condition of the system can be mastered conveniently at any time, and the display content comprises: the time synchronization control signal comprises the current time, the baseband carrier frequency number selected by the current time and the current received data.
The BD/GPS time service receiving module receives the current standard Beijing time downloaded by the satellite and outputs the time to the FPGA chip;
the photoelectric conversion receiving module converts line signals distributed to k wireless, FSO or optical fiber carrier frequency bands in turn according to time slots into high-frequency carrier electric signals;
the amplification module is used for receiving the weak high-frequency carrier electric signal and amplifying the weak high-frequency carrier electric signal to a preset value;
and the filtering and shaping module filters high-frequency carrier components in the amplified high-frequency carrier electric signals, and then obtains baseband data transmission signals through the wave shaping circuit and outputs the baseband data transmission signals to the channel merging module of the FPGA chip.
Further, the method for controlling multipath synchronous receiving of signals further comprises the steps of:
The first step: signals received by time slots from k different wireless, FSO or optical fiber carrier frequency band channels are received, amplified, demodulated, filtered and shaped by corresponding k line receiving devices, and then become discontinuous digital baseband modulation signals transmitted by time slots;
And a second step of: k paths of intermittent digital baseband modulation signals are parallelly fed into a channel merging module in an FPGA chip, digital baseband modulation signals received by time slot interruption input by each channel are integrated through a combiner to form one path of continuous transmission digital baseband modulation signals, and then the continuous transmission digital baseband modulation signals are output to a baseband data decoding module.
Further, the control method for generating the baseband sampling frequency signal further comprises the following steps:
The first step: generating local base time in the FPGA chip by using a clock signal output by the crystal oscillator, wherein the local base time comprises time such as time, minute, second, millisecond and the like, and the time is used as initial reference time for receiving data by the system;
And a second step of: the BD/GPS time service receiving module is utilized to obtain standard Beijing time including time of time, minute, second, millisecond and the like, and the time is output to the FPAG chip to be used as calibration time;
and a third step of: refreshing the local reference time by using the calibration time of BD/GPS time service, so that the time generated by a local circuit is consistent with the standard Beijing time, and the time scales of a communication receiving end and a transmitting end are completely consistent, thereby being used as a time synchronization control signal for simultaneously controlling digital carrier and sampling frequency selection by two communication parties;
Fourth step: generating m different digital sampling signals in an FPGA chip by using a clock signal output by a local crystal oscillator, and combining m (m=1, 2,3, …) sampling signals into n (n=1, 2,3, …) sampling frequency groups, wherein the number of sampling frequencies in each sampling group is j (j=1, 2,3, …), and the sampling frequencies are numbered in sequence so as to be called and displayed according to the numbers; the sampling frequencies in each sampling frequency grouping can be different frequencies, or the same frequency or partial same frequency;
Fifth step: selecting control signals by using externally input sampling frequency groups, selecting specified sampling frequency groups, and selecting frequencies specified by sampling frequency numbers in the specified groups by using time synchronization control signals in an FPGA chip; because the time synchronous control signal is continuously and synchronously changed with the control signal of the transmitting end, the sampling frequency of the receiving end is also continuously and synchronously changed with the carrier frequency of the transmitting end, so that the digital carrier and the sampling frequency of both communication parties are synchronously tracked and changed all the time.
Further, the baseband digital demodulation control method further comprises the following steps:
the first step: when the data is not received, the baseband data decoding module receives a high-level direct current signal, which indicates that the transmission line is in an idle state at present, and no data can be received;
And a second step of: when data is received, the input end is changed from high level to low level, and the duration of the low level is 16 periods of time for the digital carrier signal, namely the duration of one data bit, which indicates that the reception of one frame of data is started;
And a third step of: a counter with a counting range of 8+ (h+1+1) multiplied by 16 pulses is designed by taking a digital carrier frequency signal as a driving clock, and the counter starts to count after the input end of a baseband data decoding module is changed from high level to low level, wherein h is the length of a data frame appointed by a transmitting end;
Fourth step: when the counter counts to 8 clock pulses, the counter indicates that the clock pulse is currently at the midpoint of the start bit of the data frame, the input start bit signal is sampled, if the clock pulse is 0, the input start bit signal is actually the start bit of the received data frame, the input signal is sampled once every 16 pulses and corresponds to the midpoint position of the data bit, the sampling result is sent into a temporary storage for storage, and after the h-bit data is received, the 1-bit parity check bit and the 1-bit frame termination identification bit are received;
Fifth step: and performing exclusive OR operation on the 1-bit data received and the parity check bit which is pre-agreed and coordinated by the transmitting end, if the exclusive OR operation result of the h-bit data is the same as the received parity check bit, indicating that the h-bit data is correctly received, outputting the data stored in the temporary storage to external equipment in parallel, and simultaneously outputting the data to a display control circuit for display.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
1. The Beijing time received by the BD/GPS time service receiving module and the local time generated by the FPGA chip can be modified into standard time, and the time controls the sampling frequency of the baseband to change continuously along with the change of time so as to track the continuous change of the code speed of the baseband data at the transmitting end, and the other party is difficult to intercept with a fixed code speed, so that the channel is protected from the bottom layer; secondly, the baseband frame designed according to the special format has independent data frame start-stop identification marks which are only known by the user, and the sampling is carried out at the midpoint position of each bit, so that the phase protection of 8 sampling frequency pulses of each bit of data can be provided; thirdly, after the signals received by the circuit are subjected to photoelectric conversion, amplification, filtering and shaping, high-frequency carrier components can be removed, direct-current components in the baseband data frames are restored, and when the baseband frames are decoded, the starting bit, the idle bit and the identification data bit mark can be captured through the change of the direct-current level; fourth, the channel merging module is used for merging the signals of different channels received by k different time slots into a path of complete transmission data signal, so that the loss of data is avoided, and the other party is difficult to obtain complete data, thereby realizing the second layer protection of the transmission channel. In addition, most of the hardware of the embodiment of the invention is realized in the FPGA chip, so that the system has high reliability, small volume and the capability of reprogramming in the system.
2. The beneficial effects of receiving the high-frequency modulation data according to k channels are that: the other party does not know how many channels are transmitting data, so that data cannot be received from k channels at the same time, so that the received data is incomplete, complete information cannot be obtained from the received data, and the difficulty of capturing signals by the other party is further increased due to the fact that the other party does not know how many channels are transmitting data, and the instantaneous change of a baseband carrier wave and a sampling frequency is added.
3. The control method for generating the baseband sampling frequency signal has the beneficial effects that: the digital carrier wave and sampling frequency used by each time period of both communication parties are the same, so that the modulation and demodulation of synchronous tracking of signals are facilitated; the digital carrier wave and sampling frequency used by the two communication parties at different time are different, so that the transmission signal is effectively prevented from being intercepted by the other party. The length of the synchronization period is determined by the time unit selected by the time synchronization control signal, and is agreed in advance according to the requirements of two communication parties, and can be units of time, minutes, seconds, milliseconds and the like. The smaller the unit, the faster the sampling frequency changes, and the harder it is for the other party to capture.
4. First, although the carrier frequencies of the two transmitting and receiving sides are the same, the phases may be different, which may cause sampling value errors, and sampling is performed at the midpoint of 16 sampling clock widths of each bit of data, so that phase protection of 8 clock widths can be obtained; secondly, the parity check of each frame of data can identify and find 1-bit data errors in transmission, so that error correction processing is convenient to carry out, and the reliability of data transmission and reception is ensured.
Drawings
Fig. 1 is a schematic diagram of a tracking reception control device based on time synchronization in an embodiment of the invention.
Fig. 2 is a schematic diagram of a connection relationship of an FSO photoelectric conversion receiving circuit, in which a tracking reception control device based on time synchronization is located outside an FPGA chip in an embodiment of the present invention.
Fig. 3 is a schematic diagram of a connection relationship of a receiving amplifier circuit of a tracking and receiving control device located outside an FPGA chip based on time synchronization in an embodiment of the present invention.
Fig. 4 is a schematic diagram of a connection relationship of a filtering shaping circuit of a tracking reception control device located outside an FPGA chip based on time synchronization in an embodiment of the present invention.
Fig. 5 is a schematic diagram of circuit connection relations of a timing acquisition module, a sampling clock generation module, a sampling clock control module, a channel combination module, a baseband data decoding module, a clock driving module and a display control module, in which a tracking and receiving control device based on time synchronization is located in an FPGA chip in an embodiment of the present invention.
Fig. 6 is a schematic diagram of a tracking reception control method based on time synchronization in an embodiment of the invention.
Fig. 7 is a schematic diagram of a method for controlling multipath synchronous reception of signals included in a method for controlling tracking reception based on time synchronization according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a control method for generating a baseband digital carrier signal according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of a control method for generating a baseband digital carrier signal according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1-9, in this embodiment, a tracking reception control device based on time synchronization is provided, which includes the following implementation methods:
the implementation steps of the tracking and signaling control device based on time synchronization in the embodiment of the tracking and signaling control device and method based on time synchronization are shown in fig. 1, and schematic diagrams of connection relations of functional modules in a circuit system implemented by the device are shown in fig. 2-5. The signal receiving step comprises the following steps:
Step 1: acquisition of high frequency carrier modulated signals from external FSO optical path transmission channels
As shown in fig. 2, the tracking reception control device based on time synchronization first obtains optical signals from 8 external free space optical communication FSO optical paths allocated by time slots from a transmitted end round stream, demodulates the optical signals by a photodiode LED, obtains weak high frequency carrier modulated electric signals from both ends of an R1, RP1 series circuit, and outputs the weak high frequency carrier modulated electric signals to a signal amplifier.
Step 2: amplifying weak high-frequency carrier modulated signals
As shown in fig. 3, the function of the receiving amplifier is to amplify the weak high-frequency carrier modulation signal output by the optical/electrical conversion receiving module and output the signal to the filter shaping circuit. The amplifier comprises a follower U2A which completes the impedance transformation function, U2B, U C can provide the maximum signal amplification amount of 2000 times, and RP2 is adjusted to control the amplification amount; c1 and C2 are blocking capacitors for preventing the mutual influence of working points between U2A, U and U2B, U C, R3 and R6 are balancing resistors of a differential amplifying circuit, and R2, R4, R5, R7 and RP2 respectively control the amplification factors of the two-stage amplifiers.
Step 3: high frequency carrier wave filtering and shaping
As shown in fig. 4, a high-frequency carrier wave filtering and shaping circuit diagram is shown, in which C3 completes dc isolation with the amplifier and changes the differential output of the amplifier into single-ended output; the integrating circuit formed by R8 and C4 filters the high-frequency carrier component in the high-frequency carrier modulation signal, and then the IC2D, IC E two-stage Schmitt trigger performs waveform shaping and outputs a baseband digital frame signal containing a direct-current component to the FPGA for decoding the baseband data frame.
Step 4: control circuit implementation of baseband data frame decoding
Fig. 5 shows a Vivado 2019.2 development platform of XILINX corporation in the united states, which selects Artix-7 series chip xc7a35tfgg484-2, a time service acquisition module, a sampling clock generation module, a sampling clock control module, a channel combination module, a baseband data decoding module, a clock driving module, a display control module and a circuit connection relationship between these modules, which are realized by using internal resources of the FPGA chip.
U2 in fig. 5 is a time service acquisition module, under the control of an external crystal oscillator clock clk and a reset signal rst, extracting current time serial data bdtimrx received from the BD/GPS time service receiving module as time service time, generating a local time signal by the external crystal oscillator clock at the same time, and continuously refreshing the local time by using the time service time to enable the local time to be consistent with the time service time, and obtaining control time timctr [3:0] of baseband data frame demodulation and outputting;
U1 in fig. 5 is a sampling clock generating module, which generates sampling signals fn [9:0] with 10 frequencies required for decoding the baseband data frame under the control of an external crystal oscillator clock clk and a reset signal rst;
u3 in fig. 5 is a sampling clock control module, and under the control of the external crystal oscillator clock clk, the reset signal rst, the external input frequency selection signal fsel10[3:0], and the control time timctr [3:0] of the demodulation of the baseband data frame, a sampling frequency with the number sfn [3:0] is selected from the baseband sampling signals fn [9:0] of 10 frequencies to be output as a demodulation sampling frequency clksp of baseband decoding. clksp stay at each frequency fn [9:0], which may be time, minutes, seconds, milliseconds, or other time, determined by the current standard time timctr [3:0 ];
u5 in fig. 5 is a channel merging module, which merges 8 paths of signals fso rx [7:0] which are transmitted according to time slots after high-frequency demodulation and are input from the outside into one path of continuous transmission baseband digital signals rx in an FPGA chip, and sends the baseband digital signals rx to a baseband data decoding module;
U4 in fig. 5 is a baseband data decoding module, which counts samples at the middle position of each start bit, data bit, parity check bit and stop bit by using a counter according to a reset signal rst and demodulation sampling frequency clksp of baseband decoding, so as to obtain all bits in a frame, extract h bits of data from the bits, realize decoding of received baseband data, and restore and output original data datarx [7:0] sent by a sending end;
u0 in fig. 5 is a clock driving module, and an input external crystal oscillator clock is divided into 1kHz to obtain a display driving clock signal clk_1khz;
U6 in fig. 5 is a display control module, under the action of a display driving clock signal clk_1khz and a reset signal rst, the key signals in the working process of the display system are displayed through a 4-bit nixie tube tut [3:0] and a seven-segment display sec [9:0], so that the working condition of the system can be conveniently mastered at any time, and the display contents comprise: the current time timctr [3:0] of the time synchronization control signal, the baseband sampling frequency number sfn [3:0] selected at the current time, the currently received data datarx [7:0].
The implementation steps of the tracking reception control method based on time synchronization in the embodiment of the tracking reception control device based on time synchronization are shown in fig. 6, and the signal receiving method is as follows: firstly, obtaining the output time of a BD/GPS time service module, synchronizing the local time to Beijing time completely consistent with a transmitting end, simultaneously generating m frequency signals for sampling baseband data frames, controlling the output according to time periods, receiving FSO optical signals from an external line, obtaining baseband transmission data frame signals through photoelectric conversion, amplifying, filtering and shaping, and decoding the baseband transmission data frames to restore the original data transmitted by the transmitting end.
In the embodiment of the tracking and signaling control device and method based on time synchronization shown in fig. 6, the tracking and signaling control method based on time synchronization includes a multipath synchronous receiving control method of signals, a control method of baseband sampling frequency signal generation, and a control method of baseband digital demodulation.
Fig. 7 is a schematic diagram of a method for controlling multipath synchronous reception of signals included in a method for controlling tracking reception based on time synchronization according to an embodiment of the present invention. The multipath synchronous receiving control method of the signals further comprises the steps of:
The first step: the signals received by the time slot-based channels from 8 different FSO carrier frequency bands are processed by the corresponding 8 line receiving photoelectric conversion circuit modules, the amplifying circuit modules and the filtering shaping modules, then clk_10kHz high-frequency carrier signals are filtered, and 8 paths of baseband data frame signals which are distributed with working time slots according to the clock clk_100deg.Hz are output;
and a second step of: the 8 paths of intermittent baseband data frame signals are parallelly fed into a channel merging module in the FPGA chip, digital baseband modulation signals received by time slot fragments input by all channels are integrated through a combiner to form one path of continuous transmission digital baseband modulation signals, and then the continuous transmission digital baseband modulation signals are output to a baseband data decoding module;
Fig. 8 is a schematic diagram of a control method for baseband sampling frequency signal generation, which is included in a tracking reception control method based on time synchronization according to an embodiment of the present invention, and the method further includes the following steps:
The first step: generating local base time in the FPGA chip by using a clock signal output by the crystal oscillator, wherein the local base time comprises time such as time, minute, second, millisecond and the like, and the time is used as initial reference time for receiving data by the system;
And a second step of: the BD/GPS time service receiving module is utilized to obtain standard Beijing time including time of time, minute, second, millisecond and the like, and the time is output to the FPAG chip to be used as calibration time;
and a third step of: refreshing the local reference time by using the calibration time of BD/GPS time service, so that the time generated by a local circuit is consistent with the standard Beijing time, and the time scales of a communication receiving end and a transmitting end are completely consistent, thereby being used as a time synchronization control signal for simultaneously controlling digital carrier and sampling frequency selection by two communication parties;
Fourth step: generating m different sampling frequency signals in an FPGA chip by utilizing a clock signal output by a local crystal oscillator, and combining m (m=1, 2, 3, …) sampling frequency signals into n (n=1, 2, 3, …) sampling frequency groups, wherein the number of sampling frequencies in each sampling frequency group is j (j=1, 2, 3, …), and the sampling frequencies are numbered in sequence so as to be called and displayed according to the numbers; the sampling frequencies in each carrier grouping can be different frequencies, or the same frequency or partial same frequency;
Fifth step: selecting control signals by using externally input sampling frequency groups, selecting specified sampling frequency groups, and selecting frequencies specified by sampling frequency numbers in the specified groups by using time synchronization control signals in an FPGA chip; because the time synchronous control signal is continuously and synchronously changed with the control signal of the transmitting end, the sampling frequency of the receiving end is also continuously and synchronously changed with the carrier frequency of the transmitting end, so that the digital carrier and the sampling frequency of both communication parties are synchronously tracked and changed all the time.
Fig. 9 is a schematic diagram of a control method for baseband sampling frequency signal generation, which is included in a tracking reception control method based on time synchronization in an embodiment of the present invention, and the method further includes the following steps:
the first step: when the data is not received, the baseband data decoding module receives a high-level direct current signal, which indicates that the transmission line is in an idle state at present, and no data can be received;
and a second step of: when data is received, the input end is changed from high level to low level, the duration of the low level is the duration of 16 periods of the sampling frequency signal, namely the duration of one data bit, and the duration of one data bit indicates that the reception of one frame of data is started;
And a third step of: a counter with a counting range of 8+ (h+1+1) multiplied by 16 pulses is designed by taking a sampling frequency signal as a driving clock, and the counter starts to count after the input end of a baseband data decoding module is changed from high level to low level, wherein h is the length of a data frame appointed by a transmitting end;
Fourth step: when the counter counts to 8 sampling frequency pulses, the counter indicates that the current sampling frequency pulse is at the midpoint of the start bit of the data frame, the input start bit signal is sampled, if the sampling frequency pulse is 0, the input start bit signal is actually the start bit of the received data frame, the input signal is sampled once every 16 pulses and is sent to a temporary storage for storage, and after the h-bit data is received, the 1-bit parity check bit and the 1-bit frame termination identification bit are received;
Fifth step: and performing exclusive OR operation on the 1-bit data received and the parity check bit which is pre-agreed and coordinated by the transmitting end, if the exclusive OR operation result of the h-bit data is the same as the received parity check bit, indicating that the h-bit data is correctly received, outputting the data stored in the temporary storage to external equipment in parallel, and simultaneously outputting the data to a display control circuit for display.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (3)
1. The tracking and receiving control device based on time synchronization is applied to an FPGA chip and is characterized in that: the device is used for realizing a tracking reception control method based on time synchronization;
The tracking reception control device based on time synchronization comprises: the system comprises a time service acquisition module, a sampling clock generation module, a sampling clock control module, a channel combination module, a baseband data decoding module, a clock driving module, a display control module, a photoelectric conversion receiving module, an amplifying module, a filtering shaping module and a BD/GPS time service receiving module which are arranged outside an FPGA chip;
The clock driving module is respectively connected with the time service acquisition module and the sampling clock generation module in a signal way, the BD/GPS time service receiving module is also connected with the time service acquisition module in a signal way, the time service acquisition module is connected with the sampling clock generation module in a signal way, the sampling clock generation module is connected with the sampling clock control module in a signal way, the sampling clock control module is connected with the baseband data decoding module in a signal way, the channel merging module is also connected with the baseband data decoding module in a signal way, and the baseband data decoding module is connected with the display control module in a signal way; the optical/electrical conversion receiving module, the amplifying module and the filtering shaping module are sequentially connected with signals, and the filtering shaping module is connected with the FPGA chip through signals;
The tracking reception control method based on time synchronization comprises the following steps: a multipath synchronous receiving control method of signals, a control method of baseband sampling frequency signal generation and a baseband digital demodulation control method;
The multipath synchronous receiving control method of the signals further comprises the following steps:
The first step: signals received by time slots from k different wireless, FSO or optical fiber carrier frequency band channels are received, amplified, demodulated, filtered and shaped by corresponding k line receiving devices, and then become discontinuous digital baseband modulation signals transmitted by time slots;
And a second step of: k paths of intermittent digital baseband modulation signals are parallelly fed into a channel merging module in an FPGA chip, digital baseband modulation signals received by time slot interruption input by each channel are integrated through a combiner to form one path of continuous transmission digital baseband modulation signals, and then the continuous transmission digital baseband modulation signals are output to a baseband data decoding module;
The control method for generating the baseband sampling frequency signal further comprises the following steps:
The first step: generating local base time in the FPGA chip by using a clock signal output by the crystal oscillator, wherein the local base time comprises time, minute, second and millisecond time, and the local base time is used as initial reference time for receiving data by the system;
And a second step of: the BD/GPS time service receiving module is utilized to obtain standard Beijing time including time, minute, second and millisecond time, and the time is output to the FPAG chip to be used as calibration time;
and a third step of: refreshing the local reference time by using the calibration time of BD/GPS time service, so that the time generated by a local circuit is consistent with the standard Beijing time, and the time scales of a communication receiving end and a transmitting end are completely consistent, thereby being used as a time synchronization control signal for simultaneously controlling digital carrier and sampling frequency selection by two communication parties;
Fourth step: generating m different digital sampling signals in an FPGA chip by using a clock signal output by a local crystal oscillator, combining the m sampling signals into n sampling frequency groups, wherein the number of sampling frequencies in each sampling group is j, and numbering the sampling frequencies in sequence so as to be called and displayed according to the numbers; the sampling frequencies in each sampling frequency grouping can be different frequencies, or the same frequency or partial same frequency;
wherein m=1, 2, 3, …; n=1, 2, 3, …; j=1, 2, 3, …;
Fifth step: selecting control signals by using externally input sampling frequency groups, selecting specified sampling frequency groups, and selecting frequencies specified by sampling frequency numbers in the specified groups by using time synchronization control signals in an FPGA chip; because the time synchronous control signal is continuously and synchronously changed with the control signal of the transmitting end, the sampling frequency of the receiving end is also continuously and synchronously changed with the carrier frequency of the transmitting end, so that the digital carrier and the sampling frequency of both communication parties are synchronously tracked and changed all the time;
the baseband digital demodulation control method further comprises the following steps:
the first step: when the data is not received, the baseband data decoding module receives a high-level direct current signal, which indicates that the transmission line is in an idle state at present, and no data can be received;
And a second step of: when data is received, the input end is changed from high level to low level, and the duration of the low level is 16 periods of time for the digital carrier signal, namely the duration of one data bit, which indicates that the reception of one frame of data is started;
And a third step of: a counter with a counting range of 8+ (h+1+1) multiplied by 16 pulses is designed by taking a digital carrier frequency signal as a driving clock, and the counter starts to count after the input end of a baseband data decoding module is changed from high level to low level, wherein h is the length of a data frame appointed by a transmitting end;
Fourth step: when the counter counts to 8 clock pulses, the counter indicates that the clock pulse is currently at the midpoint of the start bit of the data frame, the input start bit signal is sampled, if the clock pulse is 0, the input start bit signal is actually the start bit of the received data frame, the input signal is sampled once every 16 pulses and corresponds to the midpoint position of the data bit, the sampling result is sent into a temporary storage for storage, and after the h-bit data is received, the 1-bit parity check bit and the 1-bit frame termination identification bit are received;
fifth step: and performing exclusive OR operation on the 1-bit data received and the parity check bit which is pre-agreed and coordinated by the transmitting end, if the exclusive OR operation result of the h-bit data is the same as the received parity check bit, indicating that the h-bit data is correctly received, outputting the data stored in the temporary storage to external equipment in parallel, and simultaneously outputting the data to a display control circuit for display.
2. The time synchronization-based tracking receiver control device according to claim 1, wherein: the time service acquisition module extracts the current time received from the BD/GPS time service receiving module as time service time, and simultaneously generates a local time signal by an external crystal oscillator clock, and then refreshes the local time by continuously using the time service time to ensure that the local time is consistent with the time service time, thereby obtaining control time of baseband data frame demodulation;
the sampling clock generation module generates various carrier signals required by decoding the baseband data frames;
The sampling clock control module combines m sampling frequency signals into n sampling frequency groups under the control of the current standard time, the number of carriers in each sampling frequency group is j, and one sampling frequency is used as a baseband data frame to be decoded in different time periods according to the sampling frequency number in turn;
Wherein m=1, 2, 3, …; n=1, 2, 3, …; j=1, 2, 3, ….
3. The time synchronization-based tracking receiver control device according to claim 2, wherein: the channel merging module merges k paths of signals which are transmitted according to time slots after the high-frequency demodulation and are input from the outside into one path of continuous transmission baseband digital signals in the FPGA chip;
The baseband data decoding module acquires all bits in a frame through the middle positions of a sampling start bit, a data bit, a parity check bit and a stop bit, extracts h bits of data from the bits, decodes the received baseband data, and restores and outputs original data sent by a sending end;
The clock driving module obtains a display driving clock signal by dividing an input external crystal oscillator clock;
The display control module is used for displaying key signals in the working process of the system, so that the working condition of the system can be mastered conveniently at any time, and the display content comprises: the time synchronization control signal comprises the current time, a baseband carrier frequency number selected by the current time and the current received data;
the BD/GPS time service receiving module receives the current standard Beijing time downloaded by the satellite and outputs the time to the FPGA chip;
the photoelectric conversion receiving module converts line signals distributed to k wireless, FSO or optical fiber carrier frequency bands in turn according to time slots into high-frequency carrier electric signals;
the amplification module is used for receiving the weak high-frequency carrier electric signal and amplifying the weak high-frequency carrier electric signal to a preset value;
and the filtering and shaping module filters high-frequency carrier components in the amplified high-frequency carrier electric signals, and then obtains baseband data transmission signals through the wave shaping circuit and outputs the baseband data transmission signals to the channel merging module of the FPGA chip.
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