CN115910985A - Power semiconductor module - Google Patents
Power semiconductor module Download PDFInfo
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- CN115910985A CN115910985A CN202211405522.0A CN202211405522A CN115910985A CN 115910985 A CN115910985 A CN 115910985A CN 202211405522 A CN202211405522 A CN 202211405522A CN 115910985 A CN115910985 A CN 115910985A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 229920001296 polysiloxane Polymers 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 description 8
- NMWSKOLWZZWHPL-UHFFFAOYSA-N 3-chlorobiphenyl Chemical compound ClC1=CC=CC(C=2C=CC=CC=2)=C1 NMWSKOLWZZWHPL-UHFFFAOYSA-N 0.000 description 4
- 101001082832 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) Pyruvate carboxylase 2 Proteins 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000499 gel Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 239000000741 silica gel Substances 0.000 description 2
- 229910002027 silica gel Inorganic materials 0.000 description 2
- 238000005493 welding type Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Abstract
The invention discloses a power semiconductor module, comprising: the grid PCB comprises a driving connection unit, and one end of the grid leading-out end is connected with the grid of the semiconductor chip; the grid PCB is provided with a plurality of grid contacts electrically connected with the other end of the grid leading-out end, the grid contacts are connected with the driving connection unit through a plurality of first wiring layers, and current paths flowing through the first wiring layers are consistent. By implementing the invention, the current paths from the driving end to each grid contact are consistent, and the grid parasitic parameter equalization is realized, so that the current equalizing capability of the current between the modules connected in parallel inside the module is effectively improved, and the whole safe working area of the module is improved. And the improvement of the current sharing capability can improve the safety and reliability of the parallel sub-module while increasing the parallel sub-module.
Description
Technical Field
The invention relates to the technical field of high-power semiconductors, in particular to a power semiconductor module.
Background
In recent years, with the acceleration of the commercialization process of silicon carbide power semiconductor devices, the development of the technology is promoted by a good market prospect. In order to meet the growing requirements of high-power applications, a multi-chip parallel package structure is usually adopted to increase the rated current of the module. However, a large transient unbalanced current occurs between the parallel chips, and the suppression of the common-source stray inductance of the gate-level driving circuit of each chip is more difficult, which brings about a small challenge to the safety and stability of the power semiconductor module.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a power semiconductor module to solve the technical problem in the prior art that a larger transient unbalanced current is caused for a parallel chip.
The technical scheme provided by the embodiment of the invention is as follows:
a first aspect of an embodiment of the present invention provides a power semiconductor module, including: the grid PCB comprises a driving connection unit, and one end of the grid leading-out end is connected with the grid of the semiconductor chip; the grid PCB is provided with a plurality of grid contacts electrically connected with the other end of the grid leading-out end, the grid contacts are connected with the driving connection unit through a plurality of first wiring layers, and current paths flowing through the first wiring layers are consistent.
Optionally, the sub-module further comprises: one end of the auxiliary emitter leading-out end is connected with the emitter of the semiconductor chip; and a plurality of auxiliary emitter contacts electrically connected with the other end of the auxiliary emitter leading-out end are arranged on the grid PCB, the auxiliary emitter contacts are connected with the driving connection unit through a plurality of second wiring layers, and current paths flowing through the second wiring layers are consistent.
Optionally, the gate PCB board comprises: the grid contact, the auxiliary emitter contact and the first wiring layer are arranged on the first layer, the second wiring layer is arranged on the second layer, the auxiliary emitter contact is not in contact with the first wiring layer, and the auxiliary emitter contact is connected with the second wiring layer through a through hole.
Optionally, the sub-module further comprises: and one end of the emitter leading-out end is connected with the emitter of the semiconductor chip, and the other end of the emitter leading-out end is connected with the negative electrode of an external power supply.
Optionally, the gate PCB further comprises: one end of each grid resistor is connected with the grid contact, the other end of each grid resistor is connected with the driving connection unit, and the resistance values of the grid resistors are adjustable.
Optionally, the gate terminal, the auxiliary emitter terminal, and the emitter terminal are formed by elastic components, heights of the gate terminal, the auxiliary emitter terminal, and the emitter terminal are greater than a height of the semiconductor chip, a height of the emitter terminal is greater than a height of the auxiliary emitter terminal, and a height difference between the height of the emitter terminal and the height of the auxiliary emitter terminal is equal to a thickness of the gate PCB.
Optionally, the power semiconductor module further comprises: the positions of the holes of the pipe shell with the holes correspond to those of the sub-modules, and the pipe shell and the sub-modules are matched to realize pressure balance control.
Optionally, the sub-module further comprises: and the bottom plate is arranged on the back surface of the semiconductor chip and is connected with the semiconductor chip.
Optionally, the sub-module further comprises: an insulating housing having a height matching the height of the gate terminal, the auxiliary emitter terminal, and the emitter terminal.
Optionally, the sub-module further comprises: the silicone gel is filled in the sub-module.
The technical scheme of the invention has the following advantages:
according to the power semiconductor module provided by the embodiment of the invention, the current level of the power semiconductor module is improved by connecting the plurality of sub-modules in parallel; the grid PCB is arranged outside the sub-module, the first wiring layer is arranged on the grid PCB and connected with the grid of the sub-module through the grid contact on the board and the grid leading-out end, current paths flowing through the first wiring layers are consistent and symmetrically distributed, so that current paths from the driving end to the grid contacts are consistent, grid parasitic parameter equalization is realized, current flow equalization capacity of current between the modules connected in parallel inside the module is effectively improved, and the whole safe working area of the module is improved. And the improvement of the current sharing capability can improve the safety and reliability of the parallel sub-module while increasing the parallel sub-module, which greatly helps to increase the current level of the device. In addition, through setting up the grid PCB board in the module, can be under the circumstances that size, shape etc. are injectd, can realize the parallelly connected flow equalizing of a plurality of sub-modules through the structure of adjustment grid PCB board, wiring mode, effectively reduce research and development cost.
According to the power semiconductor module provided by the embodiment of the invention, the emitter connection of the semiconductor chip of the auxiliary emitter leading-out end is arranged, the auxiliary emitter leading-out end and the grid leading-out end are connected to different circuits in different layers of the grid PCB, namely the drive connecting units are connected through the first wiring layer and the second wiring layer respectively, so that the decoupling of the drive circuit and the power circuit is realized, the parasitic inductance of a common source is reduced, the imbalance degree of current between parallel chips is reduced, the switching speed of the module is increased, and the switching loss of the module is reduced, so that the safe working area of the module is effectively increased, and the switching performance of the module is improved.
According to the power semiconductor module provided by the embodiment of the invention, current paths flowing through a plurality of second wiring layers are consistent; the lengths of current paths from the driving connection unit to each auxiliary emitter contact are consistent, the consistency of emitter parasitic parameters in a driving loop is realized, and the balance degree of current among parallel chips is effectively improved.
According to the power semiconductor module provided by the embodiment of the invention, the plurality of grid resistors with adjustable resistance values are arranged, and the current sharing capability among the parallel chips can be further improved by changing the resistance values of the grid resistors. The bottom plate is arranged on the back of the semiconductor chip, so that the thermal resistance of a heat dissipation channel on the back of the chip can be reduced. And insulating materials such as silica gel are filled in the sub-modules, so that the overall insulating capability and reliability of the modules can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a top view of a power semiconductor module in an embodiment of the invention;
FIG. 2 is a cross-sectional view of a power semiconductor module in an embodiment of the invention;
FIG. 3 is a top view of a first layer of a gate PCB in accordance with an embodiment of the present invention;
FIG. 4 is a top view of a first layer of a gate PCB in an embodiment of the invention.
Detailed Description
As described in the background art, when chips are connected in parallel, a large transient unbalanced current may occur between the chips connected in parallel, and the current distribution is unbalanced, which may cause an excessive current to pass through a certain chip, resulting in local failure of a sub-module formed by the chips; and may even cause the power module to fail or explode. Therefore, the imbalance of the current causes a problem that the safe operating area of the device is reduced.
In view of this, embodiments of the present invention provide a power semiconductor module, which enables gate parasitic parameters to have consistency through consistency of current paths among a plurality of parallel chips, thereby effectively improving the balance degree of current among the parallel chips and improving the overall safe working area of the module.
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be connected through the inside of the two elements, or may be connected wirelessly or through a wire. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present invention provides a power semiconductor module, as shown in fig. 1, 2, and 3, including: the grid PCB comprises a grid PCB 2 and a plurality of sub-modules 1 connected in parallel, wherein each sub-module 1 comprises a semiconductor chip and a grid leading-out terminal 3, the grid PCB 2 comprises a driving connection unit 6, and one end of the grid leading-out terminal 3 is connected with a grid of the semiconductor chip; the grid PCB 2 is provided with a plurality of grid contacts 8 electrically connected with the other end of the grid leading-out end 3, the grid contacts 8 are connected with the driving connection unit 6 through a plurality of first wiring layers, and current paths flowing through the first wiring layers are consistent.
The driving connection unit is connected with an external driving unit, and the external driving unit adopts a gate driver and is used for applying voltage to a gate of the semiconductor chip and providing driving current. The material of the current flowing path of the first wiring layer is a metal material such as copper, and the rest is made of an insulating material. The current paths flowing through the plurality of first wiring layers are uniform, specifically, the lengths of the current paths are uniform, and the widths of the current paths are adjustable. The semiconductor chip may be a pressure welding type chip or a welding type chip, and the specific type of the chip is not limited in the embodiment of the present invention.
According to the power semiconductor module provided by the embodiment of the invention, the current grade of the power semiconductor module is improved by connecting the plurality of sub-modules in parallel; the grid PCB is arranged outside the sub-module, the first wiring layer is arranged on the grid PCB and connected with the grid of the sub-module through the grid contact on the board and the grid leading-out end, current paths flowing through the first wiring layers are consistent and symmetrically distributed, so that current paths from the driving end to the grid contacts are consistent, grid parasitic parameter equalization is realized, current flow equalization capacity of current between the modules connected in parallel inside the module is effectively improved, and the whole safe working area of the module is improved. And current sharing capability
The improvement of the voltage-stabilizing device can improve the safety and reliability of the parallel sub-module while increasing the parallel sub-module, and the improvement is greatly helpful for increasing the current level of the device. In addition, through setting up the grid PCB board in the module, can be under the circumstances that size, shape etc. are injectd, can realize the parallelly connected flow equalizing of a plurality of sub-modules through the structure of adjustment grid PCB board, wiring mode, effectively reduce research and development cost.
In one embodiment, as shown in fig. 2 and 3, the sub-module further includes: an auxiliary emitter leading-out terminal 4, wherein one end of the auxiliary emitter leading-out terminal 4 is connected with the emitter of the semiconductor chip; a plurality of auxiliary emitter contacts 9 electrically connected with the other end of the auxiliary emitter leading-out terminal 4 are arranged on the grid PCB 2, the plurality of auxiliary emitter contacts 9 are connected with the driving connection unit 6 through a plurality of second wiring layers, and current paths flowing through the plurality of second wiring layers are consistent. As shown in fig. 2, the sub-module further comprises: and one end of the emitter leading-out terminal 5 is connected with the emitter of the semiconductor chip, and the other end of the emitter leading-out terminal is connected with the negative electrode of an external power supply. Specifically, the material of the current flow path of the second wiring layer is a metal material such as copper, and the rest is made of an insulating material. As shown in fig. 3, a plurality of holes 10 may be provided on the gate PCB so that the emitter terminal can be connected to the negative electrode of the external power source through the holes without contacting the gate PCB.
In one embodiment, the currents flowing through the plurality of first wiring layers may be distributed symmetrically in addition to the uniform paths, and the currents flowing through the plurality of second wiring layers may be distributed symmetrically in addition to the uniform paths. This can further improve the uniformity of the emitter parasitic parameters in the drive circuit.
The gate PCB includes: first and second layers, specifically, fig. 3 is a first layer plan view of a gate PCB board, and fig. 4 is a second layer plan view of the gate PCB board, wherein the gate PCB board is divided into a driving connection unit 6 and a body part 7. The gate contact 9, the auxiliary emitter contact 9 and the first wiring layer are disposed in the first layer, the second wiring layer is disposed in the second layer, the auxiliary emitter contact 9 is not in contact with the first wiring layer, and as shown in fig. 3, the auxiliary emitter contact 9 is connected to the second wiring layer through a via hole 11.
In addition, the grid leading-out end, the auxiliary emitter leading-out end and the emitter leading-out end are formed by elastic components, the heights of the grid leading-out end, the auxiliary emitter leading-out end and the emitter leading-out end are larger than the height of the semiconductor chip, the height of the emitter leading-out end is larger than the height of the auxiliary emitter leading-out end, and the height difference between the height of the emitter leading-out end and the height difference between the heights of the auxiliary emitter leading-out ends is the thickness of the grid PCB.
Specifically, the grid leading-out end, the auxiliary emitter leading-out end and the emitter leading-out end are respectively connected with the grid or the emitter through bonding wires, the elastic assembly is used as the leading-out end, and the height of the elastic assembly is larger than that of the semiconductor chip, so that the spring assembly can be used for bearing pressure without bearing pressure of the semiconductor chip, and crimping packaging and short circuit failure modes are realized.
According to the power semiconductor module provided by the embodiment of the invention, the emitter connection of the semiconductor chip of the auxiliary emitter leading-out end is arranged, the auxiliary emitter leading-out end and the grid leading-out end are connected to different circuits in different layers of the grid PCB, namely, the driving connection units are connected through the first wiring layer and the second wiring layer respectively, so that the decoupling of the driving circuit and the power circuit is realized, the parasitic inductance of a common source is reduced, the imbalance degree of current between chips connected in parallel is reduced, the switching speed of the module is increased, and the switching loss of the module is reduced, thereby effectively increasing the safe working area of the module and improving the switching performance of the module.
According to the power semiconductor module provided by the embodiment of the invention, current paths flowing through a plurality of second wiring layers are consistent; the lengths of current paths from the driving connection unit to each auxiliary emitter contact are consistent, the consistency of emitter parasitic parameters in a driving loop is realized, and the balance degree of current among parallel chips is effectively improved.
In one embodiment, the gate PCB further comprises: one end of each grid resistor is connected with the grid contact, the other end of each grid resistor is connected with the driving connection unit, and the resistance values of the grid resistors are adjustable. Specifically, the setting of the grid resistor can be adjusted through a plurality of resistance values, and the current sharing capability among the parallel chips can be further improved by changing the resistance value of the grid resistor.
In one embodiment, the power semiconductor module further comprises: the positions of the holes of the pipe shell with the holes correspond to those of the sub-modules, and the pipe shell and the sub-modules are matched to realize pressure balance control. The sub-module further comprises: and the bottom plate is arranged on the back surface of the semiconductor chip and is connected with the semiconductor chip. The sub-module further comprises: an insulating housing having a height matching the height of the gate terminal, the auxiliary emitter terminal, and the emitter terminal. The sub-module further comprises: the silicone gel is filled in the sub-module. Wherein, the height of the insulating shell can be matched with the insulating requirement of the module.
According to the power semiconductor module provided by the embodiment of the invention, the bottom plate is arranged on the back surface of the semiconductor chip, so that the thermal resistance of a heat dissipation channel on the back surface of the chip can be reduced. And insulating materials such as silica gel are filled in the sub-modules, so that the overall insulating capability and reliability of the modules can be improved.
Although the present invention has been described in detail with respect to the exemplary embodiments and the advantages thereof, those skilled in the art will appreciate that various changes, substitutions and alterations can be made to the embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while maintaining the scope of the present invention.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (10)
1. A power semiconductor module, comprising: the grid PCB comprises a driving connection unit, and one end of the grid leading-out end is connected with the grid of the semiconductor chip;
the grid PCB is provided with a plurality of grid contacts electrically connected with the other end of the grid leading-out end, the grid contacts are connected with the driving connection unit through a plurality of first wiring layers, and current paths flowing through the first wiring layers are consistent.
2. The power semiconductor module of claim 1, wherein the sub-module further comprises: one end of the auxiliary emitter leading-out end is connected with the emitter of the semiconductor chip;
and a plurality of auxiliary emitter contacts electrically connected with the other end of the auxiliary emitter leading-out end are arranged on the grid PCB, the auxiliary emitter contacts are connected with the driving connection unit through a plurality of second wiring layers, and current paths flowing through the second wiring layers are consistent.
3. The power semiconductor module of claim 2, wherein the gate PCB board comprises: the gate contact, the auxiliary emitter contact and the first wiring layer are disposed on the first layer, the second wiring layer is disposed on the second layer, the auxiliary emitter contact is not in contact with the first wiring layer, and the auxiliary emitter contact is connected to the second wiring layer through a via hole.
4. The power semiconductor module of claim 2, wherein the sub-module further comprises: and one end of the emitter leading-out end is connected with the emitter of the semiconductor chip, and the other end of the emitter leading-out end is connected with the negative electrode of an external power supply.
5. The power semiconductor module of claim 1, wherein the gate PCB board further comprises: one end of each grid resistor is connected with the grid contact, the other end of each grid resistor is connected with the driving connection unit, and the resistance values of the grid resistors are adjustable.
6. The power semiconductor module of claim 4, wherein the gate terminal, the auxiliary emitter terminal and the emitter terminal are formed by elastic components, wherein heights of the gate terminal, the auxiliary emitter terminal and the emitter terminal are greater than a height of the semiconductor chip, a height of the emitter terminal is greater than a height of the auxiliary emitter terminal, and a difference between the height of the emitter terminal and the height of the auxiliary emitter terminal is equal to a thickness of the gate PCB.
7. The power semiconductor module of claim 1, further comprising: the positions of the holes of the pipe shell with the holes correspond to those of the sub-modules, and the pipe shell and the sub-modules are matched to realize pressure balance control.
8. The power semiconductor module of claim 1, wherein the sub-module further comprises: and the bottom plate is arranged on the back surface of the semiconductor chip and is connected with the semiconductor chip.
9. The power semiconductor module of claim 4, wherein the sub-module further comprises: and the height of the insulating shell is matched with the heights of the grid leading-out terminal, the auxiliary emitter leading-out terminal and the emitter leading-out terminal.
10. The power semiconductor module of claim 2, wherein the sub-module further comprises: the silicone gel is filled in the sub-module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211405522.0A CN115910985B (en) | 2022-11-10 | 2022-11-10 | Power semiconductor module |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211405522.0A CN115910985B (en) | 2022-11-10 | 2022-11-10 | Power semiconductor module |
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| CN115910985A true CN115910985A (en) | 2023-04-04 |
| CN115910985B CN115910985B (en) | 2023-10-27 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08191239A (en) * | 1995-01-11 | 1996-07-23 | Hitachi Ltd | Power semiconductor module |
| JP2009105454A (en) * | 2009-02-10 | 2009-05-14 | Mitsubishi Electric Corp | Power semiconductor module |
| CN107240571A (en) * | 2017-05-10 | 2017-10-10 | 株洲中车时代电气股份有限公司 | Power semiconductor chip, includes the submodule group and compression joint type package module of the chip |
| CN109817612A (en) * | 2019-03-14 | 2019-05-28 | 华北电力大学 | A kind of encapsulating structure improving solder type silicon carbide power module electric heating property |
| CN110050339A (en) * | 2016-12-16 | 2019-07-23 | Abb瑞士股份有限公司 | Power semiconductor modular with low gate vias inductance |
| US20200091140A1 (en) * | 2018-09-14 | 2020-03-19 | Fuji Electric Co., Ltd. | Semiconductor unit, semiconductor module, and semiconductor device |
| CN112234054A (en) * | 2020-10-28 | 2021-01-15 | 南瑞联研半导体有限责任公司 | Multi-chip parallel half-bridge IGBT module |
| CN113711351A (en) * | 2019-04-18 | 2021-11-26 | 日立能源瑞士股份公司 | Power semiconductor module with laser-welded lead frame |
-
2022
- 2022-11-10 CN CN202211405522.0A patent/CN115910985B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08191239A (en) * | 1995-01-11 | 1996-07-23 | Hitachi Ltd | Power semiconductor module |
| JP2009105454A (en) * | 2009-02-10 | 2009-05-14 | Mitsubishi Electric Corp | Power semiconductor module |
| CN110050339A (en) * | 2016-12-16 | 2019-07-23 | Abb瑞士股份有限公司 | Power semiconductor modular with low gate vias inductance |
| CN107240571A (en) * | 2017-05-10 | 2017-10-10 | 株洲中车时代电气股份有限公司 | Power semiconductor chip, includes the submodule group and compression joint type package module of the chip |
| US20200091140A1 (en) * | 2018-09-14 | 2020-03-19 | Fuji Electric Co., Ltd. | Semiconductor unit, semiconductor module, and semiconductor device |
| CN109817612A (en) * | 2019-03-14 | 2019-05-28 | 华北电力大学 | A kind of encapsulating structure improving solder type silicon carbide power module electric heating property |
| CN113711351A (en) * | 2019-04-18 | 2021-11-26 | 日立能源瑞士股份公司 | Power semiconductor module with laser-welded lead frame |
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