CN115599152A

CN115599152A - Multiple LDO output voltage circuit with overshoot suppression and adaptive compensation

Info

Publication number: CN115599152A
Application number: CN202211103733.9A
Authority: CN
Inventors: 王浩; 李文杰; 旷章曲
Original assignee: Howay Integrated Circuit Chengdu Co ltd
Current assignee: Howay Integrated Circuit Chengdu Co ltd
Priority date: 2022-09-09
Filing date: 2022-09-09
Publication date: 2023-01-13

Abstract

The invention discloses a multiple LDO output voltage circuit with overshoot suppression and adaptive compensation, which comprises: the device comprises different reference voltage generation modules, an error amplifier, an intermediate stage, a power tube, an overshoot prevention module, an adaptive Miller compensation module and a feedback network. The circuit has no external capacitor and increased capacitor, so the circuit area can be reduced; the error amplifier and the power output stage are connected by the intermediate stage, so that the gain can be increased, the driving capability can be improved, and the response speed can be improved; the overshoot-proof module is used for detecting current and providing bias voltage for the intermediate stage, so that static power consumption is reduced, and overshoot suppression can be realized on the voltage of the output end of the circuit; the self-adaptive compensation is carried out through the self-adaptive compensation module, and the stability of the circuit can be improved.

Description

Multiple LDO output voltage circuit with overshoot suppression and adaptive compensation

Technical Field

The invention relates to the technical field of low-noise low-dropout regulator circuits, in particular to a circuit with overshoot suppression and adaptive compensation for various LDO output voltages.

Background

As technology advances, more and more functions need to be integrated into a chip, and low power consumption and miniaturization are inevitable trends of system-on-chip (SoC) in advanced electronic devices. To extend battery life and conserve power consumption, the circuit functions within the chip are only used when needed and remain off for the remainder of the time. Furthermore, soC solutions require fully integrated low Power Management Integrated Circuits (PMICs).

Current PMICs are typically a combination of a high efficiency switching DC-DC converter and a low noise low dropout regulator (LDO) to produce multiple clean power supplies on the chip. Due to stringent delay requirements and other critical performance, modern system modules including high performance analog-to-digital converters (ADCs) and Voltage Controlled Oscillators (VCOs) require very clean and high performance voltage sources. Therefore, the LDO used in the embedded system needs to have the performance of fast response speed, low noise, small overshoot voltage, low power consumption, and small shift and area of various output voltages.

The structure of a conventional LDO circuit is shown in fig. 1, and mainly includes an Error Amplifier (EA), a power transistor (Mp), a feedback circuit network, and a corresponding load. Some LDO chips are externally connected with a large capacitor, and the capacitor is usually in the uF level; or some capacitors without external connection chip will add larger capacitor in chip for system stability. With the development of chip miniaturization, the traditional LDO structures can not meet the requirements for the performance of LDO response speed, overshoot prevention capability and the like when a large capacitor added outside or inside a chip is not provided. Generally, the conventional LDO circuit mainly has the following disadvantages: (1) The area is large, and the number of capacitors and power tubes added in the chip is large; (2) power consumption is high; (3) the response speed is low, and the loading capacity is weak; (4) The overshoot voltage is large, so that the abnormal function of the supplied power module is easily caused; (5) The stability is poor since the previous compensation circuit cannot follow the variations of the load current as it varies.

Disclosure of Invention

The invention aims to provide a plurality of LDO output voltage circuits with overshoot suppression and adaptive compensation, which have the advantages of low power consumption, high corresponding speed, strong load carrying capacity, small area and capability of realizing overshoot suppression and adaptive compensation.

The purpose of the invention is realized by the following technical scheme:

a multiple LDO output voltage circuit with overshoot suppression and adaptive compensation, comprising: the device comprises different reference voltage generation modules, an error amplifier, an intermediate stage, a power tube, an overshoot prevention module, a self-adaptive Miller compensation module and a feedback network; wherein:

the reference voltage input end of the error amplifier is connected with the different reference voltage generation module, and the feedback input end of the error amplifier is connected with the first port of the feedback network; the output end of the error amplifier is connected with the grid electrode of the power tube through the intermediate stage, the output end of the error amplifier is gained through the intermediate stage, the power supply electrode of the error amplifier and the source electrode of the power tube are both connected with VDD, and the drain electrode of the power tube and the second port of the feedback network are connected with the output end of the circuit;

the overshoot prevention module is connected with the intermediate stage and the output end of the circuit; providing a bias voltage for the intermediate stage through the overshoot prevention module, adjusting the magnitude of the bias voltage according to the magnitude of the voltage of the output end of the circuit through the overshoot prevention module, and meanwhile, performing overshoot suppression on the voltage of the output end of the circuit through the overshoot prevention module;

and one end of the self-adaptive Miller compensation module is connected with the output end of the error amplifier, the other end of the self-adaptive Miller compensation module is connected with the output end of the circuit, and self-adaptive compensation is carried out according to the current of the output end of the error amplifier and the current of the output end of the circuit.

The technical scheme provided by the invention can show that: (1) No external capacitor is connected with the chip, and the capacitor is added in the chip, so that the circuit area can be reduced; (2) The error amplifier and the power output stage are connected by the intermediate stage, so that the gain can be increased, the driving capability can be improved, and the response speed can be improved; (3) The overshoot prevention module is used for detecting the current and providing bias voltage for the intermediate stage at the same time, so that static power consumption is reduced, and overshoot suppression can be realized on the voltage of the output end of the circuit; (5) Carry out the adaptive compensation through adaptive compensation module, can improve circuit stability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional LDO circuit according to the background art of the present invention;

FIG. 2 is a schematic diagram of a variety of LDO output voltage circuits with overshoot suppression and adaptive compensation according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an intermediate stage according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a current detection module according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an overshoot suppression module provided in an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an adaptive miller compensation module according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of different reference voltage generating modules according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

The terms that may be used herein are first described as follows:

the terms "comprising," "including," "containing," "having," or other similar terms of meaning should be construed as non-exclusive inclusions. For example: including a feature (e.g., material, component, ingredient, carrier, formulation, material, dimension, part, component, mechanism, device, process, procedure, method, reaction condition, processing condition, parameter, algorithm, signal, data, product, or article of manufacture), is to be construed as including not only the particular feature explicitly listed but also other features not explicitly listed as such which are known in the art.

The term "consisting of … …" is meant to exclude any technical feature elements not explicitly listed. If used in a claim, the term shall render the claim closed except for the inclusion of the technical features that are expressly listed except for the conventional impurities associated therewith. If the term occurs in only one clause of the claims, it is defined only to the elements explicitly recited in that clause, and elements recited in other clauses are not excluded from the overall claims.

Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "secured," etc., are to be construed broadly, as for example: can be fixedly connected, can also be detachably connected or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms herein can be understood by those of ordinary skill in the art as appropriate.

The following describes various LDO output voltage circuits with overshoot suppression and adaptive compensation provided by the present invention in detail. Details which are not described in detail in the embodiments of the invention belong to the prior art which is known to a person skilled in the art. Those not specifically mentioned in the examples of the present invention were carried out according to the conventional conditions in the art or conditions suggested by the manufacturer. The reagents and instruments used in the examples of the present invention are not specified by manufacturers, and are conventional products commercially available.

An embodiment of the present invention provides a multiple LDO output voltage circuit with overshoot suppression and adaptive compensation, as shown in fig. 2, which mainly includes: the device comprises different reference voltage generation modules, an Error Amplifier (EA), a middle stage (Buffer), a power tube (Mp), an overshoot prevention module (consisting of a current detection module and an overshoot suppression module), a self-adaptive Miller compensation module and a feedback network (consisting of resistors R0 and R1); in addition, some loads are included, and since there is no external off-chip capacitor and no in-chip added capacitor, CL in fig. 2 mainly refers to the parasitic capacitor of the supplied circuit, and RL and Iload are respectively the load resistance and the load current. Overall:

the reference voltage input end of the error amplifier is connected with the different reference voltage generating modules, and the feedback input end of the error amplifier is connected with the first port of the feedback network; the output end of the error amplifier is connected with the grid electrode of the power tube through the intermediate stage, the output end of the error amplifier is gained through the intermediate stage, the power supply electrode of the error amplifier and the source electrode of the power tube are both connected with VDD, and the drain electrode of the power tube and the second port of the feedback network are connected with the output end of the circuit (namely the output end of the whole circuit);

In order to more clearly show the technical solutions and the technical effects provided by the present invention, the following description is directed to the structures of the various parts of the circuit and the related principles.

1. Intermediate stage (Buffer).

In the embodiment of the present invention, the error amplifier and the power output stage are connected by a buffer as an intermediate stage, which can increase gain and improve driving capability to improve system response speed, as shown in fig. 3, a structural example of the intermediate stage is provided, and 5 MOS transistors and1 NPN transistor are used, where the 5 MOS transistors include: the NMOS transistor NM0 comprises a PMOS transistor PM0, a first PMOS transistor PM1, an NMOS transistor NM0, a first NMOS transistor NM1 and a second NMOS transistor NM2, the NPN transistor is recorded as QN0, wherein Vo1 is the output end voltage of the error amplifier, vg is the grid voltage output by the intermediate stage to the power transistor, the grid voltage Vn1 of the first NMOS transistor NM1 is the bias voltage provided by the current detection module, the diode (namely the grid and the drain of the diode) of the NMOS transistor NM0 is connected to serve as a resistor, and the NM2 transistor plays a reset role.

The main structure of the middle stage is as follows: the PMOS pipe PM0 is connected with a source electrode of the first PMOS pipe PM1 by VDD (power supply end), and the grid electrodes of the PMOS pipe PM0, the first PMOS pipe PM1 and the second NMOS pipe NM2 are connected with a drain electrode of the PMOS pipe PM0, a drain electrode of the second NMOS pipe NM2 and a collector electrode of the NPN pipe QN 0; the drain electrode of the first PMOS tube PM1, the source electrode of the second NMOS tube NM2 and the drain electrode of the first NMOS tube NM1 are connected together to serve as the output end of the intermediate stage; the base electrode of the NPN tube QN0 is used as the input end of the intermediate stage and is connected with the output end of the error amplifier, and the emitter electrode of the NPN tube QN0 is connected with the grid electrode and the drain electrode of the NMOS tube NM 0; the NMOS tube NM0 and the source electrode of the first NMOS tube NM1 are grounded, the first NMOS tube MOS tube NM1 is used as a middle-stage current source, and the grid electrode of the first NMOS tube MOS tube NM1 is connected with the output end of the current detection module in the overshoot prevention module.

2. An anti-overshoot module.

Due to the change of the current at the output end of the circuit, the LDO feedback loop system cannot react quickly, so that the voltage at the output end of the circuit can generate an overshoot phenomenon, and the stability of a supplied power module (a load circuit) is influenced finally.

In order to quickly sense the change of the current at the output end of the circuit, and simultaneously have simple structure and low power consumption, a current detection module is added in the circuit; similarly, in order to solve the problem of overshoot at the output end voltage of the circuit, an overshoot suppression module is added, the overshoot suppression module and the current detection module form an overshoot prevention module together, and the current detection module and the overshoot suppression module are respectively introduced below.

1. And a current detection module.

One end of the current detection module is connected with the current source of the intermediate stage, the other end of the current detection module is connected with the output end of the circuit and used for providing bias voltage for the intermediate stage, an example of the current detection module is provided in fig. 4, the current detection module mainly comprises two MOS (metal oxide semiconductor) tubes, namely a second PMOS (P-channel metal oxide semiconductor) tube PM2 and a third NMOS (N-channel metal oxide semiconductor) tube NM3, and the current detection module has the following structure: the source electrode of the second PMOS tube PM2 is connected with VDD, the grid electrode is connected with the output end (Vout) of the circuit, and the drain electrode is connected with the drain electrode of the third NMOS tube NM 3; the drain electrode of the third NMOS tube NM3 is connected with the grid electrode and the grid electrode of the intermediate-level current source, and the source electrode is grounded.

The output voltage Vn1 of the current detection module is used for providing bias voltage for a first NMOS tube NM1 in the intermediate stage, when the current of the output end of the circuit is suddenly increased, the grid voltage of a second PMOS tube PM2 is reduced, the leakage current of a second MOS tube PM2 is increased, and here, a diode (namely the grid and the drain) of the second NMOS tube NM2 is connected to serve as a resistor, so that the voltage Vn1 is increased, the current of the first NMOS tube NM1 in the intermediate stage is increased, the output end (Vg) of the intermediate stage finally achieves a quick discharge effect, and the response speed of the output end of the intermediate stage is improved. The current detection module provides bias voltage for the intermediate stage while detecting current, so that static power consumption is reduced.

The current detection module and the intermediate stage can well prevent the problem that the output end current of the circuit suddenly changes from small to large to cause the voltage of the output end of the circuit to undershoot, the lowest voltage point of the undershoot is controlled within a certain range, and meanwhile, the current detection module is only used as a bias circuit to provide bias voltage for an NM1 tube in the intermediate stage when the circuit normally works, and extra static power consumption cannot be increased.

2. An overshoot suppression module.

In order to solve the problem that when the current of the output end of the circuit changes from large to small, the output end of the intermediate stage cannot follow the change of the output end of the circuit quickly, the reaction time between the two output ends has a certain difference value, and the current is output to a load capacitor in part of the difference value, so that the overshoot phenomenon of the voltage of the output end of the circuit is caused.

As shown in fig. 5, an example of an overshoot-suppression module is provided, which mainly includes: 6 MOS pipe, 1 PNP pipe and1 NPN pipe, wherein, 6 MOS pipes include: the third PMOS tube PM3, the fourth PMOS tube PM4, the fifth PMOS tube PM5, the fourth PMOS tube NM4, the fifth PMOS tube NM5 and the sixth PMOS tube NM6, the PNP tube is marked as QP0, and the NPN tube is the first NPN tube QN1. The main structure is as follows:

the source electrodes of the third PMOS tube PM3, the fourth PMOS tube PM4 and the fifth PMOS tube PM5 are connected with VDD; the grid electrode of the third PMOS tube PM3 is connected with the drain electrode, and is connected with the base electrode of the first NPN tube QN1 and the emitting electrode of the PNP tube QP 0; the grid electrode of the fourth PMOS tube PM4 is connected with the drain electrode, the grid electrode of the fifth PMOS tube PM5 and the drain electrode of the sixth NMOS tube NM6 are connected, and the drain electrode of the fifth PMOS tube PM5 is connected with the output end of the intermediate stage; a grid electrode of the sixth NMOS tube NM6 and a collector electrode of the first NPN tube QN1 are commonly connected with an output end of the circuit, and a source electrode of the sixth NMOS tube NM6 serves as a first external bias voltage input end and inputs a first external bias voltage Vn2; the base electrode of the PNP tube QP0 is connected with the output end of the intermediate stage, the collector electrode of the PNP tube QP0 is connected with the drain electrode of the fourth NMOS tube NM4, the grid electrode of the fourth NMOS tube NM4 is the second external bias voltage input end, the second external bias voltage Vn3 is input, and the source electrode of the fourth NMOS tube NM4 and the source electrode of the fifth NMOS tube NM5 are grounded; the gate of the fifth NMOS transistor NM5 is connected to the drain and to the emitter of the first NPN transistor QN1.

In the embodiment of the present invention, in order to describe the overshoot suppression principle, the overshoot suppression module may be divided into two parts:

(1) The first part is used for realizing rapid discharge of the output end voltage of the circuit from big sudden change to hour at the output end current of the circuit, and comprises components such as a third PMOS tube PM3, a PNP tube QP0, a fourth NMOS tube NM4, a fifth NMOS tube NM5 and a first NPN tube QN1 in the graph 5, when the middle-stage output end current changes from big sudden change to hour at the output end of the circuit, the changed current is amplified through the PNP tube QP0 and transmitted to the first NPN tube QN1, so that the purpose of rapidly discharging the output end voltage of the current is achieved, and the situation that the excessive current continuously charges a load capacitor to raise the output end voltage of the circuit is prevented.

(2) The second part is used for limiting the maximum value of the overshoot voltage at the output end of the circuit, and includes components such as a sixth NMOS transistor NM6, a fourth PMOS transistor PM4, and a fifth PMOS transistor PM5 in fig. 5, when the difference between the overshoot voltage Vout at the output end of the circuit and the first external bias voltage Vn2 is greater than the threshold voltage of the sixth NMOS transistor NM6, the gate of the power transistor is charged quickly through a current mirror circuit composed of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5, so as to realize the quick pull-up of the gate voltage (i.e., the intermediate-stage output voltage), and the peak value of the overshoot voltage can be better suppressed.

In the embodiment of the invention, vn2 and Vn3 are bias voltages provided by an external bias circuit. The first external bias voltage Vn2 needs to change along with the selection of the voltage gear of the output end of the circuit, and the difference value between the voltage of the output end of the circuit and the Vn2 needs to be smaller than the threshold voltage of the sixth NMOS tube NM6 when the circuit normally works, so that the part can be started to work only when the current of the output end of the circuit changes from large to small, and is in a turn-off state at other moments, and the part which consists of the third PMOS tube PM3, the PNP tube QP0, the fourth NMOS tube NM4, the fifth NMOS tube NM5 and the first NPN tube QN1 is also started to work only when the current of the output end changes, so that the power consumption of the whole circuit cannot be increased due to the increase of the undershoot suppression module.

3. An adaptive Maitreya compensation module.

The stability is used as a key performance index of the LDO, and whether the function of the LDO can be normally realized is directly determined. The change of the current at the output end of the circuit can cause the stability problem of the LDO, so that the system performance of the whole LDO feedback loop is poor. In order to solve the problem, the embodiment of the invention designs a self-adaptive miller compensation module circuit.

As shown in fig. 6, an example of an adaptive miller compensation module circuit is provided, which mainly includes: the two capacitors are called a capacitor C0 and a first capacitor C1, the two resistors are called a second resistor R2 and a third resistor R3, and the two inverters are called a first inverter INV1 and a second inverter INV2.

The structure is as follows: the upper polar plate of the capacitor C0 is connected with the upper polar plate of the first capacitor C1 and is connected with the output end of the error amplifier; the lower pole plate of the first capacitor C1 is connected with the first port of the first CMOS switch, and the lower pole plate of the capacitor C0 is connected with the second port of the first CMOS switch; a first port of the second resistor R2 is connected with a first port of the third resistor R3, and is connected with a lower electrode plate of the capacitor C0 and a second port of the first CMOS switch; a second port of the third resistor R3 is connected with a first port of the second CMOS switch; a second port of the second resistor R2 is connected to a second port of the second CMOS switch and to an output terminal (Vout) of the circuit.

The two CMOS switches have the same structure, the first CMOS switch comprises a sixth PMOS tube PM6 and a seventh NMOS tube NM7, and the second CMOS switch comprises a seventh PMOS tube PM7 and an eighth NMOS tube NM8; the first CMOS switch structure is as follows: the drain electrode of the sixth PMOS transistor PM6 is connected to the source electrode of the seventh NMOS transistor NM7, and serves as a first port of the first CMOS, the source electrode of the sixth PMOS transistor PM6 is connected to the drain electrode of the seventh NMOS transistor NM7, and serves as a second port of the first CMOS switch, the gate electrode of the sixth PMOS transistor PM6 and the gate electrode of the seventh NMOS transistor NM7 both serve as control signal input ports of the first CMOS switch, and the corresponding first control signal swp and the second control signal swn are input separately, and the first control signal swp and the second control signal swn input corresponding control signal input ports at the same time. The second CMOS switch structure is as follows: the drain of the seventh PMOS transistor PM7 is connected to the source of the eighth NMOS transistor NM8, and serves as the first port of the second CMOS switch, the source of the seventh PMOS transistor PM7 is connected to the drain of the eighth NMOS transistor NM8, and serves as the second port of the second CMOS switch, the gate of the seventh PMOS transistor PM7 and the gate of the eighth NMOS transistor NM8 both serve as control signal input ports of the second CMOS switch, and the corresponding first control signal swp and the corresponding second control signal swn are separately input, and the first control signal swp and the corresponding control signal swn are simultaneously input to the corresponding control signal input ports. The two CMOS switch control signals, i.e., the first control signal swp and the second control signal swn, are generated by the current detection module output voltage Vn1 sequentially through the second inverter INV2 and the first inverter INV1, as shown in the lower half of fig. 6, the current detection module output voltage Vn1 generates the first control signal swp through the second inverter INV2, and then generates the second control signal swn through the first inverter INV 1.

The principle is as follows: the capacitor C0, the first capacitor C1 and the first CMOS switch form an adaptive Maitreya capacitor circuit, and the second resistor R2, the third resistor R3 and the second CMOS switch form an adaptive zero-adjusting resistor circuit; when the current of the output end of the circuit is increased from small to large, the bias voltage Vn1 generated by a current detection module in the overshoot-prevention module is increased, so that the first control signal swp is low, the second control signal swn is high, two CMOS switches are conducted, the capacitor C0 and the first capacitor C1 are connected in parallel to increase a Miller compensation capacitor, the second resistor R2 and the third resistor R3 are connected in parallel to reduce the size of a zero-adjusting resistor, the zero pole change caused by the increase of the transconductance gm of the power tube when the current of the output end is increased is well tracked, and meanwhile, the bandwidth is improved and the response speed is increased; when the current of the output end of the circuit is changed from large to small or works normally, the first control signal swp is high, the second control signal swn is low, and the two CMOS switches are closed, so that the stability of the LDO feedback system at the moment is ensured.

As will be understood by those skilled in the art, the transconductance gm is a property of the MOS, and means the variation of the drain current of the MOS transistor divided by the variation of the gate-source voltage.

4. And different reference voltage generation modules.

In an embodiment of the present invention, the different reference voltage generating module includes: the resistor voltage division network, the logic module and the third CMOS switch; wherein: the output end of the resistance voltage-dividing network is in control connection with the negative input end of the error amplifier through a third CMOS switch, one end of the logic module is connected with an input control signal of an external circuit, and the other end of the logic module is connected with a control signal input end of the third CMOS switch.

As shown in fig. 7, an example of different reference voltage generation modules is provided, which takes 4 bits as an example, and 4 bits of logic modules in a dashed box, where the resistor divider network generates 16 different voltage values, where av _ ldo _ sel <3:0> is a 4-bit external input control signal, av _ ldo _ sel <3:0> generates s <7,5,3,1> through inverter INV3<0:3>, s < 3579 zxft 3265 > generates s <6,4,2,0> through inverter INV4<0:3, s < 3525 > and s <6,4,2,0> are used for decoding with the input of a non-gate Vref _ sel < 0> and Vref _ sel < 0> according to the following description, so that the following three different values of the same switch for a PMOS transistor, i.e. v5 INV5< 0> Vref _ INV5 INV < 0> and Vref _ sel < NM <15 > Vref _ 15> are used for controlling the same input of the same PMOS switch, i.e..

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A multiple LDO output voltage circuit with overshoot suppression and adaptive compensation, comprising: the device comprises different reference voltage generation modules, an error amplifier, an intermediate stage, a power tube, an overshoot prevention module, a self-adaptive Miller compensation module and a feedback network; wherein:

the reference voltage input end of the error amplifier is connected with the different reference voltage generating modules, and the feedback input end of the error amplifier is connected with the first port of the feedback network; the output end of the error amplifier is connected with the grid electrode of the power tube through the intermediate stage, the output end of the error amplifier is gained through the intermediate stage, the power supply electrode of the error amplifier and the source electrode of the power tube are both connected with VDD, and the drain electrode of the power tube and the second port of the feedback network are connected with the output end of the circuit;

2. The LDO output voltage circuit with overshoot suppression and adaptive compensation of claim 1, wherein the intermediate stage comprises 5 MOS transistors and1 NPN transistor, wherein 5 MOS transistors comprise: PMOS pipe PM0, first PMOS pipe PM1, NMOS pipe NM0, first NMOS pipe NM1, second NMOS pipe NM2, the NPN pipe is marked as QN0, the structure is as follows:

the PMOS pipe PM0 is connected with a source electrode of the first PMOS pipe PM1 by VDD, and the grid electrodes of the PMOS pipe PM0, the first PMOS pipe PM1 and the second NMOS pipe NM2 are connected with a drain electrode of the PMOS pipe PM0, a drain electrode of the second NMOS pipe NM2 and a collector electrode of the NPN pipe QN 0; the drain electrode of the first PMOS tube PM1, the source electrode of the second NMOS tube NM2 and the drain electrode of the first NMOS tube NM1 are connected together to serve as the output end of the intermediate stage; the base electrode of the NPN tube QN0 is used as the input end of the intermediate stage and is connected with the output end of the error amplifier, and the emitter electrode of the NPN tube QN0 is connected with the grid electrode and the drain electrode of the NMOS tube NM 0; the NMOS tube NM0 and the source electrode of the first NMOS tube NM1 are grounded, the first NMOS tube MOS tube NM1 is used as a current source of a middle stage, and the grid electrode of the first NMOS tube MOS tube NM1 is connected with the output end of the current detection module in the overshoot prevention module.

3. The LDO output voltage circuit with overshoot suppression and adaptive compensation of claim 1, wherein the overshoot prevention module comprises: an overshoot suppression module and a current detection module; wherein:

one end of the current detection module is connected with the current source of the intermediate stage, and the other end of the current detection module is connected with the output end of the circuit and used for providing bias voltage for the intermediate stage;

and one end of the overshoot suppression module is connected with the output end of the intermediate stage, and the other end of the overshoot suppression module is connected with the output end of the circuit and used for realizing overshoot suppression.

4. The LDO output voltage circuit with overshoot suppression and adaptive compensation of claim 3, wherein the current detection module comprises two MOS transistors, a second PMOS transistor PM2 and a third NMOS transistor NM3, and has the following structure:

the source electrode of the second PMOS tube PM2 is connected with VDD, the grid electrode is connected with the output end of the circuit, and the drain electrode is connected with the drain electrode of the third NMOS tube NM 3;

the drain electrode of the third NMOS tube NM3 is connected with the grid electrode and the grid electrode of the intermediate-level current source, and the source electrode is grounded.

5. The LDO output voltage circuit with overshoot suppression and adaptive compensation of claim 3, wherein said overshoot suppression module comprises: 6 MOS pipes, 1 PNP pipe and1 NPN pipe, wherein, 6 MOS pipes include: the third PMOS tube PM3, the fourth PMOS tube PM4, the fifth PMOS tube PM5, the fourth PMOS tube NM4, the fifth PMOS tube NM5 and the sixth PMOS tube NM6, the PNP tube is marked as QP0, the NPN tube is the first NPN tube QN1, and the structure is as follows:

6. The LDO output voltage circuit with overshoot suppression and adaptive compensation of claim 5, wherein the overshoot suppression of the voltage at the output of the circuit comprises:

when the current at the output end of the circuit suddenly changes from large to small, the current at the output end of the intermediate stage changes, and the changed current is amplified through the PNP tube QP0 and transmitted to the first NPN tube QN1, so that the discharge at the output end of the circuit is realized;

when the difference value between the overshoot voltage value at the output end of the circuit and the first external bias voltage Vn2 is larger than the threshold voltage of the sixth NMOS transistor NM6, the grid electrode of the power tube is charged through a current mirror circuit composed of a fourth PMOS transistor PM4 and a fifth PMOS transistor PM 5.

7. The LDO output voltage circuits with overshoot suppression and adaptive compensation of claim 5, wherein the adaptive Miller compensation module comprises: the two capacitors are called a capacitor C0 and a first capacitor C1, the two resistors are called a second resistor R2 and a third resistor R3, and the two inverters are called a first inverter INV1 and a second inverter INV2, and the structure is as follows:

the upper polar plate of the capacitor C0 is connected with the upper polar plate of the first capacitor C1 and is connected with the output end of the error amplifier; the lower pole plate of the first capacitor C1 is connected with the first port of the first CMOS switch, and the lower pole plate of the capacitor C0 is connected with the second port of the first CMOS switch; a first port of the second resistor R2 is connected with a first port of the third resistor R3, and is connected with a lower electrode plate of the capacitor C0 and a second port of the first CMOS switch; a second port of the third resistor R3 is connected with a first port of the second CMOS switch; a second port of the second resistor R2 is connected with a second port of the second CMOS switch and is connected with the output end of the circuit;

the output voltage Vn1 of the current detection module in the overshoot-proof module sequentially passes through a second inverter INV2 and a first inverter INV1 to generate a first control signal swp and a second control signal swn for controlling two CMOS switches; the output voltage Vn1 of the current detection module generates a first control signal swp through a second inverter INV2, and generates a second control signal swn through a first inverter INV 1; the two CMOS switches are provided with two control signal input ports, and each control signal input port independently inputs a control signal.

8. The multiple LDO output voltage circuit with overshoot suppression and adaptive compensation of claim 7, wherein two CMOS switches are identical, the first CMOS switch comprises a sixth PMOS transistor PM6 and a seventh NMOS transistor NM7, the second CMOS switch comprises a seventh PMOS transistor PM7 and an eighth NMOS transistor NM8;

the first CMOS switch structure is as follows: the drain electrode of the sixth PMOS tube PM6 is connected with the source electrode of the seventh NMOS tube NM7 and serves as a first port of the first CMOS, the source electrode of the sixth PMOS tube PM6 is connected with the drain electrode of the seventh NMOS tube NM7 and serves as a second port of the first CMOS switch, the grid electrode of the sixth PMOS tube PM6 and the grid electrode of the seventh NMOS tube NM7 serve as control signal input ports of the first CMOS switch, and the corresponding first control signal swp and the corresponding second control signal swn are independently input;

the second CMOS switch structure is as follows: the drain electrode of the seventh PMOS transistor PM7 is connected to the source electrode of the eighth NMOS transistor NM8, and serves as the first port of the second CMOS switch, the source electrode of the seventh PMOS transistor PM7 is connected to the drain electrode of the eighth NMOS transistor NM8, and serves as the second port of the second CMOS switch, and the gate electrode of the seventh PMOS transistor PM7 and the gate electrode of the eighth NMOS transistor NM8 both serve as the control signal input ports of the second CMOS switch, and the corresponding first control signal swp and the corresponding second control signal swn are input separately.

9. The LDO output voltage circuits with overshoot suppression and adaptive compensation of claim 7 or 8, wherein the adaptive compensation of the adaptive Miller compensation module comprises:

the capacitor C0, the first capacitor C1 and the first CMOS switch form an adaptive Maitreya capacitor circuit, and the second resistor R2, the third resistor R3 and the second CMOS switch form an adaptive zero-adjusting resistor circuit;

when the current of the output end of the circuit is increased from small to large, the bias voltage Vn1 generated by a current detection module in the overshoot prevention module is increased, so that a first control signal swp is low, a second control signal swn is high, two CMOS switches are conducted, a capacitor C0 and a first capacitor C1 are connected in parallel to increase a Miller compensation capacitor, and a second resistor R2 and a third resistor R3 are connected in parallel to reduce the size of a zero setting resistor; when the current at the output end of the circuit changes from large to small or works normally, the first control signal swp is high, the second control signal swn is low, and the two CMOS switches are closed.

10. The LDO output voltage circuit with overshoot suppression and adaptive compensation of claim 1, wherein the different reference voltage generation module comprises: the resistor voltage division network, the logic module and the third CMOS switch; wherein:

the output end of the resistance voltage-dividing network is in control connection with the negative input end of the error amplifier through a third CMOS switch, one end of the logic module is connected with an input control signal of an external circuit, and the other end of the logic module is connected with the input control signal end of the third CMOS switch.