CN115498857A

CN115498857A - Drive circuit, chip and electronic equipment

Info

Publication number: CN115498857A
Application number: CN202211165583.4A
Authority: CN
Inventors: 田磊
Original assignee: 3Peak Inc
Current assignee: 3Peak Inc
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2022-12-20

Abstract

The application provides a driving circuit, a chip and electronic equipment, wherein a control port of a logic device in the driving circuit is respectively connected with a first end of a first switch unit and a first end of a second switch unit; the second end of the first switch unit is connected with the driving power supply, the second end of the second switch unit is grounded, and the backflow prevention unit is respectively connected with the third end of the first switch unit and the third end of the second switch unit; a connecting terminal is led out between the backflow prevention unit and the second switch unit and serves as an output end of the driving circuit; the control signal input end of the backflow prevention unit and the control signal input end of the first switch unit are used for switching the driving circuit to a target driving mode when corresponding control signals are acquired, and the target driving mode comprises a drain open circuit driving mode and a push-pull output driving mode. By arranging the backflow prevention unit, the situation that current flows backwards to generate larger leakage current is avoided, and the logic device outputs correct driving high level.

Description

Drive circuit, chip and electronic equipment

Technical Field

The application relates to the field of chips, in particular to a driving circuit, a chip and electronic equipment.

Background

Many common chips have logic output driving requirements, so a driver circuit needs to be deployed in the chip, the driving requirements corresponding to different adaptation protocols are different, and the adapted drivers are different. The driver is for example a push-pull output driver or an open-drain driver. In order to save the development and design cost of the chip, a chip capable of supporting multi-protocol driving needs to be designed. For example, to support different digital communication protocols, the output driver needs to support both push-pull output and open-drain driving output.

When the open-drain driving output is supported, an external power supply needs to be externally connected through a pull-up resistor. When the voltage of the external power supply is higher than the voltage of the driving power supply of the chip, the situation of current back-flowing may occur. Therefore, a driving circuit which is possibly compatible with push-pull output and drain open circuit driving output is designed, and the situation of current back-flow cannot occur in different voltage domains is ensured, so that the problem concerned by the technical personnel in the field is solved.

Disclosure of Invention

It is an object of the present application to provide a driving circuit, a chip and an electronic device, so as to at least partially improve the above problems.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

in a first aspect, an embodiment of the present application provides a driving circuit, where the driving circuit includes a logic device, a first switch unit, a second switch unit, and a backflow prevention unit;

a control port of the logic device is respectively connected with a first end of the first switch unit and a first end of the second switch unit;

the second end of the first switch unit is connected with a driving power supply, the second end of the second switch unit is grounded, and the backflow prevention unit is respectively connected with the third end of the first switch unit and the third end of the second switch unit;

a wiring terminal is led out between the backflow prevention unit and the second switch unit and is used as an output end of the driving circuit;

the control signal input end of the backflow prevention unit and the control signal input end of the first switch unit are used for switching the driving circuit to a target driving mode when corresponding control signals are obtained, and the target driving mode comprises a drain open circuit driving mode and a push-pull output driving mode.

Optionally, the backflow prevention unit comprises a first subunit and a second subunit;

the first end of the first subunit is connected with the third end of the first switch unit, the second end of the first subunit is connected with the third end of the second switch unit, the third end of the first subunit is connected with the second end of the second subunit, and the first end of the second subunit is connected with the driving power supply;

when a control signal input end of the backflow prevention unit and a control signal input end of the first switch unit receive a control signal corresponding to the push-pull output driving mode, the second subunit is switched to a normally-on state to pull up a third end of the first subunit to the driving power supply so as to switch the first subunit to the normally-on state, the on-off state of the first switch unit is controlled by a trigger signal sent by a control port of the logic device, and the driving circuit is switched to the push-pull output driving mode;

when the control signal input end of the backflow prevention unit and the control signal input end of the first switch unit receive the control signal corresponding to the drain open-circuit driving mode, the second subunit is switched to a normally-off state, the third end of the first subunit is conducted with the output end of the driving circuit, so that the first subunit is switched to the normally-off state, the first switch unit is switched to the normally-off state, and the driving circuit is switched to the drain open-circuit driving mode.

Optionally, the first sub-unit includes a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;

a first pole of the fourth PMOS tube is used as a first end of the first subunit and is connected with a third end of the first switch unit;

a second pole of the fourth PMOS tube is used as a second end of the first subunit and is connected with a third end of the second switch unit;

the substrate of the fourth PMOS tube is connected with the first pole of the third PMOS tube, the substrate of the third PMOS tube is connected with the first pole of the third PMOS tube, a wiring terminal is led out between the substrate of the fourth PMOS tube and the first pole of the third PMOS tube, the wiring terminal is used as a third end of the first subunit and is connected with a second end of the second subunit, and the second pole of the third PMOS tube is connected with the output end of the driving circuit;

the first pole of the second PMOS tube is connected to the output end of the driving circuit, the substrate of the second PMOS tube is connected to the first pole of the second PMOS tube, and the second pole of the second PMOS tube is connected to the grid electrode of the fourth PMOS tube.

Optionally, the first sub-unit further includes a second NMOS transistor; the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is connected to the grid electrode of the fourth PMOS tube; and the grid electrode of the second NMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are used as control signal input ends of the first subunit.

Optionally, the second sub-unit includes a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor;

a source electrode of the sixth PMOS tube is used as a first end of the second subunit and is connected to the driving power supply;

a first pole of the fifth PMOS tube is used as a second end of the second subunit and is connected with a third end of the first subunit, a substrate of the fifth PMOS tube is connected with the first pole of the fifth PMOS tube, and a drain electrode of the sixth PMOS tube is connected with a second pole of the fifth PMOS tube;

the first pole of the seventh PMOS tube is connected between the first pole of the fifth PMOS tube and the third end of the first subunit, the substrate of the seventh PMOS tube is connected to the first pole of the seventh PMOS tube, and the second pole of the seventh PMOS tube is connected to the gate of the fifth PMOS tube.

Optionally, the second sub-unit further includes a third NMOS transistor; the source electrode of the third NMOS tube is grounded, and the drain electrode of the third NMOS tube is connected to the grid electrode of the fifth PMOS tube;

and the grid electrode of the third NMOS tube, the grid electrode of the seventh PMOS tube and the grid electrode of the sixth PMOS tube are used as control signal input ends of the second subunit.

Optionally, the first switch unit includes a first PMOS transistor and a nand gate;

the source electrode of the first PMOS tube is used as the second end of the first switch unit and is connected with a driving power supply, and the drain electrode of the first PMOS tube is used as the third end of the first switch unit and is connected with the backflow prevention unit;

the first input end of the nand gate is used as the first end of the first switch unit and connected with the control port of the logic device, the second input end of the nand gate is used as the control signal input end of the first switch unit, and the output end of the nand gate is connected with the grid of the first PMOS transistor.

Optionally, the driving circuit further includes a state switching unit, and an output end of the state switching unit is connected to a control signal input end of the first switch unit and a control signal input end of the backflow prevention unit, respectively;

the input end of the state switching unit is used for accessing a driving mode signal, outputting a corresponding control signal based on the driving mode signal, and switching the states of the first switch unit and the backflow prevention unit so as to switch the driving circuit to a target driving mode.

Optionally, the state switching unit includes a first inverter and a second inverter, and an output terminal of the first inverter is connected to an input terminal of the second inverter;

the input end of the first inverter is used as the input end of the state switching unit;

the output end of the second inverter is used as the first output end of the state switching unit;

a wiring terminal is led out between the output end of the first phase inverter and the input end of the second phase inverter and is used as a second output end of the state switching unit;

and the control signal input end of the first switch unit and the control signal input end of the backflow prevention unit are connected to the first output end and/or the second output end of the state switching unit.

Optionally, when the driving circuit is in the open-drain driving mode, the output terminal of the driving circuit is further configured to be sequentially connected to a pull-up resistor and an external power supply.

In a second aspect, an embodiment of the present application provides a chip, where the chip includes the driving circuit of the first aspect.

In a third aspect, an embodiment of the present application provides an electronic device, which includes the chip described in the second aspect.

Compared with the prior art, the driving circuit, the chip and the electronic device provided by the embodiment of the application comprise a logic device, a first switch unit, a second switch unit and a backflow prevention unit; the control port of the logic device is respectively connected with the first end of the first switch unit and the first end of the second switch unit; the second end of the first switch unit is connected with the driving power supply, the second end of the second switch unit is grounded, and the backflow prevention unit is respectively connected with the third end of the first switch unit and the third end of the second switch unit; a connecting terminal is led out between the backflow preventing unit and the second switch unit and serves as an output end of the driving circuit; the control signal input end of the backflow prevention unit and the control signal input end of the first switch unit are used for switching the driving circuit to a target driving mode when corresponding control signals are acquired, and the target driving mode comprises a drain open circuit driving mode and a push-pull output driving mode. By arranging the backflow prevention unit, the situation that current flows backwards to generate larger leakage current is avoided, and the logic device outputs correct driving high level.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a connection diagram of a push-pull output driver according to an embodiment of the present disclosure;

fig. 2 is a schematic connection diagram of an open-drain driver according to an embodiment of the present disclosure;

fig. 3 is a schematic connection diagram of a push-pull output and open-drain driving multiplexing circuit according to an embodiment of the present disclosure;

fig. 4 is a connection diagram of a driving circuit provided in an embodiment of the present application;

fig. 5 is a schematic connection diagram of an anti-backflow unit according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another connection of a driving circuit provided in the embodiment of the present application;

fig. 7 is a schematic connection diagram of a state switching unit according to an embodiment of the present application.

In the figure: 10-a first switching unit; 20-a second switching unit; 30-a logic device; 40-backflow prevention unit; 401 — a first subunit; 402-a second subunit; 50-state switching unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not construed as indicating or implying relative importance.

It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

Referring to fig. 1 and fig. 2, fig. 1 is a connection schematic diagram of a push-pull output driver according to an embodiment of the present application, and fig. 2 is a connection schematic diagram of an open-drain driver according to an embodiment of the present application. It should be understood that the push-pull output driver shown in fig. 1 has the characteristics of low power consumption and high speed; the open-drain driver shown in fig. 2 is often externally provided with a pull-up resistor, and can realize the functions of a line and a function.

When a chip is required to be designed to support multi-protocol driving. For example, in order to support different digital communication protocols, the output port VOUT is required to support both push-pull output and open-drain driving output. Specifically, referring to fig. 3, fig. 3 is a connection schematic diagram of a push-pull output and open-drain driving multiplexing circuit according to an embodiment of the present disclosure. It should be appreciated that in the push-pull output mode, no pull-up resistor may be external at the output port VOUT, and in the open-drain driving mode, a pull-up resistor may be external at the output port VOUT.

Specifically, as shown in fig. 3, when MODE _ CTRL =0, the chip implements open-drain driving; when MODE _ CTRL =1, the chip implements push-pull output driving. The chip can support two circuit designs for driving the output. However, there is a significant drawback to the approach shown in fig. 3. When MODE _ CTRL =0, in an application of an open drain, an external power voltage connected to the pull-up resistor needs to be strictly limited to be not higher than an IO power voltage inside the chip, otherwise, a PMOS may generate a current back-flow, which generates a large back-flow current, and causes a logic output not to correctly drive a high level.

In order to overcome the above problems, embodiments of the present application provide a driving circuit, which may be disposed in a chip. Referring to fig. 4, fig. 4 is a connection schematic diagram of a driving circuit according to an embodiment of the present disclosure. As shown in fig. 4, the driving circuit includes a logic device 30, a first switching unit 10, a second switching unit 20, and a backflow prevention unit 40.

The control ports of the logic device 30 are connected to the first terminal (a 1) of the first switching unit 10 and the first terminal (b 1) of the second switching unit 20, respectively.

The logic device 30 is configured to send out a trigger signal, and the trigger signal is configured to control the on/off states of the first switch unit 10 and the second switch unit 20, so as to control the output of the driving circuit.

The second end (a 2) of the first switch unit 10 is connected with the driving power supply, the second end (b 2) of the second switch unit 20 is grounded, and the backflow prevention unit 40 is respectively connected with the third end (a 3) of the first switch unit 10 and the third end (b 3) of the second switch unit 20.

A connection terminal is led out between the backflow prevention unit 40 and the second switch unit 20 to serve as an output terminal (VOUT) of the driving circuit.

The backflow prevention unit 40 is used for preventing the external high-voltage power supply connected by the wiring terminal from performing backflow on the driving power supply.

The control signal input end of the backflow prevention unit 40 and the control signal input end (a 4) of the first switch unit 10 are used for switching the driving circuit to a target driving mode when acquiring a corresponding control signal, and the target driving mode includes an open-drain driving mode and a push-pull output driving mode.

Alternatively, when the open-drain driving mode is used, the anti-backflow unit 40 is in a normally-off state, the first switch unit 10 is in a normally-off state, the on-off state of the first switch unit 10 is not controlled by the trigger signal of the logic device 30, and the on-off state of the second switch unit 20 changes along with the trigger signal of the logic device 30, for example, when the trigger signal is at a high level, the second switch unit 20 is turned on, and when the trigger signal is at a low level, the second switch unit 20 is turned off.

Because the backflow prevention unit 40 is in a normally-off state, the external power supply does not flow back to the first switch unit 10 and the driving power supply, thereby avoiding the situation that the current flows back to generate a large leakage current, and ensuring that the logic device 30 outputs a correct driving high level.

When the push-pull output driving mode is used, the backflow prevention unit 40 is in a normally-on state, the first switch unit 10 and the second switch unit 20 are conducted, and the on-off states of the first switch unit 10 and the second switch unit 20 change along with the trigger signal of the logic device 30.

In summary, the present application provides a driving circuit, which includes a logic device, a first switch unit, a second switch unit, and a backflow prevention unit; the control port of the logic device is respectively connected with the first end of the first switch unit and the first end of the second switch unit; the second end of the first switch unit is connected with the driving power supply, the second end of the second switch unit is grounded, and the backflow preventing unit is respectively connected with the third end of the first switch unit and the third end of the second switch unit; a connecting terminal is led out between the backflow prevention unit and the second switch unit and serves as an output end of the driving circuit; the control signal input end of the backflow prevention unit and the control signal input end of the first switch unit are used for switching the driving circuit to a target driving mode when corresponding control signals are obtained, and the target driving mode comprises a drain open circuit driving mode and a push-pull output driving mode. By arranging the backflow prevention unit, the situation that current flows backwards to generate larger leakage current is avoided, and the logic device outputs correct driving high level.

With reference to fig. 4, the embodiment of the present application further provides a possible implementation manner for the specific structure of the first switch unit 10. As shown in fig. 4, the first switch unit 10 includes a first PMOS transistor PM1 and a nand gate U1.

The source of the first PMOS transistor PM1 is used as the second end of the first switch unit 10 and connected to the driving power supply, and the drain of the first PMOS transistor PM1 is used as the third end of the first switch unit 10 and connected to the backflow prevention unit 40.

A first input end of the nand gate U1 is connected to the control port of the logic device 30 as a first end (a 1) of the first switch unit 10, a second input end of the nand gate U1 is connected to the control signal input end (a 4) of the first switch unit 10, and an output end of the nand gate U1 is connected to the gate of the first PMOS transistor PM 1.

For example, when the MCP is 1, that is, the push-pull output mode is selected, the on-off state of the first switch unit 10 changes with the trigger signal of the logic device 30, for example, when the output of the logic device 30 is at a high level 1, the nand gate U1 outputs a low level, at which the first switch unit 10 is turned on, and when the output of the logic device 30 is at a low level 0, the nand gate U1 outputs a high level, at which the first switch unit 10 is turned off. When the MCP is 0, i.e., the open-drain driving mode is selected, the nand gate output is at high level 1 regardless of whether the output of the logic device 30 is at high level or low level, and the first switch unit 10 is in an off state.

With reference to fig. 4, the embodiment of the present application further provides a possible implementation manner for the specific structure of the second switch unit 20. As shown in fig. 4, the second switch unit 20 employs a first NMOS transistor PM1, a source of the first NMOS transistor PM1 is grounded, a gate of the first NMOS transistor PM1 is connected to the logic device 30, and a drain of the first NMOS transistor PM1 is connected to the backflow prevention unit 40.

On the basis of fig. 4, as to the specific structure of the backflow prevention unit 40, the embodiment of the present application further provides a possible implementation manner, please refer to fig. 5, and fig. 5 is a schematic connection diagram of the backflow prevention unit provided in the embodiment of the present application.

As shown in fig. 5, the backflow prevention unit 40 includes a first sub-unit 401 and a second sub-unit 402.

Optionally, the control signal input terminals of the backflow prevention unit 40 include a control signal input terminal of the first subunit 401 and a control signal input terminal of the second subunit 402.

The first terminal (d 1) of the first sub-unit 401 is connected to the third terminal (a 3) of the first switching unit 10, the second terminal (d 2) of the first sub-unit 401 is connected to the third terminal (b 3) of the second switching unit 20, the third terminal (d 3) of the first sub-unit 401 is connected to the second terminal (e 2) of the second sub-unit 402, and the first terminal (e 2) of the second sub-unit 402 is connected to the driving power supply.

When the control signal input end of the backflow prevention unit 40 and the control signal input end of the first switch unit 10 receive the control signal corresponding to the push-pull output driving mode, the second subunit 402 is switched to the normally-on state to pull up the third end of the first subunit 401 to the driving power supply, so that the first subunit 401 is switched to the normally-on state, and the driving circuit is switched to the push-pull output driving mode.

When the control signal input terminal of the backflow prevention unit 40 and the control signal input terminal of the first switch unit 10 receive a control signal corresponding to the open-drain driving mode, the second subunit 402 is switched to the normally-off state, the third terminal of the first subunit 401 is conducted with the output terminal (VOUT) of the driving circuit, so that the first subunit 401 is switched to the normally-off state, the first switch unit 10 is switched to the normally-off state, and the driving circuit is switched to the open-drain driving mode.

With continuing reference to fig. 5, regarding the specific structures of the first subunit 401 and the second subunit 402, the embodiment of the present application further provides a possible implementation manner.

As shown in fig. 5, the first sub-unit 401 includes a second NMOS transistor NM2, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fourth PMOS transistor PM4.

A first pole of the fourth PMOS transistor PM4 is connected to the third end of the first switch unit 10 as a first end of the first subunit 401.

A second pole of the fourth PMOS transistor PM4 is connected to the third terminal of the second switching unit 20 as a second terminal of the first sub-unit 401.

A substrate (also called body) of the fourth PMOS transistor PM4 is connected to a first pole of the third PMOS transistor PM3, a substrate of the third PMOS transistor PM3 is connected to a first pole of the third PMOS transistor PM3, a connection terminal is led out between the substrate of the fourth PMOS transistor PM4 and the first pole of the third PMOS transistor PM3, and serves as a third end of the first subunit 401 to be connected to a second end of the second subunit 402, and a second pole of the third PMOS transistor PM3 is connected to an output end of the driving circuit.

The first pole of the second PMOS transistor PM2 is connected to the output end of the driving circuit, the substrate of the second PMOS transistor PM2 is connected to the first pole of the second PMOS transistor PM2, and the second pole of the second PMOS transistor PM2 is connected to the gate of the fourth PMOS transistor.

The source electrode of the second NMOS tube NM2 is grounded, and the drain electrode of the second NMOS tube NM2 is connected to the grid electrode of the fourth PMOS tube.

The gate of the second NMOS transistor NM2, the gate of the second PMOS transistor PM2, and the gate of the third PMOS transistor PM3 are used as input terminals of the control signal of the first subunit 401.

It should be noted that the types of the control signals received by the gate of the second NMOS transistor NM2, the gate of the second PMOS transistor PM2, and the gate of the third PMOS transistor PM3 may be the same, for example, all are MCPs shown in fig. 5, and of course, may be different, and are not limited herein.

With reference to fig. 5, the second sub-unit 402 includes a third NMOS transistor NM3, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, and a seventh PMOS transistor PM7.

The source of the sixth PMOS transistor PM6 is connected to the driving power source as the first end of the second subunit 402.

A first pole of the fifth PMOS transistor PM5 is connected to the third end of the first subunit 401 as a second end of the second subunit 402, a substrate of the fifth PMOS transistor PM5 is connected to the first pole of the fifth PMOS transistor PM5, and a drain of the sixth PMOS transistor PM6 is connected to the second pole of the fifth PMOS transistor PM 5.

A first pole of the seventh PMOS transistor PM7 is connected between the first pole of the fifth PMOS transistor and the third end of the first subunit 401, a substrate of the seventh PMOS transistor PM7 is connected to the first pole of the seventh PMOS transistor PM7, and a second pole of the seventh PMOS transistor PM7 is connected to the gate of the fifth PMOS transistor.

The source electrode of the third NMOS tube NM3 is grounded, and the drain electrode of the third NMOS tube NM3 is connected to the gate electrode of the fifth PMOS tube.

The gate of the third NMOS transistor NM3, the gate of the seventh PMOS transistor PM7, and the gate of the sixth PMOS transistor PM6 are used as the control signal input terminals of the second subunit 402.

It should be noted that the control signals corresponding to the gate of the third NMOS transistor NM3, the gate of the seventh PMOS transistor PM7, and the gate of the sixth PMOS transistor PM6 may be different, as shown in fig. 5, the control signal corresponding to the gate of the third NMOS transistor NM3 and the gate of the seventh PMOS transistor PM7 is MCP, the control signal corresponding to the gate of the sixth PMOS transistor PM6 is MCN, and MCN is opposite to MCP.

It should be understood that, in the present application, switching of the output mode needs to be completed based on the control signal, and as to how to generate the control signal, the embodiment of the present application also provides a possible implementation manner, please refer to fig. 6, where fig. 6 is another connection schematic diagram of the driving circuit provided in the embodiment of the present application.

As shown in fig. 6, the driving circuit further includes a state switching unit 50, and an output end of the state switching unit 50 is connected to a control signal input end of the first switching unit 10 and a control signal input end of the backflow preventing unit 40, respectively.

The input end of the state switching unit 50 is used for accessing a driving mode signal, outputting a corresponding control signal based on the driving mode signal, and switching the states of the first switching unit 10 and the backflow prevention unit 40, so that the driving circuit is switched to a target driving mode.

Regarding the specific structure of the state switching unit 50, a possible implementation manner is also provided in the embodiment of the present application, please refer to fig. 7, and fig. 7 is a schematic connection diagram of the state switching unit provided in the embodiment of the present application.

As shown in fig. 7, the state switching unit 50 includes a first inverter T1 and a second inverter T2, and an output terminal of the first inverter T1 is connected to an input terminal of the second inverter T2.

An input end of the first inverter T1 is used as an input end of the state switching unit 50, and is connected to the driving MODE signal (MODE _ CTRL).

An output terminal of the second inverter T2 serves as a first output terminal of the state switching unit 50 to output the MCP signal.

A connection terminal is led out between the output end of the first inverter T1 and the input end of the second inverter T2, and serves as a second output end of the state switching unit 50 to output an MCN signal.

A control signal input terminal of the first switching unit 10 and a control signal input terminal of the second switching unit 20 are connected to a first output terminal and/or a second output terminal of the state switching unit 50.

Specifically, as shown in fig. 5, the types of the control signals received by the gate of the second NMOS transistor NM2, the gate of the second PMOS transistor PM2, and the gate of the third PMOS transistor PM3 may be the same, and are all MCPs. The control signals corresponding to the grid electrode of the third NMOS tube NM3 and the grid electrode of the seventh PMOS tube PM7 are MCP, the control signal corresponding to the grid electrode of the sixth PMOS tube PM6 is MCN, and the MCN is opposite to the MCP. The NAND gate U1 is connected with the control signal MCP.

On the basis of fig. 7 and fig. 5, for how to implement the driving mode switching, the embodiment of the present application also provides a possible implementation manner, please refer to the following.

When MODE _ CTRL =1, the third PMOS transistor PM3 is in an off state, the gate of the fifth PMOS transistor PM5 is pulled down by the third NMOS transistor NM3 and is in an on state, the sixth PMOS transistor PM6 is in an on state, the substrate of the fourth PMOS transistor PM4 is pulled up to the driving power supply VDD, the gate voltage of the fourth PMOS transistor PM4 is pulled down to the ground by the second NMOS transistor NM2, the fourth PMOS transistor PM4 is in an on state, and the push-pull output of the chip is realized.

When MODE _ CTRL =0, the chip implements open-drain driving. Specifically, the second PMOS transistor PM2 is in a conducting state, the body of the second PMOS transistor PM2 is connected to VOUT, the gate voltage of the fourth PMOS transistor PM4 is pulled to VOUT, the body of the fourth PMOS transistor PM4 is pulled up to VOUT by the third PMOS transistor PM3, and the fourth PMOS transistor PM4 is turned off and is not limited by VOUT, so that the current flowing in VOUT is prevented from flowing backwards through the fourth PMOS transistor PM4.

In addition, the sixth PMOS transistor PM6 is turned off, the seventh PMOS transistor PM7 is turned on, the gate voltage of the fifth PMOS transistor PM5 is pulled to the body of PM4 by the seventh PMOS transistor PM7, and the substrate of the fifth PMOS transistor PM5 is also connected to the body of PM4, so that the fifth PMOS transistor PM5 is turned off, thereby preventing the current flowing in VOUT from flowing backward through the third PMOS transistor PM3 and then through the fifth PMOS transistor PM 5. The body of the fourth PMOS pipe PM4 can change along with the change of VOUT, and even if the voltage of the external power supply is higher than the voltage of the chip VDD, the reverse current flowing cannot occur.

In one possible implementation manner, when the driving circuit is in the open-drain driving mode, the output terminal of the driving circuit is further configured to be sequentially connected with the pull-up resistor and the external power supply.

Alternatively, a third switching unit may be provided at the output terminal of the driving circuit and the pull-up resistor, the third switching unit being turned on when in an open-drain driving mode and turned off when in a push-pull output driving mode.

The embodiment of the application provides a backflow prevention driving circuit, digital output driving supports different driving types, and push-pull output and drain open circuit output are supported; output mode switching can be realized only by using one control bit, and backward flow of external voltage higher than the power supply voltage of the chip can be prevented only by one set of circuit when the drain is open.

The embodiment of the application also provides a chip which comprises the driving circuit.

The embodiment of the application also provides electronic equipment, and the electronic equipment comprises the chip.

Alternatively, the electronic device may be a cell phone, a computer, a portable terminal device, a wearable device, and other computing devices.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A drive circuit is characterized by comprising a logic device, a first switch unit, a second switch unit and a backflow prevention unit;

the control port of the logic device is respectively connected with the first end of the first switch unit and the first end of the second switch unit;

2. The driving circuit of claim 1, wherein the back-flow prevention unit comprises a first sub-unit and a second sub-unit;

when the control signal input end of the backflow preventing unit and the control signal input end of the first switch unit receive the control signal corresponding to the push-pull output driving mode, the second subunit is switched to a normally-on state, so that the third end of the first subunit is pulled up to the driving power supply, the first subunit is switched to the normally-on state, and the driving circuit is switched to the push-pull output driving mode;

when the control signal input end of the backflow prevention unit and the control signal input end of the first switch unit receive a control signal corresponding to the open-drain drive mode, the second subunit is switched to a normally-off state, the third end of the first subunit is conducted with the output end of the drive circuit, so that the first subunit is switched to the normally-off state, the first switch unit is switched to the normally-off state, and the drive circuit is switched to the open-drain drive mode.

3. The driving circuit of claim 2, wherein the first sub-unit comprises a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;

4. The driving circuit of claim 3, wherein the first sub-unit further comprises a second NMOS transistor;

the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is connected to the grid electrode of the fourth PMOS tube;

and the grid electrode of the second NMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are used as control signal input ends of the first subunit.

5. The driving circuit of claim 2, wherein the second sub-unit comprises a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor;

6. The driving circuit of claim 5, wherein the second sub-unit further comprises a third NMOS transistor;

the source electrode of the third NMOS tube is grounded, and the drain electrode of the third NMOS tube is connected to the grid electrode of the fifth PMOS tube;

7. The driving circuit of claim 1, wherein the first switching unit comprises a first PMOS transistor and a nand gate;

the first input end of the NAND gate is used as the first end of the first switch unit and connected with the control port of the logic device, the second input end of the NAND gate is used as the control signal input end of the first switch unit, and the output end of the NAND gate is connected with the grid of the first PMOS tube.

8. The driving circuit according to claim 1, wherein the driving circuit further comprises a state switching unit, an output terminal of the state switching unit is respectively connected with a control signal input terminal of the first switch unit and a control signal input terminal of the backflow prevention unit;

9. The driving circuit according to claim 8, wherein the state switching unit includes a first inverter and a second inverter, an output terminal of the first inverter being connected to an input terminal of the second inverter;

10. The driving circuit of claim 1, wherein the output terminal of the driving circuit is further configured to be connected to a pull-up resistor and an external power source in sequence when the driving circuit is in an open-drain driving mode.

11. A chip, characterized in that it comprises a driver circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that it comprises a chip according to claim 11.