CN115336202A

CN115336202A - Encoding and decoding method and device for polarization code

Info

Publication number: CN115336202A
Application number: CN202080098652.7A
Authority: CN
Inventors: 莫晓帆; 李楠; 李航
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2022-11-11
Also published as: WO2021196054A1

Abstract

The application provides a coding and decoding method and a coding and decoding device of a polarization code, wherein the method comprises the following steps: receiving a message from an encoding device, wherein the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit; and taking the type of the first bit as a target type, and decoding the first bit according to a first decoding algorithm corresponding to the target type, wherein the target type comprises a parity check bit or a frozen bit. Since the mapped sub-sequence does not include known bits after the type of the first bit is mapped to the target type, decoding of the sub-sequence including known bits can be achieved. Because the bit value of the frozen bit or the PC bit is irrelevant to the soft value, when the subsequence is decoded according to the decoding algorithm corresponding to the target type, the soft value calculation of the subsequence is not needed, so that under the condition of ensuring the benefit brought by the known bit, the expense generated by the soft value calculation is saved, and the decoding efficiency is improved.

Description

Encoding and decoding method and device for polarization code

Technical Field

The present application relates to the field of communications technologies, and in particular, to a polar code (polar code) encoding and decoding method and apparatus.

Background

The communication system generally adopts channel coding to improve the reliability of data transmission and ensure the quality of communication. For example, a polarization code, reed-muller (RM) code, or other coding method can be used. The polar code is a coding method capable of gradually reaching the channel capacity, and has excellent decoding performance in a wide working interval (such as code length, code rate or signal-to-noise ratio).

In the current decoding scheme of the polar code, the decoding device divides the bits included in the sequence to be decoded into the following three types: information bits (information bits), freeze bits (freeze bits), and Parity Check (PC) bits. The information bits are used for carrying information, the frozen bits are bits with fixed padding, and the PC bits are used for checking. The decoding device can perform fast decoding based on the type of the bit, and the decoding process comprises the following steps: firstly, dividing a sequence to be decoded to obtain a plurality of subsequences to be decoded; determining a decoding algorithm corresponding to each subsequence according to a combination mode of the bit type of each subsequence in the plurality of subsequences to be decoded; and then, the plurality of subsequences are decoded in parallel according to the decoding algorithm corresponding to each subsequence, so that the decoding efficiency is improved, and the quick decoding is realized.

In the current polar code encoding scheme, the encoding apparatus uses some bits with known bit values for redundancy padding, and then jointly encodes these bits with other types of bits, which may be called known bits (knock-down bits), and sends them to the decoding apparatus. The encoding device may map the known bits to the starting position of the decoding sequence, so that the decoding device may determine the decoding reliability of the known bits according to the decoding result of the known bits at the starting position and the bit values of the known bits, and reserve at least one path according to the decoding reliability of the known bits, which may improve the decoding reliability.

Since the type of bits adapted by the decoding algorithm only comprises at least one of information bits, frozen bits or PC bits, the decoding means cannot determine the decoding algorithm to which the sub-sequence corresponds when the type of bits in the sub-sequence comprises known bits. In the prior art, a decoding device can decode known bits as information bits, and in Polar code decoding methods such as Serial Cancellation (SC) and Serial Cancellation List (SCL), decoding processes corresponding to the information bits are complex, and algorithm overhead is large, thereby reducing decoding efficiency. Therefore, how to reduce the overhead and improve the decoding efficiency while ensuring the gain caused by the known bits is a problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a coding and decoding method and device of a polar code, which are used for decoding a subsequence comprising known bits, reducing the overhead and improving the decoding efficiency under the condition of ensuring the benefit brought by the known bits.

In a first aspect, a method for decoding a polar code is provided, where the method includes: receiving a message from an encoding device, wherein the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit; and taking the type of the first bit as a target type, and decoding the first bit according to a first decoding algorithm corresponding to the target type, wherein the target type comprises a parity check bit or a frozen bit.

The method provided by the first aspect may be executed by a decoding apparatus or an apparatus capable of supporting the decoding apparatus to implement the functions required by the method, for example, a system on a chip or the like.

In the above embodiments of the present application, the sub-sequence includes a first bit, and the type of the first bit is a known bit. And taking the type of the first bit as a target type, and decoding the first bit according to a first decoding algorithm corresponding to the target type, wherein the target type is a PC bit or a frozen bit. Since the mapped sub-sequence does not include known bits after the type of the first bit is mapped to the target type, decoding of the sub-sequence including known bits can be achieved. Because the bit value of the frozen bit or the PC bit is irrelevant to the soft value, when the subsequence is decoded according to the decoding algorithm corresponding to the target type, the soft value calculation is not needed to be carried out on the subsequence, so that under the condition of ensuring the benefit brought by the known bit, the expense generated by carrying out the soft value calculation is saved, and the decoding efficiency is improved.

In one possible design, the subsequence further includes second bits, the type of the second bits including at least one of frozen bits, parity bits, or information bits, and the method further includes: and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit. According to the method, the type of the first bit is used as a target type, the first bit is decoded based on a decoding algorithm corresponding to the target type, and when the subsequence further comprises a second bit, the second bit is decoded according to a second decoding algorithm corresponding to the type of the second bit, so that the subsequence comprising the known bit is decoded.

In one possible design, the message is an uplink control message, or a downlink control message.

In one possible design, the uplink control message includes a first field and a second field, where the first field is used to indicate whether the first bit is included in the subsequence, and the second field is used to indicate a position of the first bit in the subsequence. By the method, it may be determined whether a first bit is included in the sub-sequence and, in case the first bit is included, a position of the first bit in the sub-sequence.

In one possible design, the downlink control message includes a third field and a fourth field, where the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate a position of the first bit in the subsequence. By the method, it may be determined whether a first bit is included in the sub-sequence and, in case the first bit is included, a position of the first bit in the sub-sequence.

In one possible design, taking the type of the first bit as the target type includes: when the value range of the first bit is consistent with the value range of the parity bit, taking the type of the first bit as the parity bit; or when the value range of the first bit is consistent with the value range of the frozen bit, the type of the first bit is taken as the frozen bit.

In one possible design, taking the type of the first bit as the target type includes: mapping the type of the first bit to a target type to obtain a position distribution sequence, wherein the position distribution sequence is used for representing the type of each bit in the subsequence; decoding the first bit according to a first decoding algorithm corresponding to the target type, and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit, including: respectively determining a first decoding algorithm and a second decoding algorithm according to the position distribution sequence; and decoding the subsequence according to a third decoding algorithm, wherein the third decoding algorithm comprises a first decoding algorithm and a second decoding algorithm. By the method, the position distribution sequence is obtained after the type of the first bit is mapped to the target type. Since the type of bits indicated by the position distribution sequence does not comprise known bits, the decoding algorithm may be adapted based on the position distribution sequence, thereby enabling decoding of sub-sequences comprising known bits.

In one possible design, where the information bit is not included in the type of second bit, the third decoding algorithm does not include soft value calculations for determining likelihood probabilities that the bit values of the individual bits in the subsequence are 0 or 1. By the method, the bit value of the PC bit and the bit value of the frozen bit are irrelevant to soft value calculation, so that when the type of the second bit does not comprise the information bit, the soft value calculation is not needed, the overhead caused by the soft value calculation can be saved, and the decoding efficiency is improved.

In one possible design, where the information bits are included in the type of second bits, the third decoding algorithm includes soft value calculations for determining likelihood probabilities that the bit values of the individual bits in the subsequence are 0 or 1. By this method, when the type of the second bit includes an information bit, decoding of the sub-sequence including the known bit can be achieved by decoding the sub-sequence through soft value calculation.

In one possible design, when the information bit is not included in the type of second bit, the method further includes: decoding the subsequence according to a third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit; and extracting a first hard value from the hard value sequence as a decoding result. By this method, the known bit is treated as an information bit in the hard value trace back, and when the type of the second bit does not include an information bit, the bit value of the known bit can be extracted from the hard value sequence as a decoding result.

In one possible design, when the information bit is included in the type of second bit, the method further includes: decoding the subsequence according to a third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit; a first hard value and a third hard value are extracted from the sequence of hard values as a result of the decoding, the third hard value being a hard value corresponding to an information bit in the second bits. By the method, the known bit is treated as the information bit in the hard value backtracking, and when the type of the second bit does not comprise the information bit, the bit value of the known bit can be extracted from the hard value sequence as the decoding result.

In a second aspect, a method for decoding a polar code is provided, the method including: receiving a message from an encoding device, wherein the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit; and taking the type of the first bit as a PC bit, and decoding the first bit according to a first decoding algorithm corresponding to the PC bit, wherein the target type comprises a parity check bit or a frozen bit.

The method provided by the second aspect may be performed by a decoding apparatus or an apparatus capable of supporting the decoding apparatus to implement the functions required by the method, such as a chip system.

In the above embodiments of the present application, the sub-sequence includes a first bit, and the type of the first bit is a known bit. And taking the type of the first bit as a PC bit, and decoding the first bit according to a first decoding algorithm corresponding to the PC bit. Since the mapped sub-sequence does not include known bits after the type of the first bit is mapped to the target type, decoding of the sub-sequence including known bits can be achieved. Because the bit value of the PC bit is irrelevant to the soft value, when the subsequence is decoded according to the decoding algorithm corresponding to the PC bit, the soft value calculation of the subsequence is not needed, so that under the condition of ensuring the benefit brought by the known bit, the expense generated by the soft value calculation is saved, and the decoding efficiency is improved.

In one possible design, the subsequence further includes second bits, the type of the second bits including at least one of frozen bits, parity bits, or information bits, and the method further includes: and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit.

In one possible design, the uplink control message includes a first field and a second field, where the first field is used to indicate whether the first bit is included in the subsequence, and the second field is used to indicate a position of the first bit in the subsequence.

In one possible design, the downlink control message includes a third field and a fourth field, where the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate a position of the first bit in the subsequence.

In one possible design, regarding the type of the first bit as a PC bit, includes: mapping the type of the first bit into PC bits to obtain a position distribution sequence, wherein the position distribution sequence is used for representing the type of each bit in the subsequence; decoding the first bit according to a first decoding algorithm corresponding to the PC bit, and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit, including: respectively determining a first decoding algorithm and a second decoding algorithm according to the position distribution sequence; and decoding the subsequence according to a third decoding algorithm, wherein the third decoding algorithm comprises a first decoding algorithm and a second decoding algorithm.

In one possible design, where the information bit is not included in the type of second bit, the third decoding algorithm does not include soft value calculations for determining likelihood probabilities that the bit value of each bit in the subsequence is 0 or 1.

In one possible design, where the information bits are included in the type of second bits, the third decoding algorithm includes soft value calculations for determining likelihood probabilities that the bit values of the individual bits in the subsequence are 0 or 1.

In one possible design, when the information bit is not included in the type of second bit, the method further includes: decoding the subsequence according to a third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit; and extracting a first hard value from the hard value sequence as a decoding result.

In one possible design, when the information bits are included in the type of second bits, the method further includes: decoding the subsequence according to a third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit; a first hard value and a third hard value are extracted from the sequence of hard values as a result of the decoding, the third hard value being a hard value corresponding to an information bit in the second bits.

In a third aspect, a method for decoding a polar code is provided, the method including: receiving a message from an encoding device, wherein the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit; and taking the type of the first bit as a frozen bit, and decoding the first bit according to a first decoding algorithm corresponding to the frozen bit, wherein the target type comprises a parity check bit or the frozen bit.

The method provided by the third aspect may be performed by a decoding apparatus or an apparatus capable of supporting the decoding apparatus to implement the functions required by the method, such as a system-on-chip or the like.

In the above embodiments of the present application, the sub-sequence includes a first bit, and the type of the first bit is a known bit. And taking the type of the first bit as a frozen bit, and decoding the first bit according to a first decoding algorithm corresponding to the frozen bit. Since the mapped sub-sequence does not include known bits after the type of the first bit is mapped to the target type, decoding of the sub-sequence including known bits can be achieved. Because the bit value of the frozen bit is irrelevant to the soft value, when the subsequence is decoded according to the decoding algorithm corresponding to the frozen bit, the soft value calculation of the subsequence is not needed, so that under the condition of ensuring the benefit brought by the known bit, the expense generated by the soft value calculation is saved, and the decoding efficiency is improved.

In one possible design, the subsequence further includes a second bit, the type of the second bit including at least one of a frozen bit, a parity bit, or an information bit, the method further including: and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit.

In one possible design, treating the type of the first bit as a frozen bit includes: mapping the type of the first bit into a frozen bit to obtain a position distribution sequence, wherein the position distribution sequence is used for representing the type of each bit in the subsequence; decoding the first bit according to a first decoding algorithm corresponding to the frozen bit, and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit, including: respectively determining a first decoding algorithm and a second decoding algorithm according to the position distribution sequence; and decoding the subsequence according to a third decoding algorithm, wherein the third decoding algorithm comprises a first decoding algorithm and a second decoding algorithm.

In one possible design, when no information bits are included in the type of second bits, the method further includes: decoding the subsequence according to a third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit; the first hard value is extracted from the sequence of hard values as a decoding result.

In one possible design, when the information bit is included in the type of second bit, the method further includes: decoding the subsequence according to a third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit; a first hard value and a third hard value are extracted from the sequence of hard values as a result of the decoding, the third hard value being a hard value corresponding to an information bit in the second bits.

In a fourth aspect, a method for decoding a polar code is provided, the method including: receiving a message from an encoding device, wherein the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit; and decoding the first bit according to a first decoding algorithm corresponding to the type of the first bit.

The method provided by the fourth aspect may be performed by a decoding apparatus or an apparatus capable of supporting the decoding apparatus to implement the functions required by the method, such as a chip system.

In the above embodiments of the present application, the sub-sequence includes a first bit, and the type of the first bit is a known bit. Decoding of the sub-sequence comprising known bits may be achieved by decoding the first bit with a first decoding algorithm corresponding to the type of the first bit.

In one possible design, decoding the first bit according to a first decoding algorithm corresponding to a type of the first bit and decoding the second bit according to a second decoding algorithm corresponding to a type of the second bit includes: respectively determining a first decoding algorithm and a second decoding algorithm according to the position distribution sequence corresponding to the subsequence; and decoding the subsequence according to a third decoding algorithm, wherein the third decoding algorithm comprises a first decoding algorithm and a second decoding algorithm.

In a fifth aspect, a method for coding a polarization code is provided, the method comprising: respectively acquiring a first bit and a second bit, wherein the type of the first bit is a known bit, and the type of the second bit comprises at least one of a frozen bit, a parity bit or an information bit; generating a pilot sequence based on the first bit; coding the second bit to obtain a first coding sequence; and when the pilot sequence is determined to be transmitted, a second coding sequence is sent to the decoding device, wherein the second coding sequence comprises the pilot sequence and the coding sequence.

The method provided by the fifth aspect may be executed by an encoding apparatus or an apparatus capable of supporting the encoding apparatus to implement the functions required by the method, such as a system-on-chip or the like.

In the above embodiments of the present application, a first bit and a second bit are obtained, respectively, and a pilot sequence is generated based on the first bit, where the pilot sequence may not be sent. Therefore, the encoding device can determine whether to use the known bits for redundancy filling, i.e. whether to send the pilot sequence according to the network resource occupation condition or the decoding performance requirement and other information. When the air interface resources are sufficient or the decoding performance requirement is high, the coding device can send the pilot frequency sequence, so that the decoding performance can be improved, and the high-requirement decoding performance requirement can be met. When the air interface resource is in shortage, the coding device may not send the pilot sequence, thereby reducing the load of the air interface resource.

In one possible design, the second code sequence is the first code sequence when it is determined that the pilot sequence is not to be transmitted.

In one possible design, the second coding sequence is an uplink control message, or a downlink control message.

In a possible design, the second coding sequence includes at least one sub-sequence, and for a sub-sequence, the uplink control message includes a first field and a second field, where the first field is used to indicate whether a first bit is included in the sub-sequence, and the second field is used to indicate a position of the first bit in the sub-sequence.

In one possible design, the second coding sequence includes at least one subsequence, and for a subsequence, the downlink control message includes a third field and a fourth field, where the third field is used to indicate whether the subsequence includes the first bit, and the fourth field is used to indicate a position of the first bit in the subsequence.

In one possible design, the method further includes: when the air interface resources are sufficient, determining to send a pilot frequency sequence; or, when the air interface resource is tense, determining not to send the pilot frequency sequence.

In a sixth aspect, a communication device is provided, which includes a receiver and a decoder:

the receiver is used for receiving a message from the encoding device, the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit;

and the decoder is used for taking the type of the first bit as a target type and decoding the first bit according to a first decoding algorithm corresponding to the target type, wherein the target type comprises a parity check bit or a frozen bit.

In one possible design, the sub-sequence further includes a second bit, the type of the second bit includes at least one of a freeze bit, a parity bit, or an information bit, and the decoder is further configured to:

and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit.

In one possible design, the decoder is specifically configured to:

when the value range of the first bit is consistent with the value range of the parity check bit, taking the type of the first bit as an odd-even check bit; or,

and when the value range of the first bit is consistent with the value range of the frozen bit, taking the type of the first bit as the frozen bit.

In one possible design, the decoder is specifically configured to:

mapping the type of the first bit to a target type to obtain a position distribution sequence, wherein the position distribution sequence is used for representing the type of each bit in the subsequence;

respectively determining a first decoding algorithm and a second decoding algorithm according to the position distribution sequence;

and decoding the subsequence according to a third decoding algorithm, wherein the third decoding algorithm comprises a first decoding algorithm and a second decoding algorithm.

In one possible design, when the information bit is not included in the second bit type, the decoder is further configured to:

decoding the subsequence according to a third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit;

and extracting a first hard value from the hard value sequence as a decoding result.

In one possible design, when the information bit is included in the second bit type, the decoder is further configured to:

a first hard value and a third hard value are extracted from the sequence of hard values as a result of the decoding, the third hard value being a hard value corresponding to an information bit in the second bits.

In a seventh aspect, a communication device is provided, which includes a receiver and a decoder:

the receiver is used for receiving a message from the encoding device, wherein the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit;

and the decoder is used for taking the type of the first bit as a PC bit and decoding the first bit according to a first decoding algorithm corresponding to the PC bit.

In one possible design, the decoder is specifically configured to:

mapping the type of the first bit into PC bits to obtain a position distribution sequence, wherein the position distribution sequence is used for representing the type of each bit in the subsequence;

In one possible design, where the information bit is not included in the type of second bit, the third decoding algorithm does not include soft value calculations for determining likelihood probabilities that the bit values of the individual bits in the subsequence are 0 or 1.

and extracting the first hard value and a third hard value from the hard value sequence as a decoding result, wherein the third hard value is a hard value corresponding to the information bit in the second bit.

In an eighth aspect, a communication device is provided, which includes a receiver and a decoder:

and the decoder is used for taking the type of the first bit as the frozen bit and decoding the first bit according to a first decoding algorithm corresponding to the frozen bit.

In one possible design, the decoder is specifically configured to:

mapping the type of the first bit into a frozen bit to obtain a position distribution sequence, wherein the position distribution sequence is used for representing the type of each bit in the subsequence;

the first hard value is extracted from the sequence of hard values as a decoding result.

In a ninth aspect, a communication device is provided, the communication device comprising a receiver and a decoder;

and the decoder is used for decoding the first bit according to a first decoding algorithm corresponding to the type of the first bit.

In one possible design, the decoder is specifically configured to:

respectively determining a first decoding algorithm and a second decoding algorithm according to the position distribution sequence corresponding to the subsequence;

In a possible design, when the second bit type does not include an information bit, the decoder is specifically configured to:

In one possible design, when the second bit type includes an information bit, the decoder is specifically configured to:

In a tenth aspect, there is provided a communication apparatus comprising an encoder and a transmitter:

the encoder is used for respectively acquiring a first bit and a second bit, wherein the type of the first bit is a known bit, and the type of the second bit comprises at least one of a frozen bit, a parity bit or an information bit; generating a pilot sequence based on the first bit; coding the second bit to obtain a first coding sequence;

and the transmitter is used for transmitting a second coding sequence to the decoding device when determining to transmit the pilot sequence, wherein the second coding sequence comprises the pilot sequence and the first coding sequence.

In one possible design, the encoder is further configured to:

when the air interface resources are sufficient, determining to send a pilot frequency sequence; or,

and when the air interface resources are in shortage, determining not to send the pilot frequency sequence.

In an eleventh aspect, there is provided a communication apparatus comprising: the device comprises an input interface circuit and a logic circuit, wherein the input interface circuit is used for receiving a message from an encoding device, the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit; the logic circuit is configured to perform the method according to any one of the first to fourth aspects 12 to 21 based on the subsequence.

In a twelfth aspect, a communication apparatus is provided, including: the device comprises a logic circuit and an output interface circuit, wherein the logic circuit is used for respectively acquiring a first bit and a second bit, the type of the first bit is a known bit, and the type of the second bit comprises at least one of a frozen bit, a parity bit or an information bit; generating a pilot sequence based on the first bit; encoding the second bit to obtain an encoded sequence, and performing the method of any one of the above fifth aspects; the output interface circuit is used for sending an encoding message to a decoding device, wherein the encoding message comprises the pilot frequency sequence and the encoding sequence.

In a thirteenth aspect, a communication apparatus is provided, including: a memory for storing a program; a processor configured to execute the program stored in the memory, and when executed, cause the communication apparatus to perform the method of any one of the first to fifth aspects.

In one possible design, the processor includes the memory.

In one possible design, the communication device is a chip or an integrated circuit.

A fourteenth aspect provides a computer readable storage medium having computer readable instructions stored therein, which when run on a communication apparatus, cause the communication apparatus to perform the method of any one of the first to fifth aspects.

A fifteenth aspect provides a computer program product for causing a communication device to perform the method of any one of the first to fifth aspects when the computer program product is run on the communication device.

In a sixteenth aspect, a chip system is provided, where the chip system includes a processor and may further include a memory, and is configured to implement the method of any one of the first to fifth aspects. The chip system may be formed by a chip, and may also include a chip and other discrete devices.

Drawings

Fig. 1A is a schematic architecture diagram of a communication system according to an embodiment of the present application;

fig. 1B is a schematic architecture diagram of another communication system suitable for use in the embodiments of the present application;

FIG. 2 is a diagram illustrating a parallel decoding process according to an embodiment of the present application;

FIG. 3 is a flowchart illustrating a fast decoding method for a polar code according to an embodiment of the present invention;

fig. 4 is a flowchart of a method for coding a polar code according to an embodiment of the present application;

fig. 5 is a flowchart of a decoding method of a polar code according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating a mapping manner of a known bit in a parallel decoding process according to an embodiment of the present application;

fig. 7 is a flowchart of another decoding method for polar codes according to an embodiment of the present application;

fig. 8 is another schematic diagram of a mapping manner of known bits in a parallel decoding process according to an embodiment of the present application;

fig. 9 is a flowchart of another decoding method for polar codes according to an embodiment of the present application;

fig. 10 is another schematic diagram of a mapping manner of known bits in a parallel decoding process according to an embodiment of the present application;

fig. 11 is a flowchart of another decoding method for polar codes according to an embodiment of the present application;

fig. 12 is a flowchart of another decoding method for polar codes according to an embodiment of the present application;

fig. 13 is a flowchart of another decoding method for polar codes according to an embodiment of the present application;

fig. 14 is a flowchart of another decoding method for polar codes according to an embodiment of the present application;

fig. 15 is a flowchart of another decoding method for polar codes according to an embodiment of the present application;

fig. 16 is a schematic diagram of an apparatus for decoding a polar code according to an embodiment of the present disclosure;

fig. 17 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 18 is a schematic structural diagram of another communication device according to an embodiment of the present application;

fig. 19 is a schematic structural diagram of another communication device according to an embodiment of the present application;

fig. 20 is a schematic structural diagram of another communication device according to an embodiment of the present application;

fig. 21 is a schematic structural diagram of another communication device according to an embodiment of the present application.

Detailed Description

The embodiment of the application provides a coding and decoding method and device of a polarization code. The method and the device are based on the same technical conception, and because the principle of solving the problems of the method and the device is similar, the implementation of the device and the method can be mutually referred, and repeated parts are not described again. In the description of the embodiment of the present application, "and/or" describes an association relationship of associated objects, which means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. At least one referred to in this application means one or more; plural means two or more. In addition, it is to be understood that the terms first, second, third and the like in the description of the present application are used for distinguishing between the descriptions and are not to be construed as indicating or implying relative importance or order.

The encoding and decoding method provided in the embodiments of the present application may be applied to a fifth generation (5G) communication system, such as a 5G New Radio (NR) system, a device to device (D2D) communication system, a bluetooth communication system, a WiFi communication system, or various future communication systems.

First, a communication system applied to the embodiment of the present application will be described.

Fig. 1A illustrates a possible architecture of a communication system 100 to which the coding and decoding method provided in the present embodiment is applied. As shown in fig. 1A, the communication system 100 includes: a network device 200 and one or more terminals 300 (3 terminals are included in fig. 1A) located within the coverage of the network device 200. The communication system 100 may further include a core network, to which the network device 200 accesses, thereby providing services to the terminals 300 within the coverage area. For example, referring to fig. 1A, a network device 200 provides wireless access to one or more terminals 300 within the coverage area of the network device 200. In addition, there may be overlapping areas of coverage between different network devices 200, where two elliptical areas overlap and the overlapping area between network device 200 and network device 200'.

The network device 200 is a node in a Radio Access Network (RAN), which may also be referred to as a base station and may also be referred to as a RAN node (or device). Illustratively, the network device 200 may be: next generation base station (gNB), next generation evolved Node B (Ng-eNB), transmission Reception Point (TRP), evolved Node B (evolved Node B, eNB), radio Network Controller (RNC), node B (NB), base Station Controller (BSC), base Transceiver Station (BTS), home base station (e.g., home evolved Node B, or home Node B, HNB), base Band Unit (BBU), or wireless fidelity (Wifi) Access Point (AP), network device 200 may also be a satellite, and satellite may also be referred to as an aerial platform, aerial vehicle, or satellite. The network apparatus 200 may also be other devices having a network apparatus function, for example, the network apparatus 200 may also be a device serving as a network apparatus function in D2D communication. The network device 200 may also be a network device in a future possible communication system.

In some deployments, the network apparatus 200 may include Centralized Units (CUs) and Distributed Units (DUs). Network device 200 may also include an Active Antenna Unit (AAU). The CU implements part of the functions of the network device 200, and the DU implements part of the functions of the network device, for example, the CU is responsible for processing non-real-time protocols and services, and implementing functions of a Radio Resource Control (RRC) layer and a packet data convergence layer (PDCP) layer. The DU is responsible for processing a physical layer protocol and a real-time service, and implements functions of a Radio Link Control (RLC) layer, a Medium Access Control (MAC) layer, and a Physical (PHY) layer. The AAU implements part of the physical layer processing functions, radio frequency processing and active antenna related functions. Since the information of the RRC layer eventually becomes or is converted from the information of the PHY layer, the higher layer signaling, such as the RRC layer signaling, may also be considered to be transmitted by the DU or by the DU + AAU under this architecture. It is to be understood that the network apparatus 200 may be a device comprising one or more of a CU node, a DU node, an AAU node. The embodiment of the present application does not limit this. The network device 200 may be the network device 200 itself, or may be a chip in the network device 200.

A terminal 300, also referred to as User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), etc., is a device that provides voice and/or data connectivity to a user. For example, the terminal 300 includes a handheld device, a vehicle-mounted device, and the like having a wireless connection function. Currently, the terminal 300 may be: mobile phone (mobile phone), tablet computer, notebook computer, palmtop computer, mobile Internet Device (MID), wearable device (e.g., smart watch, smart bracelet, pedometer, etc.), vehicle-mounted device (e.g., automobile, bicycle, electric vehicle, airplane, ship, train, high-speed rail, etc.), virtual Reality (VR) device, augmented Reality (AR) device, wireless terminal in industrial control (industrial control), smart home device (e.g., refrigerator, television, air conditioner, electric meter, etc.), smart robot, wireless terminal in unmanned driving, wireless terminal in remote surgery (remote), wireless terminal in smart grid, wireless terminal in transportation safety (transportation safety), wireless terminal in city (smart city), or smart terminal in home (smart phone, smart balloon, etc., smart airplane, unmanned plane, etc. The terminal 300 may also be another device having a terminal function, for example, the terminal 300 may also be a terminal serving as a terminal function in D2D communication. The terminal 300 may be the terminal 300 itself, or may be a chip in the terminal 300. Taking a mobile phone as an example, the terminal 300 may be the mobile phone itself, or may be a chip in the mobile phone, such as a baseband chip.

Fig. 1B illustrates another possible architecture of a communication system 100 to which the coding and decoding method provided in the embodiments of the present application is applied. As shown in fig. 1B, the communication system 100 includes: a network device 200 (including 4 network devices in fig. 1B) and one or more terminals 300 (including 1 terminal in fig. 1B) located within the coverage of the network device 200. Further, the network device 200 may include a first network device 201 and a second network device 202. The first network apparatus 201 may be a macro base station. The macro base station is a base station erected on an iron tower, the body of the base station is large, the carried user data is large, the coverage area is wide, and the range of the coverage area can reach dozens of kilometers generally. The second network device 202 may be a micro base station, or a pico base station, or a femto base station. The micro base station may be a miniaturized base station, and generally refers to a small base station installed in a building or a dense area, and the base station has a small volume, a small coverage area, and a relatively low number of users. The pico base station may be a smaller base station than the micro base station, and the single carrier transmit power and coverage capability of the pico base station may be further reduced compared to the macro base station and the micro base station. The femto base station can be accessed by a home bandwidth and is a smaller base station than macro base stations, micro base stations and pico base stations.

The communication system 100 may also include a core network 400. The first network device 201 may access the core network 400. Thereby providing services (e.g., providing wireless access services) to the terminals 300 within its coverage. The second network device 202 may access the core network 400 to provide services to the terminals 300 within its coverage area. The second network device 202 may also access the core network 400 via the first network device 201 to serve the terminals 300 within its coverage area.

The technical features in the embodiments of the present application are described below.

The communication system usually adopts channel coding to improve the reliability of data transmission and ensure the quality of communication. For example, a polarization code, RM code, or the like can be used. The polar code is a coding method capable of achieving channel capacity gradually, and has excellent decoding performance in a wide working interval (such as code length, code rate or signal-to-noise ratio).

In the current decoding scheme of the polar code, the decoding apparatus divides the bits included in the sequence to be decoded into the following three types: information bits, freeze bits, and PC bits. The information bits are used to carry information, and the information bits may include payload (payload) bits and Cyclic Redundancy Check (CRC) bits. A frozen bit refers to a fixed padded bit, typically having a bit value of 0. The PC bits are used for checking, e.g., the PC bits may assist the CRC bits in checking the payload bits. The decoding device can decode the sequence to be decoded by using Polar decoding algorithms such as SC or SCL and the like based on the type of the bit, so that the quick decoding is realized and the decoding efficiency is improved. The decoding process may include bit type identification, soft value calculation, hard value calculation, and hard value backtracking. When identifying the type of bits of the sequence to be decoded, the decoding device may divide the sequence to be decoded into a plurality of subsequences to be decoded in advance according to the parallelism, perform serial decoding cycles of soft value calculation and hard value calculation on each of the plurality of subsequences to obtain a hard value sequence, and then perform hard value backtracking on the hard value sequence by the decoding device, as shown in fig. 2. Taking SC decoding algorithm as an example, soft value calculation is Log Likelihood Ratio (LLR) calculation, and hard value calculation is decoding based on LLR calculation results.

The bit type identification means that a decoding device determines the type of each bit in a sequence to be decoded, and determines a decoding algorithm corresponding to each subsequence according to the combination mode of the types of the bits in each subsequence. Soft value calculation refers to the decoding apparatus determining the soft value of each bit in each sub-sequence. The hard value calculation means that the decoding device determines the hard value of each bit in the sequence to be decoded through a maximum likelihood estimation algorithm according to the soft value of each bit in each subsequence, and obtains a hard value sequence corresponding to the sequence to be decoded. The hard value backtracking process refers to the decoding apparatus extracting the hard values of all information bits from the hard value sequence. The soft value refers to a likelihood probability that a bit value of a bit is 0 or a likelihood probability that a bit value of a bit is 1, and the hard value refers to a bit value of a bit is 0 or 1, and the soft value of each bit in the subsequence may be determined by soft value information indicated by the encoding means.

Note that, for one subsequence, the decoding device may directly perform hard value calculation without performing soft value calculation when decoding the subsequence. For example, the types of the bits in a sub-sequence are all frozen bits, and after the decoding apparatus determines that the type of each bit in the sub-sequence is all frozen bits in the type identification of the bits, the decoding apparatus can determine the bit value of each bit in the sub-sequence according to the bit value of the frozen bits, so that no soft value calculation is required.

For easy understanding, please refer to fig. 3, and fig. 3 is a flowchart illustrating a fast decoding method of a polar code.

S301: the decoding device receives a sequence to be decoded from the encoding device, wherein the sequence to be decoded comprises at least one bit.

It should be noted that the sequence to be decoded may also be referred to as information to be decoded, a codeword to be decoded, a code block to be decoded, a codeword or a code block, and the like.

S302: and the decoding device determines the type of each bit in the sequence to be decoded according to the position distribution sequence corresponding to the sequence to be decoded.

It should be noted that the position distribution sequence is used to indicate the type and position of each bit. For example, 00 indicates a freeze bit, 01 indicates an information bit, and 10 indicates a PC bit. For example, if the sequence to be decoded is [ bit 0 bit 1 bit 2 bit 3], and the position distribution sequence corresponding to the sequence to be decoded is [00 10 01], the decoding apparatus may determine, according to the position distribution sequence, that the types of bits in the sequence to be decoded are [ frozen bit PC bit information bit ], that is, the type of bit 0 is a frozen bit, the type of bit 1 is a PC bit, and the types of bit 2 and bit 3 are both information bits. The sequence of position distributions may be indicated to the decoding means by the encoding means.

S303: the decoding device divides the sequence to be decoded to obtain at least one subsequence to be decoded.

For example, the sequence to be decoded includes 128 bits, and the decoding apparatus may divide the sequence to be decoded into 16 subsequences to be decoded, where each subsequence includes 8 bits.

S304: the decoding means determines a decoding algorithm corresponding to each sub-sequence according to the type of each bit in each sub-sequence.

The decoding device can determine a decoding algorithm corresponding to each subsequence according to the combination mode and/or arrangement mode of the types of the bits in each subsequence, wherein the decoding algorithm is a simple decoding algorithm which is calculated and experimented to obtain the best benefit according to one or more of the number of the bits in the subsequence, the combination mode of the types of the bits in the subsequence or the arrangement mode of the types of the bits in the subsequence in advance. The decoding algorithm may be used to determine a hard value sequence corresponding to a sub-sequence from the sub-sequence. The decoding algorithm may indicate whether to perform soft value calculations. For example, when the type of bits in the sub-sequence does not include information bits, the decoding algorithm may indicate that no soft value calculation is performed; alternatively, where the type of bits in the sub-sequence comprises information bits, the decoding algorithm may indicate that soft value calculations are required. Further, the decoding algorithm may further indicate at least one of information such as the number of paths that need to be reserved when a path is split, an error correction method, a soft decision method, or a hard decision method.

S305: and the decoding device rapidly decodes the sequence to be decoded by using a decoding algorithm corresponding to each sub-sequence to obtain a hard value sequence corresponding to the sequence to be decoded.

S306: and the decoding device extracts the hard values of all the information bits from the hard value sequence according to the position distribution sequence corresponding to the information bits to obtain a decoding result.

For example, 00 denotes a freeze bit, 01 denotes an information bit, and 10 denotes a PC bit. The sequence to be decoded is [ bit 0 bit 1 bit 2 bit 3], the position distribution sequence corresponding to the sequence to be decoded is [00 10 01], and the hard value sequence corresponding to the sequence to be decoded is [01 1]. The decoding device can extract the hard values of all information bits from the hard value sequence according to the position distribution sequence corresponding to the information bits, namely 01, and obtain the decoding result, namely [ 1].

At this point, the decoding device completes the fast decoding of the sequence to be decoded.

In the current polar code encoding scheme, the encoding apparatus uses some bits with known bit values to perform redundancy padding, so as to obtain decoding benefits. This redundancy comes primarily from two areas: fixed padding caused by uplink and downlink proportion and a feedback window; fixed padding caused by non-scheduling of Physical Downlink Shared Channel (PDSCH) resources. Taking a single carrier as an example, the single carrier uses 7 bits for feedback, but actually, at most 4 bits actually feed back hybrid automatic repeat request (HARQ) information, and the remaining 3 bits perform redundancy padding, for example, padding non-acknowledgement character (NACK) information. The dual carrier needs to use 14 bits for feedback, 8 bits of the 14 bits are information bits for carrying HARQ information, and the remaining 6 bits are known bits for carrying NACK information. For example, the 14 bits are [11 100 0],1 represents an information bit for carrying HARQ information, and 0 represents a known bit for carrying NACK information.

In a specific implementation, the encoding apparatus may perform redundancy padding using some bits with known bit values, and then jointly encode the bits with other types of bits, which may be called known bits (knock-down bits), and send the bits to the decoding apparatus. Since the bit values of the bits are known, the decoding device can directly determine the bit values of the bits, so that the decoding reliability can be improved, and the decoding benefit is brought. For example, the encoding apparatus may map known bits to bit positions with low reliability, so that information bits carrying useful information may be mapped to bit positions with high reliability, thereby improving decoding reliability and efficiency of broadcast signaling transmission. As another example, the encoding apparatus may map the known bits to the start position of the decoding order. When at least one path needs to be reserved after the path splitting, the decoding device may determine the decoding reliability of the known bit according to the decoding result of the known bit at the starting position and the bit value of the known bit, and select a path to be reserved based on the decoding reliability of the known bit, so as to improve the decoding reliability, since the bit value of the known bit is known. For example, 3 bits may split 8 paths, and for each path, the decoding apparatus may determine the decoding reliability of the known bit according to the decoding result of the known bit at the starting position and the bit value of the known bit. If the decoding device is to reserve 1 path, the decoding device may determine the path with the highest decoding reliability of the known bits among the 8 paths as the path to be reserved.

On the encoding side, the encoding apparatus may perform redundancy padding using known bits, and then map the known bits together with other types of bits into the resource block of the corresponding sub-channel to transmit to the decoding apparatus. When the empty resource is tight, it is known that the filling of bits will additionally increase the load of the empty resource. In addition, since the type of bits to which the current decoding algorithm is adapted includes only one or more of information bits, frozen bits, or PC bits, the decoding apparatus cannot determine the decoding algorithm for the sub-sequence when the type of bits in the sub-sequence includes known bits. The decoding device can decode the known bit in the subsequence as an information bit, and the decoding algorithm corresponding to the information bit comprises soft value calculation and hard value calculation, so that the overhead is high, and the decoding efficiency is reduced.

In view of this, the coding and decoding method and apparatus for polar codes provided in the embodiments of the present application are used to decode a subsequence including known bits, so that under the condition of ensuring the benefit brought by the known bits, the overhead is reduced, and the decoding efficiency is improved.

The following describes a coding method of a polar code provided by an embodiment of the present application from an encoding side and a decoding side, respectively.

Fig. 4 is a flowchart illustrating a method for coding a polarization code according to an embodiment of the present disclosure, where the method can be applied to the communication system 100 shown in fig. 1A or fig. 1B. The execution subject of the method may be a coding device, and the coding device may be the network device 200 or at least one chip in the network device 200, and may also be the terminal 300 or at least one chip in the terminal 300. The encoding apparatus may also be referred to as a transmitting end, and the decoding apparatus as a receiving end. When the encoding apparatus is the network apparatus 200, the decoding apparatus is the terminal 300, and when the encoding apparatus is the terminal 300, the decoding apparatus is the network apparatus 200. When the method is applied to the communication system 100 shown in fig. 1B, if the encoding device is the first network device 201, the decoding device is the second network device 202 or the terminal 300; if the encoding device is the second network device 202, the decoding device is the first network device 201 or the terminal 300. The method will be described below by taking an example in which the method is applied to the communication system 100 shown in fig. 1A or 1B.

S401: the encoding device respectively acquires a first bit and a second bit, wherein the type of the first bit is a known bit, and the type of the second bit is at least one of a frozen bit, a PC bit or an information bit.

The encoding device may split the sequence to be encoded to obtain a first bit in the sequence to be encoded and a second bit in the sequence to be encoded, respectively. For example, the encoding apparatus may determine a type of each bit in the sequence to be encoded through a position distribution sequence corresponding to the sequence to be encoded, and then obtain the first bit and the second bit according to the type of each bit in the sequence to be encoded. The sequence to be encoded may be Uplink Control Information (UCI), downlink Control Information (DCI), or the like.

For example, 00 denotes a freeze bit, 01 denotes an information bit, 10 denotes a PC bit, and 11 denotes a known bit. If the sequence to be coded is [ bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7], and the position distribution sequence corresponding to the sequence to be coded is [11 0100 10 11 10], the coding apparatus may determine, according to the position distribution sequence, that the type of each bit in the sequence to be coded is [ known bit information bit frozen bit PC bit known bit PC bit ], that is, bit 0 is known bit, bit 1 is information bit, bit 2 is information bit, bit 3 is frozen bit, bit 4 is PC bit, bit 5 is known bit, bit 6 is known bit, and bit 7 is PC bit. Further, the encoding apparatus may obtain the first bit and the second bit respectively according to the type of each bit, that is, the first type of bit includes bit 0, bit 5, and bit 6, and the second type of bit includes bit 1, bit 2, bit 3, bit 4, and bit 7.

S402: the encoding apparatus generates a pilot sequence based on the first bit.

The coding apparatus may not transmit the pilot sequence after generating the pilot sequence based on the first bit. For example, if the encoding apparatus determines not to use known bits for redundancy padding, the encoding apparatus does not transmit the pilot sequence; the encoding apparatus transmits the pilot sequence if the encoding apparatus determines to use the known bits for redundancy padding.

S403: the coding device codes the second bit to obtain a first coded sequence.

Further, the encoding apparatus may determine whether to use known bits for redundancy padding according to information such as network resource occupation (e.g., air interface resource occupation) or decoding performance requirements. For example, if the encoding apparatus determines to use the known bits for the redundancy padding, S404 is performed; if the encoding apparatus determines not to use the known bits for the redundancy padding, S405 is performed.

S404: when it is determined that the known bits are used for the redundancy padding, the encoding apparatus transmits a second code sequence including the pilot sequence and the first code sequence to the decoding apparatus.

For example, in a scenario where air interface resources are sufficient or decoding performance requirements are high, the encoding device may use known bits for redundancy padding, that is, send the pilot sequence to the decoding device to meet the high-requirement decoding performance requirements, so as to improve the decoding performance. Further, after determining to use the known bits for redundancy padding (i.e., determining to send the pilot sequence to the decoding apparatus), the encoding apparatus may map the pilot sequence and the first code sequence into corresponding resource blocks on corresponding sub-channels, respectively, according to the position distribution sequence corresponding to the sequence to be encoded, and send the result to the decoding apparatus.

S405: upon determining not to use the known bits for redundancy padding, the encoding apparatus transmits a second encoded sequence, which is the first encoded sequence, to the decoding apparatus.

For example, in a scenario where air interface resources are tight, the encoding apparatus may not use known bits for performing redundancy padding, that is, not send a pilot sequence to the decoding apparatus, so as to reduce the load of the air interface resources. Further, after determining that the known bits are not used for redundancy padding (i.e., determining that the pilot sequence is not transmitted to the decoding apparatus), the encoding apparatus may map the first code sequence into the resource block on the corresponding sub-channel according to the position distribution sequence corresponding to the second bits, and transmit the resource block to the decoding apparatus, and delete the pilot sequence.

In a possible embodiment, if the encoding apparatus determines not to use known bits for redundancy padding according to the network resource occupation situation or the decoding performance requirement before S402, the encoding apparatus does not need to generate a pilot sequence based on the first bit, i.e., the encoding apparatus may only perform the steps shown in S401, S403 and S405.

In a possible implementation, the second coding sequence may be a downlink control message or an uplink control message. The second coding sequence may comprise at least one subsequence. For any subsequence of the at least one subsequence, if the second coded sequence is a downlink control message, the downlink control information includes a first field for indicating whether a first bit is included in the subsequence and a second field for indicating a position of the first bit in the subsequence; or, if the second coding sequence is an uplink control message, the uplink control message includes a third field for indicating whether the first bit is included in the subsequence and a fourth field for indicating a position of the first bit in the subsequence.

In the above embodiments of the present application, the encoding apparatus obtains a first bit and a second bit from a sequence to be encoded, and generates a pilot sequence based on the first bit, where the pilot sequence may not be transmitted. The encoding apparatus may determine whether to use known bits for redundancy padding, i.e., whether to transmit the pilot sequence, according to information such as network resource occupation or decoding performance requirements. When the air interface resources are sufficient or the decoding performance requirement is high, the coding device can send the pilot frequency sequence, so that the decoding performance can be improved, and the high-requirement decoding performance requirement can be met. When the air interface resource is in shortage, the coding device may not send the pilot sequence, thereby reducing the load of the air interface resource.

The encoding device sends the second encoded sequence to the decoding device. The decoding device receives the second coding sequence and decodes the second coding sequence. Specifically, the decoding apparatus may divide the second coding sequence into at least one subsequence to be decoded according to the parallelism, and decode the at least one subsequence to be decoded in parallel. Wherein, the at least one subsequence to be decoded comprises at least one of the first subsequence, the second subsequence or the third subsequence. Only the first bit is included in the first subsequence, the first bit being of a known type. The second subsequence comprises a first bit and a second bit, and the type of the second bit is at least one of a frozen bit, a PC bit or an information bit. Only the second bit is included in the third sub-sequence.

It should be noted that, if the second code sequence does not include the first bit, that is, the second code sequence is the first code sequence, the decoding device may decode the second code sequence with reference to the decoding process shown in fig. 3. If the at least one sub-sequence to be decoded includes a third sub-sequence, the decoding apparatus may decode the third sub-sequence with reference to the decoding process shown in fig. 3.

The following describes a specific process for decoding the first sub-sequence and the second sub-sequence, and the flowcharts shown in fig. 5, 7, 9 and 11 are the flowcharts for decoding the first sub-sequence, and the flowcharts shown in fig. 12 to 15 are the flowcharts for decoding the second sub-sequence.

It should be noted that the decoding method of the polarization code provided in the embodiment of the present application may be applied to the communication system 100 shown in fig. 1A or fig. 1B. The main body of the method may be a decoding device, and the decoding device may be the network device 200 or at least one chip in the network device 200, or may be the terminal 300 or at least one chip in the terminal 300. The encoding apparatus may also be referred to as a transmitting end, and the decoding apparatus as a receiving end. The decoding device is the terminal 300 when the encoding device is the network device 200, and the decoding device is the network device 200 when the encoding device is the terminal 300. When the method is applied to the communication system 100 shown in fig. 1B, if the encoding device is the first network device 201, the decoding device is the second network device 202 or the terminal 300; if the encoding device is the second network device 202, the decoding device is the first network device 201 or the terminal 300. The method will be described below by taking an example in which the method is applied to the communication system 100 shown in fig. 1A or 1B.

Example 1

Referring to fig. 5, fig. 5 is a flowchart illustrating a decoding method of a polar code according to an embodiment of the present disclosure. In the method, a decoding device takes the type of a first bit as a PC bit, and decodes a first subsequence based on a decoding algorithm corresponding to the PC bit, wherein the first subsequence only comprises the first bit.

S501: the decoding device receives a message from the encoding device, wherein the message comprises a first subsequence which only comprises a first bit, and the value range of the first bit is consistent with the value range of the PC bit.

The decoding means receives a message from the encoding means, which message may comprise a first sub-sequence comprising only the first bit. For example, the first subsequence includes 8 bits, the 8 bits being of a known type. The message may be an uplink control message or a downlink control message. For example, when the encoding device is the terminal 300 and the decoding device is the network device 200, the message may be an uplink control message. For another example, when the encoding device is the first network device 201 and the decoding device is the second network device 202, the message may be a downlink control message. When the message is an uplink control message, the uplink control message includes a first field and a second field, the first field is used for indicating whether a first bit is included in the first subsequence, and the second field is used for indicating a position of the first bit in the first subsequence. Or, when the message is a downlink control message, the downlink control message includes a third field and a fourth field, where the third field is used to indicate whether the first subsequence includes the first bit, and the fourth field is used to indicate a position of the first bit in the first subsequence. The first field and/or the second field may be predefined fields or reserved fields in the uplink control message, and the third field and/or the fourth field may be predefined fields or reserved fields in the downlink control message.

The value range of the first bit is consistent with the value range of the PC bit, which means that the possible value of the first bit after decoding is consistent with the possible value of the PC bit after decoding. For example, the possible value of the decoded PC bit is 0 or 1, and the possible value of the decoded first bit is 0 or 1. For another example, when the first bit carries information, the possible value of the first bit is 0 or 1. The possible value of the first bit may be determined by a position distribution sequence corresponding to the known bit, for example, the position distribution sequence of the known bit may include 100 and 102, where 100 denotes the known bit and the bit value of the known bit is 0, and 101 denotes the known bit and the bit value of the known bit is 0. The possible values of the PC bits may be determined by the decoding result of the previous subsequence, and the specific implementation process thereof may refer to the prior art, which is not described herein again.

S502: the decoding device takes the type of the first bit as a PC bit, and decodes the first subsequence according to a decoding algorithm corresponding to the PC bit to obtain a hard value sequence corresponding to the first subsequence, wherein the hard value sequence only comprises a first hard value corresponding to the first bit.

When the value range of the first bit is consistent with the value range of the PC bit, the characteristics of the different types of bits are shown in table 1. As shown in table 1, the decoding result is used to represent a value range after decoding each type of bit, the value characteristic is used to represent a calculation manner for obtaining the decoding result, the checksum error correction is used to represent a contribution of each type of bit to the checksum error correction in the decoding process, and the carrying content is used to represent a meaning or an effect of each type of bit after decoding. As shown in table 1, as for the decoding result, the value range of the known bit is consistent with the value ranges of the PC bit and the information bit, the value range is 0 or 1, and the value range of the frozen bit is fixed to 0. As for the value characteristics, the value characteristics of the known bit are consistent with the value characteristics of the frozen bit, the decoding result is known and soft value calculation is not needed, while the value of the PC bit is related to the earlier decoding result although the soft value calculation is not needed, and the value of the information bit is related to the earlier decoding result as well as the soft value calculation. For checksum error correction, the known bits are identical to the PC bits and need to participate in the checksum but are not flipped during error correction, while the frozen bits do not participate in the checksum, and the information bits need to participate in both the checksum and error correction and are also flipped during error correction. As far as the bearer content is concerned, the known bits are identical to the information bits and are used to carry messages, while the frozen bits have no practical meaning for fixed padding and the PC bits are used to carry check values. The decoding result and the checksum error correction characteristic are used for determining how to decode, and are used in bit type identification and hard value calculation; the value characteristics can be used for determining whether to perform soft value calculation or not, and can be used in the soft value calculation; the bearer content is used to determine whether to extract bits as information, which will be used in the hard value trace back.

Table 1: table for comparing characteristics of different types of bits

The decoding algorithm cannot adapt to a sub-sequence comprising known bits, but can adapt to a sub-sequence comprising at least one of frozen bits, PC bits or information bits. The decoding algorithm is determined in the type identification of the bits and used in the hard value calculation. And the type identification of the bit and the hard value calculation are related to the decoding result, the check sum and the error correction. It is considered that the decoding result of the known bit is consistent with the decoding result of the PC bit, and the contribution of the known bit to the checksum error correction is also consistent with the contribution of the PC bit to the checksum error correction. Therefore, the decoding apparatus can process the type of the first bit as a PC bit in the type recognition of the bit and the hard value calculation. Therefore, the decoding device can decode the known bit as the PC bit in the bit type identification and the hard value calculation, so that the decoding algorithm corresponding to the PC bit can be adapted to decode the known bit, the decoding performance brought by the known bit is obtained, and the decoding of the known bit is realized. For example, 000, 110, and 111 indicate the freeze bits, 001 and 010 indicate the information bits, 011 indicates the PC bits, 100 indicates the known bits with a value of 0, and 101 indicates the known bits with a value of 1. The position distribution sequence corresponding to the first sub-sequence is [100 101 100], i.e. the four bits in the first sub-sequence are all known bits. In the bit type identification and hard value calculation, the decoding device can map the known bits into PC bits, and the obtained mapped position distribution sequence is [011 011 011 011 011], namely the types of the mapped 4 bits are PC bits.

In terms of the value characteristics, the value characteristics of the bits are related to the soft value calculation, while the value characteristics of the known bits are consistent with the value characteristics of the frozen bits, which means that the known bits can obtain the decoding efficiency benefit equivalent to the frozen bits in the soft value calculation. Thus, the decoding means may treat the type of the first bit as a frozen bit in the soft value calculation. In the soft value calculation, the decoding device can treat the known bits as the frozen bits, and the types of the bits in the first subsequence are all the known bits, so the decoding device can skip the soft value calculation when decoding the first subsequence, reduce the overhead caused by the soft value calculation, and improve the decoding efficiency. For example, 000, 110, and 111 indicate the freeze bits, 001 and 010 indicate the information bits, 011 indicates the PC bits, 100 indicates the known bits with a value of 0, and 101 indicates the known bits with a value of 1. The position distribution sequence corresponding to the first sub-sequence is [100 101] and in the soft value calculation, the decoding apparatus may map the known bits to be the frozen bits, and obtain the mapped position distribution sequence as [000 000 000 000], that is, the 4 bits are all of the type of the frozen bits after mapping.

The soft value calculation is only related to the value of the information bit and is not related to the value of the frozen bit or the PC bit. In practical applications, the decoding apparatus may process the PC bits as frozen bits when performing soft value calculation on the PC bits, i.e., skip the soft value calculation. Therefore, in the soft value calculation, the decoding means can also process the frozen bits as PC bits.

In the case of bearer content, the bearer content of a bit is associated with a hard value trace back, whereas the bearer content of a known bit is identical to the bearer content of an information bit. Thus, the decoding apparatus can process the type of the first bit as an information bit in the hard value trace back. In this way, when the hard value is traced back, the decoding apparatus may process the known bits as information bits, so that the bit values of all the known bits in the first subsequence may be obtained. For example, 000, 110, and 111 indicate the freeze bits, 001 and 010 indicate the information bits, 011 indicates the PC bits, 100 indicates the known bits with a value of 0, and 101 indicates the known bits with a value of 1. The position distribution sequence corresponding to the first sub-sequence is [101 100 101], and in the hard value backtracking, the decoding device maps the known bits into information bits to obtain the mapped position distribution sequence [001 010], that is, the 4 bits are all information bits after mapping.

As an example, in the type recognition of the bit and the hard value calculation, the decoding apparatus may process the type of the first bit as a PC bit; in the soft value calculation, the decoding device can treat the type of the first bit as a frozen bit; in hard value backtracking, the decoding means may treat the type of the first bit as an information bit, as shown in fig. 6. It should be understood that since the decoding means can treat the PC bit as the frozen bit in the soft value calculation, the decoding means can also treat the type of the first bit as the PC bit in the soft value calculation.

In S502, the first subsequence only includes the first bit, and the decoding apparatus uses the type of the first bit as a PC bit, so that the decoding apparatus can decode the first subsequence according to a decoding algorithm corresponding to the PC bit, thereby implementing decoding of the known bit. Specifically, the decoding apparatus may map the type of the first bit in the first subsequence to a PC bit according to the second field in the uplink control message or the fourth field in the downlink control message, so as to obtain the first position distribution sequence. Alternatively, the decoding apparatus may map the type of the first bit in the first subsequence to PC bits according to the position distribution sequence corresponding to the first subsequence, to obtain the first position distribution sequence. Since the type of the bit indicated by the first position distribution sequence does not include the known bit, the decoding apparatus may determine a decoding algorithm corresponding to the first sub-sequence according to the first position distribution sequence, and decode the first sub-sequence according to the decoding algorithm corresponding to the first sub-sequence, so as to obtain a hard value sequence corresponding to the first sub-sequence. Since the first subsequence only includes the first bit, the decoding algorithm corresponding to the first subsequence may be a decoding algorithm corresponding to PC bits. For example, the decoding algorithm corresponding to the PC bit may be used to instruct to determine the bit value of the PC bit according to the decoding result of the previous sub-sequence. For another example, the decoding algorithm corresponding to the PC bit may also be used to indicate the contribution of the bit value of the PC bit to the bit value of the obtained information bit.

When the first subsequence is decoded, the type of the bits indicated by the first position distribution sequence is only PC bits, and the decoding device may determine the hard value sequence corresponding to the first subsequence directly according to the position distribution sequence corresponding to the first subsequence without performing soft value calculation on the first subsequence. For example, 000, 110, and 111 indicate the freeze bits, 001 and 010 indicate the information bits, 011 indicates the PC bits, 100 indicates the known bits with a value of 0, and 101 indicates the known bits with a value of 1. The position distribution sequence corresponding to the first sub-sequence is [101 100 101], and the decoding apparatus can determine that the hard value sequence corresponding to the first sub-sequence is [11 01] according to the position distribution sequence corresponding to the first sub-sequence. Wherein only a first hard value corresponding to the first bit is included in the sequence of hard values.

S503: the decoding device extracts a first hard value from the hard value sequence as a decoding result of the first subsequence.

In the hard value backtracking process, the decoding apparatus may process the type of the first bit as an information bit. Since the first subsequence comprises only the first bit, the decoding means may use the sequence of hard values as a result of the decoding of the first subsequence. For example, the decoding apparatus determines that the hard value sequence corresponding to the first sub-sequence is [10 1], and the decoding result of the first sub-sequence is [10 1].

In the above embodiment of the present application, the first subsequence only includes a first bit, the type of the first bit is a known bit, and a value range of the first bit is consistent with a value range of the PC bit. The decoding device may use the type of the first bit as a PC bit to obtain a first position distribution sequence. Since the types of bits indicated by the first position distribution sequence are PC bits, the decoding apparatus can adapt a decoding algorithm (e.g. a decoding algorithm corresponding to PC bits) according to the first position distribution sequence, thereby decoding the sub-sequence including known bits. Because the bit value of the PC bit is irrelevant to the soft value, when the decoding device decodes the first subsequence according to the decoding algorithm corresponding to the PC bit, the soft value calculation of the first subsequence is not needed, so that the overhead caused by the soft value calculation is saved, and the decoding efficiency is improved.

Example 2

Referring to fig. 7, fig. 7 is a flowchart illustrating another decoding method for a polar code according to an embodiment of the present disclosure. In the method, a decoding device takes the type of a first bit as a frozen bit, and decodes a first subsequence based on a decoding algorithm corresponding to the frozen bit, wherein the first subsequence only includes the first bit.

S701: the decoding device receives a message from the encoding device, wherein the message comprises a first subsequence which only comprises a first bit, and the value range of the first bit is consistent with the value range of the frozen bit.

The value range of the first bit is consistent with the value range of the frozen bit, which means that the possible value of the first bit after decoding is consistent with the possible value of the frozen bit after decoding. For example, the bit value of the frozen bit is fixed to 0, and the bit value of the first bit is also fixed to 0. For another example, when the first bit does not carry information, the bit value of the first bit may be fixed to 0. The possible value of the first bit may be determined by a position distribution sequence corresponding to the known bit, for example, the position distribution sequence of the known bit may only include 100, where 100 represents the known bit and the bit value of the known bit is 0.

The specific implementation manner of S701 is the same as the specific implementation method of S501 in fig. 5, and is not described herein again.

S702: the decoding device takes the type of the first bit as a frozen bit, and decodes the first subsequence according to a decoding algorithm corresponding to the frozen bit to obtain a hard value sequence corresponding to the first subsequence, wherein the hard value sequence only comprises a first hard value corresponding to the first bit.

When the range of the first bit coincides with the range of the frozen bit, the characteristics of the different types of bits may be as shown in table 2. As shown in table 2, as for the decoding result, the value range of the known bit is consistent with the value range of the frozen bit, the value range is fixed to 0, and the value range of the PC bit and the information bit is 0 or 1. In terms of the value characteristics, the value characteristics of the known bit are consistent with the value characteristics of the frozen bit, the decoding result is known and soft value calculation is not needed, while the value of the PC bit is related to the earlier decoding result although the soft value calculation is not needed, and the value of the information bit not only needs the soft value calculation but also is related to the earlier decoding result. For checksum error correction, the known bits are identical to the PC bits and need to participate in the check but are not flipped when error correction is performed, while the frozen bits do not participate in the check, and the information bits need to participate in both the check and the error correction but are also flipped when error correction is performed. As far as the bearer content is concerned, the known bits are identical to the information bits and are used to carry messages, while the frozen bits have no practical meaning for fixed padding and the PC bits are used to carry check values. The decoding result and the checksum error correction characteristic are used for determining how to decode, and are used in bit type identification and hard value calculation; the value-taking characteristics can be used for determining whether to perform soft value calculation or not, and can be used in the soft value calculation; the bearer content is used to determine whether to extract bits as information, which will be used in the hard value trace back.

Table 2: table for comparing characteristics of different types of bits

The decoding algorithm cannot adapt to a sub-sequence comprising known bits, but can adapt to a sub-sequence comprising at least one of frozen bits, PC bits or information bits. The decoding algorithm is determined in the type identification of the bits and used in the hard value calculation. And the type identification of the bit and the hard value calculation are related to the decoding result, the check sum and the error correction. Considering that the decoding result of the known bit coincides with the decoding result of the frozen bit, the decoding means may process the type of the first bit as the frozen bit in the type recognition of the bit and the hard value calculation. Although the first bit cannot participate in the check after the type of the first bit is taken as the frozen bit, the decoding process can be simplified, more simplified (simplify) decoding code patterns are generated, and the decoding parallelism can be improved.

As an example, in the type identification of the bit and the hard value calculation, the decoding apparatus may process the type of the first bit as a frozen bit; in the soft value calculation, the decoding device can treat the type of the first bit as a frozen bit; in hard value backtracking, the decoding apparatus may process the type of the first bit as an information bit, as shown in fig. 8. It should be understood that since the decoding means may treat the PC bit as the frozen bit in the soft value calculation, the decoding means may also treat the type of the first bit as the PC bit in the soft value calculation.

In S702, the first subsequence includes only the first bit, and the decoding apparatus uses the type of the first bit as the frozen bit, so that the decoding apparatus can decode the first subsequence according to a decoding algorithm corresponding to the frozen bit, thereby implementing decoding of the known bit. Specifically, the decoding device may map the type of the first bit in the first subsequence to the frozen bit according to the second field in the uplink control message or the fourth field in the downlink control message, so as to obtain the first position distribution sequence. Alternatively, the decoding apparatus may map the type of the first bit in the first subsequence to the frozen bit according to the position distribution sequence corresponding to the first subsequence, so as to obtain the first position distribution sequence. The decoding device may determine a decoding algorithm corresponding to the first subsequence according to the first position distribution sequence, and decode the first subsequence according to the decoding algorithm corresponding to the first subsequence, so as to obtain a hard value sequence corresponding to the first subsequence. Since only the first bit is included in the first sub-sequence, and the type of the bit indicated by the first position distribution sequence is only the frozen bit, the decoding algorithm corresponding to the first sub-sequence may be the decoding algorithm corresponding to the frozen bit. For example, the decoding algorithm corresponding to the frozen bit may be used to indicate that the bit value of the frozen bit is 0. As another example, the freeze bit may also be used to indicate that no check of the bit value of the information bit is involved in the acquisition.

When the first subsequence is decoded, the type of the bits indicated by the first position distribution sequence is only the frozen bits, and the decoding device may determine the hard value sequence corresponding to the first subsequence directly according to the position distribution sequence corresponding to the first subsequence without performing soft value calculation on the first subsequence. For example, 000, 110, and 111 indicate the freeze bits, 001 and 010 indicate the information bits, 011 indicates the PC bits, and 100 indicates the known bit with a value of 0. The position distribution sequence corresponding to the first sub-sequence is [100 100 100], and the decoding apparatus can determine that the hard value sequence corresponding to the first sub-sequence is [00 ] according to the position distribution sequence corresponding to the first sub-sequence. Wherein only a first hard value corresponding to the first bit is included in the sequence of hard values.

S703: the decoding device extracts a first hard value from the hard value sequence as a decoding result.

In the hard value backtracking process, the decoding apparatus may process the type of the first bit as an information bit. Since the first subsequence comprises only the first bits, the decoding means can use the sequence of hard values as a result of the decoding of the first subsequence. For example, the hard value sequence corresponding to the first sub-sequence determined by the decoding apparatus is [00 0], and the decoding result of the first sub-sequence is [00 0].

In the above embodiments of the present application, the first subsequence includes only the first bit, the type of the first bit is a known bit, and a value range of the first bit is consistent with a value range of the frozen bit. The decoding means may use the type of the first bit as the frozen bit to obtain the first position distribution sequence. Since the types of bits indicated by the first position distribution sequence are all the frozen bits, the decoding apparatus can adapt a decoding algorithm (such as a decoding algorithm corresponding to the frozen bits) according to the first position distribution sequence, thereby implementing decoding of the sub-sequence including the known bits. Because the bit value of the frozen bit is irrelevant to the soft value, when the decoding device decodes the first subsequence according to the decoding algorithm corresponding to the frozen bit, the soft value calculation of the first subsequence is not needed, so that the expense caused by the soft value calculation is saved, and the decoding efficiency is improved.

Example 3

Referring to fig. 9, fig. 9 is a flowchart illustrating another decoding method for a polar code according to an embodiment of the present application, in which a decoding apparatus uses a type of a first bit as a target type, and decodes a first subsequence based on a decoding algorithm corresponding to the target type, where the first subsequence only includes the first bit, and the target type includes a PC bit or a freeze bit.

S901: the decoding means receives a message from the encoding means, the message comprising a first sub-sequence comprising only the first bit.

The specific implementation manner of S901 is consistent with the specific implementation manner of S501 in fig. 5 or the specific implementation manner of S701 in fig. 7, and is not described herein again.

The value range of the first bit can be consistent with the value range of the PC bit, namely the value range is 0 or 1; or the value range of the first bit may be consistent with the value range of the frozen bit, that is, the value range is 0.

Further, the decoding device may use the type of the first bit as a target type according to the value range of the first bit, and decode the first subsequence based on a decoding algorithm corresponding to the target type to obtain a hard value sequence corresponding to the first subsequence. Wherein the sequence of hard values includes only a first hard value corresponding to the first bit, the target type including a PC bit or a freeze bit.

For example, in the type identification and hard value calculation of the bit, the decoding apparatus may process the type of the first bit as a target type; in the soft value calculation, the decoding device can treat the type of the first bit as a frozen bit; in hard value backtracking, the decoding apparatus may process the type of the first bit as an information bit, as shown in fig. 10. It should be understood that since the decoding means may treat the PC bit as the frozen bit in the soft value calculation, the decoding means may also treat the type of the first bit as the PC bit in the soft value calculation.

Specifically, if the value range of the first bit is consistent with the value range of the PC bit, the target type is the PC bit, and the decoding apparatus may execute the contents shown in S902 and S904; if the value range of the first bit is consistent with the value range of the frozen bit, the target type is the frozen bit, and the decoding apparatus may execute the contents shown in S903 and S904.

S902: when the value range of the first bit is consistent with the value range of the PC bit, the decoding device may use the type of the first bit as the PC bit, and decode the first subsequence according to a decoding algorithm corresponding to the PC bit, to obtain a hard value sequence corresponding to the first subsequence.

The specific implementation manner of S902 is the same as the specific implementation manner of S502 in fig. 5, and is not described herein again.

S903: when the value range of the first bit is consistent with the value range of the frozen bit, the decoding device may use the type of the first bit as the frozen bit, and decode the first subsequence according to a decoding algorithm corresponding to the frozen bit, to obtain a hard value sequence corresponding to the first subsequence.

The specific implementation manner of S903 is the same as the specific implementation manner of S702 in fig. 7, and is not described herein again.

S904: the decoding device extracts a first hard value from the hard value sequence as a decoding result of the first subsequence.

In the hard value backtracking process, the decoding apparatus may process the type of the first bit as an information bit. Since the first subsequence comprises only the first bits, the decoding means can use the sequence of hard values as a result of the decoding of the first subsequence. For example, the decoding apparatus determines that the hard value sequence corresponding to the first sub-sequence is [10 1], and the decoding result of the first sub-sequence is [10 1].

In the above embodiments of the present application, the first subsequence includes only the first bit, and the type of the first bit is a known bit. The decoding device may use the type of the first bit as a target type to obtain the first position distribution sequence, where the target type is a PC bit or a frozen bit. Since the types of bits indicated by the first position distribution sequence are both PC bits or both frozen bits, the decoding apparatus can adapt a decoding algorithm according to the first position distribution sequence, thereby implementing decoding of the sub-sequence including known bits. Because the bit value of the frozen bit or the PC bit is irrelevant to the soft value, when the decoding device decodes the first subsequence according to the decoding algorithm corresponding to the target type, the soft value calculation of the first subsequence is not needed, so that the overhead generated by the soft value calculation is saved, and the decoding efficiency is improved.

Example 4

Referring to fig. 11, fig. 11 is a flowchart illustrating another decoding method for a polar code according to an embodiment of the present disclosure. In the method, a decoding device decodes a first subsequence according to a decoding algorithm corresponding to the type of a first bit, wherein the first subsequence only includes the first bit.

S1101: the decoding means receives a message from the encoding means, the message comprising a first sub-sequence comprising only the first bit.

The value range of the first bit may be the same as the value range of the PC bit, or the value range of the frozen bit, which is not limited in the embodiment of the present application. The specific implementation manner of S1101 is the same as the specific implementation manner of S501 in fig. 5, or the specific implementation manner of S701 in fig. 7, or the specific implementation manner of S901 in fig. 9, and is not described herein again.

S1102: the decoding device decodes the first subsequence according to a first decoding algorithm corresponding to the known bit to obtain a hard value sequence corresponding to the first subsequence, wherein the hard value sequence only comprises a first hard value corresponding to the first bit.

A first decoding algorithm corresponding to the known bit may be used to decode the first bit. Since the first sub-sequence comprises only the first bit, the first decoding algorithm for the known bit can also be used to decode the first sub-sequence.

Illustratively, a first decoding algorithm corresponding to the known bit may be used to determine the bit value of the first bit. For example, the position distribution sequence corresponding to the known bit includes 100 and 101, where 100 represents the known bit with a bit value of 0 and 101 represents the known bit with a bit value of 1. The decoding device may determine the hard value sequence corresponding to the first sub-sequence according to the position distribution sequence corresponding to the first sub-sequence and the position distribution sequence corresponding to the known bit. For example, the position distribution sequence corresponding to the first sub-sequence is [100 101 100], and the hard value sequence corresponding to the first sub-sequence is [01 10]. The first decoding algorithm for the known bits may also be used to characterize the contribution to the bit value of the acquired information bit. For example, hard value decision is made according to the decoding result of the known bit and the bit value of the known bit.

Without specific description, the first decoding algorithm corresponding to the known bit may be referred to as a first decoding algorithm corresponding to a type of the first bit, or referred to as a first decoding algorithm, which is not limited in this embodiment of the present application.

S1103: the decoding device extracts a first hard value from the hard value sequence as a decoding result of the first subsequence.

In the hard value backtracking process, the decoding device extracts the first hard values of all the first bits from the hard value sequence as the decoding result of the first subsequence according to the position distribution sequence corresponding to the first subsequence.

In the above-described embodiments of the present application, only the first bit is included in the first subsequence, and the type of the first bit is a known bit. The decoding means may decode the first subsequence according to a decoding algorithm corresponding to the known bits. In the decoding process, soft value calculation is not needed, decoding of the subsequence comprising the known bits is achieved, overhead is reduced, and decoding efficiency can be improved.

A specific process of decoding the second subsequence is described below, where the second subsequence includes a first bit and a second bit, the first bit is of a known type, and the second bit is of a PC bit, a frozen bit, or at least one of an information bit.

Example 5

Referring to fig. 12, fig. 12 is a flowchart illustrating another decoding method for a polar code according to an embodiment of the present disclosure. In the method, a decoding device takes the type of the first bit as a PC bit, decodes the first bit based on a decoding algorithm corresponding to the PC bit, and decodes the second bit based on a second decoding algorithm corresponding to the type of the second bit, thereby realizing the decoding of the second subsequence. Wherein the second sub-sequence comprises the first bit and the second bit.

S1201: the decoding device receives a message from the encoding device, wherein the message comprises a second subsequence, the second subsequence comprises a first bit and a second bit, and the value range of the first bit is consistent with the value range of the PC bit.

The decoding means receives a message from the encoding means, which message may comprise a second sub-sequence comprising the first bit and the second bit. For example, the second subsequence comprises 8 bits, the 8 bits being of the type [ known bit frozen bit PC bit information bit known bit information bit ] in sequence. The message may be an uplink control message or a downlink control message. For example, when the encoding device is the terminal 300 and the decoding device is the network device 200, the message may be an uplink control message. For another example, when the encoding device is the first network device 201 and the decoding device is the second network device 202, the message may be a downlink control message. When the message is an uplink control message, the uplink control message includes a first field and a second field, the first field is used for indicating whether a first bit is included in a second subsequence, and the second field is used for indicating the position of the first bit in the second subsequence. Or, when the message is a downlink control message, the downlink control message includes a third field and a fourth field, where the third field is used to indicate whether the second subsequence includes the first bit, and the fourth field is used to indicate a position of the first bit in the second subsequence. The first field and/or the second field may be predefined fields or reserved fields in the uplink control message, and the third field and/or the fourth field may be predefined fields or reserved fields in the downlink control message.

The value range of the first bit is consistent with the value range of the PC bit, which means that the possible value of the first bit after decoding is consistent with the possible value of the PC bit after decoding. For example, the possible value of the decoded PC bit is 0 or 1, and the possible value of the decoded first bit is 0 or 1. For another example, when the first bit carries information, the possible value of the first bit is 0 or 1. The possible value of the first bit may be determined by a position distribution sequence corresponding to the known bit, for example, the position distribution sequence of the known bit may include 100 and 102, where 100 denotes the known bit and the bit value of the known bit is 0, and 101 denotes the known bit and the bit value of the known bit is 0. The possible values of the PC bits can be determined by the decoding result of the last subsequence, and the specific implementation process thereof can refer to the prior art.

S1202: the decoding device takes the type of the first bit as a PC bit to obtain a first position distribution sequence.

The value range of the first bit is consistent with the value range of the PC bit, and the decoding device can process the type of the first bit as the PC bit according to the characteristics of the different types of bits in table 1. For example, in the type identification of the bit and the hard value calculation, the decoding apparatus may process the type of the first bit as a PC bit; in the soft value calculation, the decoding device can treat the type of the first bit as a frozen bit; in hard value backtracking, the decoding apparatus may process the type of the first bit as an information bit, as shown in fig. 6. The specific implementation process of the method can be referred to as content in S502 in fig. 5, and is not described herein again.

Specifically, the decoding apparatus may map the type of the first bit included in the second subsequence to a PC bit (i.e., map a known bit to a PC bit) according to the second field in the uplink control message or the fourth field in the downlink control message, so as to obtain the first position distribution sequence. Alternatively, the decoding apparatus may determine the type of each bit in the second subsequence according to the position distribution sequence corresponding to the second subsequence, and map the type of the first bit with the known bit type in the second subsequence to the PC bit based on the type of each bit in the second subsequence. For example, 000, 110, and 111 indicate the freeze bits, 001 and 010 indicate the information bits, 011 indicates the PC bits, 100 indicates the known bits with a value of 0, and 101 indicates the known bits with a value of 1. The position distribution sequence corresponding to the second subsequence is [011 101 001 010], and the decoding apparatus can determine that the types of the bits in the second subsequence are [ PC bits known bit information bits ], and map the known bits to PC bits, so as to obtain the first position distribution sequence [011 011 011 011 001 010].

S1203: the decoding device determines a third decoding algorithm according to the first position distribution sequence, wherein the third decoding algorithm comprises a first decoding algorithm and a second decoding algorithm.

The third decoding algorithm may be configured to decode the second subsequence to obtain a hard value sequence corresponding to the second subsequence. In particular implementations, the third decoding algorithm may include soft value calculations and hard value calculations, or hard value calculations. Further, the third decoding algorithm may further include the first decoding algorithm and the second decoding algorithm, that is, the third decoding algorithm may implement all functions of the first decoding algorithm and implement all functions of the second decoding algorithm. The first decoding algorithm may be used to decode the first bit in the second subsequence, for example, when the decoding apparatus processes the type of the first bit as a PC bit, the first decoding algorithm is a decoding algorithm corresponding to the PC bit. The second decoding algorithm may be used for decoding the second bit in the second subsequence, for example, when the type of the second bit only includes the frozen bit, the second decoding algorithm is a decoding algorithm corresponding to the frozen bit.

In a possible implementation manner, the decoding apparatus may determine the first decoding algorithm and the second decoding algorithm respectively according to the first location distribution sequence. For example, the decoding device may determine information such as the number of first bits or the position of the first bits in the second subsequence from the distribution sequence of positions corresponding to the first position distribution sequence and the second subsequence, and determine the first decoding algorithm for decoding the first bits based on the information such as the number of first bits or the position of the first bits in the second subsequence.

The decoding apparatus may determine the type of the bits included in the second subsequence according to the first position distribution sequence, and determine the third decoding algorithm according to a combination manner and/or an arrangement manner of the types of the bits included in the second subsequence. Taking the combination manner as an example, different combination manners may correspond to the same decoding algorithm. For example, the combination mode 1 is [ frozen bit PC bit ], and the decoding algorithm corresponding to the combination mode 1 is decoding algorithm 1; the combination mode 2 is [ information bit PC bit ], and the decoding algorithm corresponding to the combination mode 2 is a decoding algorithm 2; the combination mode 3 is [ PC bit freezes bit information bit ], the decoding algorithm corresponding to the combination mode 3 is decoding algorithm 3; the combination mode 4 is [ information bit PC bit frozen bit ], and the decoding algorithm corresponding to the combination mode 4 is a decoding algorithm 2; are not listed here. The third decoding algorithm may be a simple decoding algorithm that is calculated and experimentally obtained with the best profit in advance according to at least one of the number of bits in the subsequence, the combination manner of the types of the bits in the subsequence, or the arrangement manner of the types of the bits in the subsequence.

Further, the decoding device may search, according to the combination mode and decoding algorithm correspondence table, a third decoding algorithm corresponding to the combination mode of the type of the bit indicated by the first position distribution sequence; or searching for a third decoding algorithm corresponding to the combination mode of the bit type indicated by the first position distribution sequence according to the identification number of the combination mode of the bit type indicated by the first position distribution sequence.

S1204: and the decoding device decodes the second subsequence according to a third decoding algorithm to obtain a hard value sequence corresponding to the second subsequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit.

In one example, the third decoding algorithm may not include soft value calculation when the information bit is not included in the type of the second bit. The decoding device does not need to perform soft value calculation on the second subsequence, so that the overhead generated by the soft value calculation can be saved, and the decoding efficiency is improved. Specifically, if the type of the second bit includes a frozen bit, the decoding apparatus may determine a hard value sequence corresponding to the second sub-sequence according to the position distribution sequence corresponding to the second sub-sequence, the first position distribution sequence, the bit value of the frozen bit, and the bit value of the known bit. If the type of the second bit comprises a PC bit, the decoding means may determine a hard value sequence corresponding to the second subsequence from the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit values of the PC bit and the bit values of the known bits. If the type of the second bit comprises a frozen bit and a PC bit, the decoding means may determine a hard value sequence corresponding to the second sub-sequence from the position distribution sequence corresponding to the second sub-sequence, the first position distribution sequence, the bit value of the PC bit, the bit value of the frozen bit, and the bit value of the known bit.

Taking the example that the second bit type includes the freeze bit, 000, 110, and 111 indicate the freeze bit, 001 and 010 indicate the information bit, 011 indicates the PC bit, 100 indicates the known bit with 0, and 101 indicates the known bit with 1. The position distribution sequence corresponding to the second subsequence is [111 100 101 000], and the first position distribution sequence is [111 011 000]. The decoding device may obtain hard values of bits in the second subsequence as [00 0] in sequence according to the first position distribution sequence, according to a decoding algorithm corresponding to the PC bits and a decoding algorithm corresponding to the frozen bits. Since the hard values of the known bits are obtained according to the decoding algorithm corresponding to the PC bits, and there may be errors, the decoding apparatus may determine that the bit 1 and the bit 2 are known bits according to the position distribution sequence corresponding to the second sub-sequence, and the bit value of the bit 1 is 0 and the bit value of the bit 2 is 1, and in combination with the hard values obtained according to the decoding algorithm corresponding to the frozen bits, may determine that the hard value sequence corresponding to the second sub-sequence is [00 1].

In another example, the third decoding algorithm includes soft value calculation when the information bits are included in the type of second bits. Meaning that the decoding means needs to perform soft value calculations and hard value calculations on the second subsequence. Specifically, if the type of the second bit only includes information bits, the decoding apparatus may determine the hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the bit value of the known bit. If the type of the second bit includes an information bit and a frozen bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, and the bit value of the frozen bit. If the type of the second bit comprises an information bit and a PC bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, and the bit value of the PC bit. If the type of the second bit includes an information bit, a PC bit and a frozen bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, the bit value of the PC bit and the bit value of the frozen bit.

Further, the decoding device may determine a decoding result of the second subsequence according to the hard value sequence. Specifically, if the type of the second bit includes the information bit, the decoding apparatus executes the content shown in S1205; if the type of the second bit does not include the information bit, the decoding apparatus executes the contents shown in S1206.

S1205: when the type of the second bit includes the information bit, the decoding means extracts a first hard value and a third hard value, which is a hard value corresponding to the information bit in the second bit, from the hard value sequence as a result of decoding of the second subsequence.

The decoding apparatus may map the type of the first bit to an information bit to obtain a mapped position distribution sequence, and extract a first hard value and a third hard value from the hard value sequence as a decoding result of the second subsequence based on the mapped position distribution sequence.

For example, 000, 110, and 111 indicate the freeze bits, 001 and 010 indicate the information bits, 011 indicates the PC bits, 100 indicates the known bits with a value of 0, and 101 indicates the known bits with a value of 1. The position distribution sequence corresponding to the second subsequence is [100 011 001], and the hard value sequence corresponding to the second subsequence is [01 1]. The decoding means may map the type of the first bit to the information bit to obtain a mapped position distribution sequence of [001 011 001]. The decoding device extracts the hard values of all the information bits from the hard value sequence based on the mapped position distribution sequence to obtain [01 ], and the decoding result is [01 ]. Wherein the decoding result of the first bit in the second subsequence is [0], and the decoding result of the information bit in the second subsequence is [ 1].

S1206: when the type of the second bit does not include the information bit, the decoding means extracts the first hard value from the hard value sequence as a decoding result of the second subsequence.

The decoding device may map the type of the first bit to an information bit to obtain a mapped position distribution sequence, and extract the first hard value from the hard value sequence as a decoding result of the second subsequence based on the mapped position distribution sequence.

In the above embodiments of the present application, the second subsequence includes a first bit and a second bit, the type of the first bit is a known bit, the value range of the first bit is consistent with the value range of the PC bit, and the type of the second bit includes at least one of the PC bit, the freeze bit, or the information bit. The decoding device may use the type of the first bit as a PC bit, decode the first bit based on a decoding algorithm corresponding to the PC bit, and decode the second bit based on a decoding algorithm corresponding to the type of the second bit, thereby implementing decoding of a subsequence including known bits. When the type of the second bit does not include the information bit, the decoding device does not need to perform soft value calculation on the second subsequence, thereby saving the overhead generated by performing soft value calculation and improving the decoding efficiency.

Example 6

Referring to fig. 13, fig. 13 is a flowchart illustrating another decoding method for a polar code according to an embodiment of the present invention. In the method, a decoding device takes the type of a first bit as a frozen bit, decodes the first bit based on a decoding algorithm corresponding to the frozen bit, and decodes a second bit based on a second decoding algorithm corresponding to the type of the second bit, thereby realizing the decoding of a second subsequence. Wherein the second sub-sequence comprises the first bit and the second bit.

S1301: the decoding device receives a message from the encoding device, wherein the message comprises a second subsequence, the second subsequence comprises a first bit and a second bit, and the value range of the first bit is consistent with the value range of the frozen bit.

The value range of the first bit is consistent with the value range of the frozen bit, which means that the possible value of the first bit after decoding is consistent with the possible value of the frozen bit after decoding. For example, the bit value of the frozen bit is fixed to 0, and the bit value of the first bit is also fixed to 0. For another example, when the first bit does not carry information, the bit value of the first bit may be fixed to 0. For example, the position distribution sequence of the known bit may only include 100, where 100 represents the known bit and the bit value of the known bit is 0.

The specific implementation manner of S1301 is the same as the specific implementation method of S1201 in fig. 12, and is not described herein again.

S1302: the decoding device takes the type of the first bit as a frozen bit to obtain a first position distribution sequence.

The value range of the first bit is consistent with the value range of the frozen bit, and according to the characteristics of the bits of different types in the table 2, the decoding device can treat the type of the first bit as the frozen bit. For example, in the type identification of the bit and the hard value calculation, the decoding apparatus may process the type of the first bit as a frozen bit; in the soft value calculation, the decoding device can treat the type of the first bit as a frozen bit; in hard value backtracking, the decoding apparatus may process the type of the first bit as an information bit, as shown in fig. 8. The specific implementation process of this embodiment can be referred to as the content in S702 in fig. 7, and is not described herein again.

Specifically, the decoding device may map the type of the first bit included in the second subsequence to a frozen bit (i.e., map the known bit to a frozen bit) according to the second field in the uplink control message or the fourth field in the downlink control message, so as to obtain the first position distribution sequence. Alternatively, the decoding apparatus may determine the type of each bit in the second subsequence according to the position distribution sequence corresponding to the second subsequence, and map the type of the first bit with the known bit type in the second subsequence to be the frozen bit based on the type of each bit in the second subsequence. For example, 000, 110, and 111 indicate the freeze bits, 001 and 010 indicate the information bits, 011 indicates the PC bits, 100 indicates the known bits with a value of 0, and 101 indicates the known bits with a value of 1. The position distribution sequence corresponding to the second subsequence is [011 101 001 010], and the decoding apparatus can determine that the types of the bits in the second subsequence are [ PC bits known bit information bits ], and map the known bits to the frozen bits, so as to obtain the first position distribution sequence of [011 000 001 010].

S1303: the decoding device determines a third decoding algorithm according to the first position distribution sequence, wherein the third decoding algorithm comprises a first decoding algorithm and a second decoding algorithm.

And the third decoding algorithm is used for decoding the second subsequence to obtain a hard value sequence corresponding to the second subsequence. The third decoding algorithm may include soft value calculation and hard value calculation, or hard value calculation. Further, the third decoding algorithm may further include the first decoding algorithm and the second decoding algorithm, that is, the third decoding algorithm may implement all functions of the first decoding algorithm and implement all functions of the second decoding algorithm. The first decoding algorithm may be used to decode the first bit in the second subsequence, for example, when the decoding apparatus treats the type of the first bit as the frozen bit, the first decoding algorithm is a decoding algorithm corresponding to the frozen bit. The second decoding algorithm may be used to decode the second bit in the second subsequence, for example, when the type of the second bit only includes PC bits, the second decoding algorithm is an algorithm corresponding to the PC bits.

The specific implementation manner of S1303 is the same as the specific implementation manner of S1202 in fig. 12, and is not described herein again.

S1304: and the decoding device decodes the first subsequence according to a third decoding algorithm to obtain a hard value sequence corresponding to the first subsequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit.

In one example, the third decoding algorithm may not include soft value calculation when the information bits are not included in the type of second bits. The decoding device does not need to perform soft value calculation on the second subsequence, so that the overhead generated by the soft value calculation can be saved, and the decoding efficiency is improved. Specifically, if the type of the second bit includes a frozen bit, the decoding device may determine a hard value sequence corresponding to the second sub-sequence according to the position distribution sequence corresponding to the second sub-sequence, the first position distribution sequence, the bit value of the frozen bit, and the bit value of the known bit. If the type of the second bit comprises a PC bit, the decoding device may determine a hard value sequence corresponding to the second sub-sequence according to the position distribution sequence corresponding to the second sub-sequence, the first position distribution sequence, the bit value of the PC bit, and the bit value of the known bit. If the type of the second bit comprises a frozen bit and a PC bit, the decoding means may determine a hard value sequence corresponding to the second sub-sequence from the position distribution sequence corresponding to the second sub-sequence, the first position distribution sequence, the bit value of the PC bit, the bit value of the frozen bit, and the bit value of the known bit.

In another example, the third decoding algorithm includes soft value calculation when the information bits are included in the type of the second bits. Meaning that the decoding apparatus needs to perform soft value calculation and hard value calculation for the second subsequence. Specifically, if the type of the second bit only includes information bits, the decoding apparatus may determine the hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the bit value of the known bit. If the type of the second bit includes an information bit and a frozen bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, and the bit value of the frozen bit. If the type of the second bit includes an information bit and a PC bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, and the bit value of the PC bit. If the second bit type includes an information bit, a PC bit, and a frozen bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, the bit value of the PC bit, and the bit value of the frozen bit.

Further, the decoding device may determine a decoding result of the second subsequence according to the hard value sequence. Specifically, if the type of the second bit includes the information bit, the decoding means executes the contents shown in S1305; if the type of the second bit does not include the information bit, the decoding apparatus performs the contents shown in S1306.

S1305: when the type of the second bit includes the information bit, the decoding means extracts a first hard value and a third hard value, which is a hard value corresponding to the information bit in the second bit, from the hard value sequence as a decoding result of the second subsequence.

The decoding device may map the type of the first bit to an information bit to obtain a mapped position distribution sequence, and extract the first hard value and the third hard value from the hard value sequence as a decoding result of the second subsequence based on the mapped position distribution sequence.

S1306: when the type of the second bit does not include the information bit, the decoding means extracts the first hard value from the hard value sequence as a decoding result of the second subsequence.

In the above embodiments of the present application, the second subsequence includes a first bit and a second bit, the type of the first bit is a known bit, the value range of the first bit is consistent with the value range of the frozen bit, and the type of the second bit includes at least one of a PC bit, a frozen bit, or an information bit. The decoding device may use the type of the first bit as a frozen bit, decode the first bit based on a decoding algorithm corresponding to the frozen bit, and decode the second bit based on a decoding algorithm corresponding to the type of the second bit, thereby decoding the subsequence including the known bit. When the type of the second bit does not include the information bit, the decoding device does not need to perform soft value calculation on the second subsequence, thereby saving the overhead generated by performing soft value calculation and improving the decoding efficiency.

Example 7

Referring to fig. 14, fig. 14 is a flowchart illustrating another decoding method for a polar code according to an embodiment of the present disclosure. In the method, a decoding device takes the type of a first bit as a target type, decodes the first bit based on a decoding algorithm corresponding to the target type, and decodes a second bit based on a second decoding algorithm corresponding to the type of the second bit, thereby realizing the decoding of a second subsequence. Wherein the second subsequence includes the first bit and the second bit and the target type includes the PC bit or the freeze bit.

S1401: the decoding means receives a message from the encoding means, the message comprising a second sub-sequence comprising the first bit and the second bit.

The specific implementation manner of S1401 is the same as the specific implementation manner of S1201 in fig. 12 or the specific implementation manner of S1301 in fig. 13, and is not described herein again.

Further, the decoding device may use the type of the first bit as a target type according to the value range of the first bit, decode the first bit based on a first decoding algorithm corresponding to the target type, and decode the second bit based on a second decoding algorithm corresponding to the type of the second bit. Wherein the target type includes a PC bit or a freeze bit.

Specifically, if the value range of the first bit is consistent with the value range of the PC bit, the target type is the PC bit, and the decoding apparatus may execute the contents shown in S1402 and S1404; if the value range of the first bit is consistent with the value range of the frozen bit, the target type is the frozen bit, and the decoding means may execute the contents shown in S1403 and S1404.

S1402: when the value range of the first bit is consistent with the value range of the PC bit, the decoding device may use the type of the first bit as the PC bit to obtain the first position distribution sequence.

The value range of the first bit is consistent with the value range of the PC bit, and the decoding device can process the type of the first bit as the PC bit according to the characteristics of the different types of bits in table 1. For example, in the type identification of the bit and the hard value calculation, the decoding apparatus may process the type of the first bit as a PC bit; in the soft value calculation, the decoding device can treat the type of the first bit as a frozen bit; in hard value backtracking, the decoding apparatus may process the type of the first bit as an information bit, as shown in fig. 6. The specific implementation process of this embodiment can be referred to as the content in S1202 in fig. 12, and is not described herein again.

S1403: when the value range of the first bit is consistent with the value range of the frozen bit, the decoding device may use the type of the first bit as the frozen bit to obtain the first position distribution sequence.

The value range of the first bit is consistent with the value range of the frozen bit, and according to the characteristics of the bits of different types in the table 1, the decoding device can treat the type of the first bit as the frozen bit. For example, in the type identification of the bit and the hard value calculation, the decoding apparatus may process the type of the first bit as a frozen bit; in the soft value calculation, the decoding device can treat the type of the first bit as a frozen bit; in hard value backtracking, the decoding apparatus may process the type of the first bit as an information bit, as shown in fig. 8. The specific implementation process of this embodiment can be referred to as content in S1302 in fig. 13, which is not described herein again.

S1404: the decoding device determines a third decoding algorithm according to the first position distribution sequence, wherein the third decoding algorithm comprises a first decoding algorithm and a second decoding algorithm.

The specific implementation process of S1404 is consistent with the specific implementation process shown in S1203 in fig. 12 or the specific implementation process shown in S1303 in fig. 13, and is not described herein again.

S1405: and the decoding device decodes the second subsequence according to a third decoding algorithm to obtain a hard value sequence corresponding to the second subsequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit.

In one example, the third decoding algorithm may not include soft value calculation when the information bits are not included in the type of second bits. The decoding device does not need to perform soft value calculation on the second subsequence, so that the overhead generated by the soft value calculation can be saved, and the decoding efficiency is improved. Specifically, if the type of the second bit includes a frozen bit, the decoding device may determine a hard value sequence corresponding to the second sub-sequence according to the position distribution sequence corresponding to the second sub-sequence, the first position distribution sequence, the bit value of the frozen bit, and the bit value of the known bit. If the type of the second bit comprises a PC bit, the decoding means may determine a hard value sequence corresponding to the second subsequence from the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit values of the PC bit and the bit values of the known bits. If the second bit type includes a frozen bit and a PC bit, the decoding means may determine a hard value sequence corresponding to the second sub-sequence based on the position distribution sequence corresponding to the second sub-sequence, the first position distribution sequence, the bit value of the PC bit, the bit value of the frozen bit, and the bit value of the known bit.

In another example, the third decoding algorithm includes soft value calculation when the information bits are included in the type of second bits. Meaning that the decoding means needs to perform soft value calculations and hard value calculations on the second subsequence. Specifically, if the type of the second bit only includes information bits, the decoding apparatus may determine the hard value sequence corresponding to the second subsequence by the maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the bit value of the known bit. If the type of the second bit includes an information bit and a frozen bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, and the bit value of the frozen bit. If the type of the second bit comprises an information bit and a PC bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, and the bit value of the PC bit. If the second bit type includes an information bit, a PC bit, and a frozen bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, the bit value of the PC bit, and the bit value of the frozen bit.

Further, the decoding device may determine a decoding result of the second sub-sequence according to the hard value sequence. Specifically, if the type of the second bit includes the information bit, the decoding apparatus executes the content shown in S1406; if the second type of the second bits does not include information bits, the decoding means executes the contents shown in S1407.

S1406: when the type of the second bit includes the information bit, the decoding means extracts a first hard value and a third hard value, which is a hard value corresponding to the information bit in the second bit, from the hard value sequence as a decoding result of the second subsequence.

S1407: when the type of the second bit does not include the information bit, the decoding means extracts the first hard value from the hard value sequence as a result of decoding the second subsequence.

The decoding apparatus may map the type of the first bit to an information bit to obtain a mapped position distribution sequence, and extract the first hard value from the hard value sequence as a decoding result of the second subsequence based on the mapped position distribution sequence.

In the above embodiments of the present application, the second subsequence includes a first bit and a second bit, the type of the first bit is a known bit, and the type of the second bit includes at least one of a PC bit, a frozen bit, or an information bit. The decoding device may decode the first bit based on a decoding algorithm corresponding to the target type with the type of the first bit as the target type, and decode the second bit based on a decoding algorithm corresponding to the type of the second bit, thereby decoding the subsequence including the known bit. When the type of the second bit does not include the information bit, the decoding device does not need to perform soft value calculation on the second subsequence, thereby saving the overhead generated by performing soft value calculation and improving the decoding efficiency.

Example 8

Referring to fig. 15, fig. 15 is a flowchart illustrating another decoding method for a polar code according to an embodiment of the present disclosure. In the method, the decoding device may decode the first bit according to a decoding algorithm corresponding to the known bit and decode the second bit corresponding to the type of the second bit, thereby implementing decoding of the second subsequence. Wherein the second sub-sequence comprises the first bit and the second bit.

S1501: the decoding means receives a message from the encoding means, the message comprising a second sub-sequence comprising the first bit and the second bit.

The value range of the first bit may be the same as the value range of the PC bit, or the value range of the frozen bit, which is not limited in the embodiment of the present application. The specific implementation manner of S1501 is the same as the specific implementation manner of S1201 in fig. 12, or the specific implementation manner of S1301 in fig. 13, or the specific implementation manner of S1401 in fig. 14, and is not described herein again.

S1502: and the decoding device respectively decodes the first bit and the second bit in the second subsequence according to a first decoding algorithm corresponding to the known bit and a second decoding algorithm corresponding to the second bit type to obtain a hard value sequence corresponding to the second subsequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit.

The first decoding algorithm may be configured to decode a first bit in the second subsequence, and the second decoding algorithm may be configured to decode a second bit in the second subsequence. The third decoding algorithm may be configured to decode the second subsequence to obtain a hard value sequence corresponding to the second subsequence. In particular implementations, the third decoding algorithm may include soft value calculations and hard value calculations, or may include hard value calculations. Further, the third decoding algorithm may further include the first decoding algorithm and the second decoding algorithm, that is, the third decoding algorithm may implement all functions of the first decoding algorithm and implement all functions of the second decoding algorithm.

In one example, the third decoding algorithm may not include soft value calculation when the information bits are not included in the type of second bits. The decoding device does not need to perform soft value calculation on the second subsequence, so that the expense caused by the soft value calculation can be saved, and the decoding efficiency is improved. Specifically, if the type of the second bit includes a frozen bit, the decoding apparatus may determine a hard value sequence corresponding to the second sub-sequence according to the position distribution sequence corresponding to the second sub-sequence, the first position distribution sequence, the bit value of the frozen bit, and the bit value of the known bit. If the type of the second bit comprises a PC bit, the decoding means may determine a hard value sequence corresponding to the second subsequence from the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit values of the PC bit and the bit values of the known bits. If the type of the second bit comprises a frozen bit and a PC bit, the decoding means may determine a hard value sequence corresponding to the second sub-sequence from the position distribution sequence corresponding to the second sub-sequence, the first position distribution sequence, the bit value of the PC bit, the bit value of the frozen bit, and the bit value of the known bit.

In another example, the third decoding algorithm includes soft value calculation when the information bits are included in the type of the second bits. Meaning that the decoding apparatus needs to perform soft value calculation and hard value calculation for the second subsequence. Specifically, if the type of the second bit only includes information bits, the decoding apparatus may determine the hard value sequence corresponding to the second subsequence by the maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the bit value of the known bit. If the type of the second bit comprises an information bit and a frozen bit, the decoding means may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, and the bit value of the frozen bit. If the type of the second bit includes an information bit and a PC bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, and the bit value of the PC bit. If the type of the second bit includes an information bit, a PC bit and a frozen bit, the decoding apparatus may determine a hard value sequence corresponding to the second subsequence by a maximum likelihood estimation algorithm according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, the bit value of the known bit, the bit value of the PC bit and the bit value of the frozen bit.

Further, the decoding device may determine a decoding result of the second sub-sequence according to the hard value sequence. Specifically, if the type of the second bit includes an information bit, the decoding apparatus executes the content shown in S1205; if the second type of the second bits does not include information bits, the decoding apparatus executes the contents shown in S1206.

S1503: when the type of the second bit includes the information bit, the decoding means extracts a first hard value and a third hard value, which is a hard value corresponding to the information bit in the second bit, from the hard value sequence as a result of decoding of the second subsequence.

The decoding device may extract the first hard values of all known bits and the third hard values of all information bits from the hard value sequence as the decoding result of the second subsequence according to the position distribution sequence corresponding to the second subsequence.

S1504: when the type of the second bit does not include the information bit, the decoding means extracts the first hard value from the hard value sequence as a decoding result of the second subsequence.

The decoding device may extract the first hard values of all known bits from the hard value sequence as the decoding result of the second subsequence according to the position distribution sequence corresponding to the second subsequence.

In the above embodiments of the present application, the second subsequence includes a first bit and a second bit, and the type of the first bit is a known bit. The decoding device may decode the first bit according to a decoding algorithm corresponding to the known bit, and decode the second bit according to a second decoding algorithm corresponding to the type of the second bit, so as to decode the subsequence including the known bit. In the decoding process, if the type of the second bit does not include the information bit, soft value calculation is not needed, so that the overhead can be reduced, and the decoding efficiency can be improved.

The following describes a decoding apparatus corresponding to the decoding method shown in fig. 11 or fig. 15. Referring to fig. 16, fig. 16 is a schematic structural diagram of a decoding apparatus according to an embodiment of the present disclosure, where the decoding apparatus can be used to implement the process shown in fig. 11 or fig. 15. The decoding apparatus 1600 can be applied to the communication system 100 shown in fig. 1A or fig. 1B. The decoding apparatus 1600 may be the network apparatus 101 or at least one chip in the network apparatus 101, or may also be the terminal 102 or at least one chip in the terminal 102. As shown in fig. 16, decoding apparatus 1600 includes a lighting calculation unit 1601, a path splitting unit 1602, a path calculation unit 1603, and a likelihood probability calculation unit 1604.

Lighting calculation section 1601 is configured to perform lighting calculation for the lighting sequence and send the lighting calculation result to likelihood probability calculation section 1604. Here, the lighting sequence refers to a subsequence including known bits, such as the first subsequence in fig. 11 or the second subsequence in fig. 15. The lighting calculation means decoding the first bit according to a decoding algorithm corresponding to the known bit. The lighting calculation unit 1601 may execute the content shown in S1102 in fig. 11 or a part of the content shown in S1502 in fig. 15.

Path splitting unit 1602, configured to determine bit values of all information bits in the subsequence according to a decoding algorithm corresponding to a combination manner of types of bits in the subsequence, and send the bit values of all information bits in the subsequence to path calculating unit 1603 and likelihood probability calculating unit 1604. For example, a sub-sequence includes N bits, N being an integer greater than or equal to 1. The N bits can be split into at most 2 ^N As a result of the decoding, the path splitting unit 1602 can combine different bit typesMode-dependent decoding algorithm determination 2 ^N A decoding result, and the 2 ^N Reliability of the decoding result, and according to the 2 ^N The reliability of the decoding results retains one or more decoding results with good reliability, and then the bit values of all information bits in the N bits are determined according to the one or more decoding results.

A path calculating unit 1603, configured to determine path branch metrics of N bits and path branch metrics for decoding the next subsequence according to the path metric of the previous subsequence and bit values of all information bits in the subsequence. The bit values of the information bits traversed by the path splitting unit 1602 and the corresponding maximum likelihood probabilities may have a deviation, for example, the traversal result is 0, but the sign of the maximum likelihood probability is negative. In this case, path calculating unit 1603 may perform absolute value accumulation on the maximum likelihood probabilities of information bits with deviations in N bits to obtain current path branch metrics of N bits, and accumulate the path branch metrics of multiple decoding to obtain accumulated path metrics of the current path (traversal values of information bits between different paths are different, and path branch metrics are also different). And the accumulated path metrics for the different paths are sorted, and the path metric for the best (e.g., the path metric value is the smallest) path metric or metrics are retained for decoding the next subsequence.

Wherein, the path branch metric and the path metric are used for representing the reliability of the decoding result, and the larger the value of the path branch metric and the path metric, the less reliable the decoding result is.

Likelihood probability calculation unit 1604 determines the bit value of each of the N bits. The bit value of the known bit is obtained by lighting calculation section 1601, the bit value of the information bit is obtained by path splitting calculation section 1602, path calculation section 1603, and likelihood probability calculation section 1604, the bit value of the frozen bit is fixed to 0, and the bit value of the pc bit is accumulated based on the bit value shift of the information bit in the previous subsequence. The bit value of each of the N bits may also be used for the determination of the bit value of the PC bit in the next subsequence.

One or more of the path splitting unit 1602, the path calculating unit 1603, or the likelihood calculating unit 1604 is used for executing the flow shown in S1102 to S1103 or executing the flow shown in S1502 to S1504. For example, the type of the second bit includes information bits, and the path splitting unit 1602, the path calculating unit 1603, and the likelihood calculating unit 1604 are configured to execute the flow shown in S1502. If the type of the second bit does not include information bits, likelihood calculation unit 1604 is configured to execute the flow shown in S1102.

For example, the sub-sequence is [ bit 0 bit 1 bit 2 bit 3], and the position distribution sequence corresponding to the sub-sequence is [000 001 100]. 000. 110 and 111 represent the freeze bits, 001 and 010 the information bits, 011 the PC bits, 100 the known bits with a value of 0, and 101 the known bits with a value of 1. The maximum likelihood probability of 4 bits is a, b, c, d in turn (b, c are all positive numbers). The 4 bit types are, in order, a frozen bit, an information bit, and a known bit. The lighting calculation unit 1601 determines that the value of bit 3 is 0, and the likelihood probability calculation unit 1604 determines that the value of bit 0 is 0. The path splitting unit 1602 traverses the values of two information bits, i.e., bit 1 and bit 2, to obtain four decoding results of the 2 bits, where the four decoding results are 0000, 0010, 0100, and 0110 in sequence. The path calculation unit 1603 compares the four decoding results with the maximum likelihood probabilities b and c to obtain path branch metrics of 4 bits, which are respectively 0, c, b and b + c, and it can be known that the decoding reliability ranking is 0000> < 0010> < 0100> < 0110. The best path obtained by the likelihood probability calculation unit 1604 is 0000, and according to the path, it can be determined that the value of bit 1 is 0, the value of bit 2 is 0, and the values of the preceding bit 0 and bit 3 are combined, so that the values of the 4 bits are sequentially 0, and 0. Further, the path calculating unit 1603 reserves the best path (for example, the path with the decoding result of 0000) or paths for decoding the next sub-sequence.

Fig. 17 shows a communication apparatus 1700 according to an embodiment of the present application, which is used for implementing the function of the decoding apparatus in the above method. The communication device 1700 includes a receiver 1701 and a decoder 1702. The communication apparatus 1700 can implement the methods described in embodiments 1 to 8.

As an example, the receiver 1701 is configured to receive a message from an encoding apparatus, where the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is a known bit;

the decoder 1702 is configured to take the type of the first bit as a target type, and decode the first bit according to a first decoding algorithm corresponding to the target type, where the target type includes a parity bit or a frozen bit.

Optionally, the sub-sequence further comprises a second bit, the type of the second bit comprises at least one of a freeze bit, a parity bit, or an information bit, and the decoder 1702 is further configured to: and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit.

Optionally, the message is an uplink control message or a downlink control message.

Optionally, the uplink control message includes a first field and a second field, where the first field is used to indicate whether the subsequence includes the first bit, and the second field is used to indicate a position of the first bit in the subsequence.

Optionally, the downlink control message includes a third field and a fourth field, where the third field is used to indicate whether the subsequence includes the first bit, and the fourth field is used to indicate a position of the first bit in the subsequence.

Optionally, the decoder 1702 is specifically configured to: when the value range of the first bit is consistent with the value range of the parity bit, taking the type of the first bit as the parity bit; or when the value range of the first bit is consistent with the value range of the frozen bit, the type of the first bit is taken as the frozen bit.

Optionally, the decoder 1702 is specifically configured to: mapping the type of the first bit to a target type to obtain a position distribution sequence, wherein the position distribution sequence is used for representing the type of each bit in the subsequence; respectively determining a first decoding algorithm and a second decoding algorithm according to the position distribution sequence; and decoding the subsequence according to a third decoding algorithm, wherein the third decoding algorithm comprises a first decoding algorithm and a second decoding algorithm.

Optionally, when the information bit is not included in the type of second bit, the third decoding algorithm does not include soft value calculation for determining likelihood probabilities that the bit values of the respective bits in the subsequence are 0 or 1.

Optionally, when the information bit is included in the type of the second bit, the third decoding algorithm includes a soft value calculation for determining a likelihood probability that the bit value of each bit in the subsequence is 0 or 1.

Optionally, when the information bit is not included in the second bit type, the decoder 1702 is further configured to: decoding the subsequence according to a third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit; the first hard value is extracted from the sequence of hard values as a decoding result.

Optionally, when the information bit is included in the second bit type, the decoder 1702 is further configured to: decoding the subsequence according to a third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit; a first hard value and a third hard value are extracted from the sequence of hard values as a result of the decoding, the third hard value being a hard value corresponding to an information bit in the second bits.

Fig. 18 shows a communication apparatus 1800 according to an embodiment of the present application, which is used for implementing the function of the encoding apparatus in the above method. The communication device 1800 includes an encoder 1801 and a transmitter 1802. The communications apparatus 1800 can implement the method described in fig. 4 in the previous embodiments.

As an example, the encoder 1801 is configured to obtain a first bit and a second bit, respectively, where the type of the first bit is a known bit, and the type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit; generating a pilot sequence based on the first bit; coding the second bit to obtain a first coding sequence; a transmitter 1802, configured to send a second code sequence to the decoding apparatus when determining to send the pilot sequence, where the second code sequence includes the pilot sequence and the first code sequence.

Optionally, when it is determined that the pilot sequence is not to be transmitted, the second code sequence is the first code sequence.

Optionally, the second coding sequence is an uplink control message, or a downlink control message.

Optionally, the encoder 1801 is further configured to: when the air interface resources are sufficient, determining to send a pilot frequency sequence; or, when the air interface resource is in shortage, determining not to send the pilot frequency sequence.

The embodiment of the present application further provides a communication apparatus 1900, and the communication apparatus 1900 may be configured to execute the method described in the communication apparatus 1700.

Some or all of the above methods may be implemented by hardware or may be implemented by software. When implemented in hardware, as shown in fig. 19, the communication apparatus 1900 includes: an input interface circuit 1901 for implementing the functions implemented by the receiver 1701; logic 1902 to implement the functions implemented by the decoder 1702.

Alternatively, the communication device may be a chip or an integrated circuit when embodied.

An embodiment of the present application further provides a communication apparatus 2000, and the communication apparatus 2000 may be configured to perform the method described in the communication apparatus 1800.

Some or all of the above methods may be implemented by hardware or may be implemented by software. When implemented by hardware, as shown in fig. 20, the communication apparatus 2000 includes: a logic circuit 2001 for implementing the functions implemented by the encoder 1801; an output interface circuit 2002 for implementing the functions implemented by the transmitter 1802.

As shown in fig. 21, the communication apparatus provided in this embodiment of the present application may be a network device, and may also be an apparatus in the network device (for example, a chip or a system on a chip or a chip set or a part of a chip for performing a function of a related method). Alternatively, the apparatus may be a terminal, or an apparatus in a terminal (e.g., a chip or a system of chips or a chip set or a part of a chip for performing the function of the related method). Wherein the apparatus may be a system-on-a-chip. In the embodiment of the present application, the chip system may be composed of a chip, and may also include a chip and other discrete devices. The apparatus 2100 includes at least one processor 2120 for implementing functions of an encoding device or a decoding device in the methods provided by the embodiments of the present application. The apparatus 2100 may also include a communication interface 2110. In the present embodiment, the communication interface 2110 may be a transceiver, circuit, bus, module or other type of communication interface for communicating with other devices through a transmission medium. For example, the communication interface 2110 is used for devices in the apparatus 2100 to communicate with other devices when implementing functions of the encoding apparatus. Illustratively, the other device may be a decoding apparatus. The processor 2120 transmits and receives data using the communication interface 2110 and is used to implement the methods implemented by the encoding device or the decoding device of the above-described method embodiments.

The apparatus 2100 may also include at least one memory 2130 for storing program instructions and/or data. The memory 2130 is coupled to the processor 2120. The coupling in the embodiments of the present application is an indirect coupling or a communication connection between devices, units or modules, and may be an electrical, mechanical or other form for information interaction between the devices, units or modules. The processor 2120 may cooperate with the memory 2130. Processor 2120 may execute program instructions stored in memory 2130. At least one of the at least one memory may be included in the processor.

The embodiment of the present application does not limit the specific connection medium among the communication interface 2110, the processor 2120 and the memory 2130. In the embodiment of the present application, the memory 2130, the processor 2120 and the communication interface 2110 are connected through a bus 2140 in fig. 21, the bus is shown by a thick line in fig. 21, and the connection manner among other components is only schematically illustrated and not limited. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 21, but this does not mean only one bus or one type of bus.

In the embodiments of the present application, the processor may be a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in a processor.

In the embodiment of the present application, the memory may be a nonvolatile memory, such as a Hard Disk Drive (HDD) or a solid-state drive (SSD), and may also be a volatile memory, for example, a random-access memory (RAM). The memory is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory in the embodiments of the present application may also be circuitry or any other device capable of performing a storage function for storing program instructions and/or data.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims

A method for decoding a polar code, the method comprising:

receiving a message from an encoding device, wherein the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit;

and taking the type of the first bit as a target type, and decoding the first bit according to a first decoding algorithm corresponding to the target type, wherein the target type comprises a parity check bit or a frozen bit.
The method of claim 1, wherein the subsequence further includes a second bit, wherein the type of the second bit includes at least one of the frozen bit, the parity bit, or the information bit, and wherein the method further comprises:

and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit.
The method according to claim 1 or 2, wherein the message is an uplink control message or a downlink control message.
The method of claim 3, wherein the uplink control message comprises a first field and a second field, the first field is used for indicating whether the first bit is included in the subsequence, and the second field is used for indicating a position of the first bit in the subsequence.
The method of claim 3, wherein a third field and a fourth field are included in the downlink control message, the third field is used for indicating whether the first bit is included in the subsequence, and the fourth field is used for indicating a position of the first bit in the subsequence.
The method according to any one of claims 1 to 5, wherein taking the type of the first bit as a target type comprises:

when the value range of the first bit is consistent with the value range of the parity bit, taking the type of the first bit as the parity bit; or,

and when the value range of the first bit is consistent with the value range of the frozen bit, taking the type of the first bit as the frozen bit.
The method according to any one of claims 2 to 6, wherein taking the type of the first bit as a target type comprises:

mapping the type of the first bit to the target type to obtain a position distribution sequence, wherein the position distribution sequence is used for representing the type of each bit in the subsequence;

decoding the first bit according to a first decoding algorithm corresponding to the target type, and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit, including:

respectively determining the first decoding algorithm and the second decoding algorithm according to the position distribution sequence;

decoding the sub-sequence according to a third decoding algorithm, the third decoding algorithm comprising the first decoding algorithm and the second decoding algorithm.
The method of claim 7, wherein when the information bit is not included in the type of the second bit, the third decoding algorithm does not include a soft value calculation for determining a likelihood probability that a bit value of each bit in the subsequence is 0 or 1.
The method of claim 7, wherein when the information bit is included in the type of the second bit, the third decoding algorithm comprises a soft value calculation for determining a likelihood probability that a bit value of each bit in the subsequence is 0 or 1.
The method of claim 7 or 8, wherein when the information bit is not included in the type of the second bit, the method further comprises:

decoding the subsequence according to the third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit;

extracting the first hard value from the sequence of hard values as a coding result.
The method of claim 7 or 9, wherein when the information bit is included in the type of the second bit, the method further comprises:

decoding the subsequence according to the third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit;

and extracting the first hard value and a third hard value from the hard value sequence as a decoding result, wherein the third hard value is a hard value corresponding to the information bit in the second bit.
A method for coding a polar code, the method comprising:

respectively acquiring a first bit and a second bit, wherein the type of the first bit is a known bit, and the type of the second bit comprises at least one of a frozen bit, a parity bit or an information bit;

generating a pilot sequence based on the first bit;

coding the second bit to obtain a first coding sequence;

and when the pilot frequency sequence is determined to be sent, sending a second coding sequence to a decoding device, wherein the second coding sequence comprises the pilot frequency sequence and the coding sequence.
The method of claim 12 wherein the second code sequence is the first code sequence when it is determined that the pilot sequence is not to be transmitted.
The method according to claim 12 or 13, wherein the second coding sequence is an uplink control message or a downlink control message.
The method according to claim 14, wherein the second coding sequence comprises at least one sub-sequence, and for a sub-sequence, the uplink control message comprises a first field and a second field, the first field is used to indicate whether the first bit is included in the sub-sequence, and the second field is used to indicate a position of the first bit in the sub-sequence.
The method according to claim 14, wherein the second coding sequence comprises at least one sub-sequence, and for a sub-sequence, the downlink control message comprises a third field and a fourth field, the third field is used to indicate whether the first bit is included in the sub-sequence, and the fourth field is used to indicate a position of the first bit in the sub-sequence.
The method according to any one of claims 12 to 16, further comprising:

when the air interface resources are sufficient, determining to send the pilot frequency sequence; or,

and when the air interface resources are in shortage, determining not to send the pilot frequency sequence.
A communication apparatus, characterized in that the communication apparatus comprises a receiver and a decoder:

the receiver is used for receiving a message from an encoding device, wherein the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit;

the decoder is configured to use the type of the first bit as a target type, and decode the first bit according to a first decoding algorithm corresponding to the target type, where the target type includes a parity bit or a frozen bit.
The apparatus of claim 18, wherein the sub-sequence further comprises a second bit, wherein a type of the second bit comprises at least one of the frozen bits, the parity bits, or information bits, and wherein the decoder is further configured to:

and decoding the second bit according to a second decoding algorithm corresponding to the type of the second bit.
The apparatus of claim 18 or 19, wherein the message is an uplink control message or a downlink control message.
The apparatus of claim 20, wherein the uplink control message comprises a first field and a second field, the first field is used for indicating whether the first bit is included in the subsequence, and the second field is used for indicating a position of the first bit in the subsequence.
The apparatus of claim 20, wherein a third field and a fourth field are included in the downlink control message, the third field is used for indicating whether the first bit is included in the subsequence, and the fourth field is used for indicating a position of the first bit in the subsequence.
The apparatus according to any of claims 18 to 22, wherein the decoder is configured to:

when the value range of the first bit is consistent with the value range of the parity bit, taking the type of the first bit as the parity bit; or,

and when the value range of the first bit is consistent with the value range of the frozen bit, taking the type of the first bit as the frozen bit.
The apparatus according to any one of claims 19 to 23, wherein the decoder is specifically configured to:

mapping the type of the first bit to the target type to obtain a position distribution sequence, wherein the position distribution sequence is used for representing the type of each bit in the subsequence;

respectively determining the first decoding algorithm and the second decoding algorithm according to the position distribution sequence;

decoding the sub-sequence according to a third decoding algorithm, the third decoding algorithm comprising the first decoding algorithm and the second decoding algorithm.
The apparatus of claim 24, wherein when the information bit is not included in the type of the second bit, the third coding algorithm does not include a soft value calculation for determining a likelihood probability that a bit value of each bit in the subsequence is 0 or 1.
The apparatus of claim 24, wherein when the information bit is included in the type of the second bit, the third decoding algorithm comprises a soft value calculation for determining a likelihood probability that a bit value of each bit in the subsequence is 0 or 1.
The apparatus of claim 24 or 25, wherein when the information bit is not included in the second bit type, the decoder is further configured to:

decoding the subsequence according to the third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit;

the first hard value is extracted from the sequence of hard values as a coding result.
The apparatus of claim 24 or 26, wherein when the information bit is included in the type of the second bit, the decoder is further configured to:

decoding the subsequence according to the third decoding algorithm to obtain a hard value sequence, wherein the hard value sequence comprises a first hard value corresponding to the first bit and a second hard value corresponding to the second bit;

and extracting the first hard value and a third hard value from the hard value sequence as a decoding result, wherein the third hard value is a hard value corresponding to the information bit in the second bit.
A communication apparatus, characterized in that the communication apparatus comprises an encoder and a transmitter:

the encoder is configured to obtain a first bit and a second bit, respectively, where the type of the first bit is a known bit, and the type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit; generating a pilot sequence based on the first bit; coding the second bit to obtain a first coding sequence;

and the transmitter is used for transmitting a second coding sequence to a decoding device when the pilot sequence is determined to be transmitted, wherein the second coding sequence comprises the pilot sequence and the first coding sequence.
The apparatus of claim 29 wherein the second code sequence is the first code sequence when it is determined not to transmit the pilot sequence.
The apparatus according to claim 29 or 30, wherein the second coding sequence is an uplink control message or a downlink control message.
The apparatus of claim 31, wherein the uplink control message comprises a first field and a second field, and wherein the first field is used for indicating whether the first bit is included in the subsequence, and wherein the second field is used for indicating a position of the first bit in the subsequence.
The apparatus of claim 31, wherein a third field and a fourth field are included in the downlink control message, the third field is used for indicating whether the first bit is included in the subsequence, and the fourth field is used for indicating a position of the first bit in the subsequence.
The apparatus of any one of claims 29-33, wherein the encoder is further configured to:

when the air interface resources are sufficient, determining to send the pilot frequency sequence; or,

and when the air interface resources are in shortage, determining not to send the pilot frequency sequence.
A communications apparatus, comprising:

the device comprises an input interface circuit, a decoding device and a decoding device, wherein the input interface circuit is used for receiving a message from the encoding device, the message comprises a subsequence to be decoded, the subsequence comprises a first bit, and the type of the first bit is a known bit;

logic circuitry for performing the method of any one of claims 1 to 11 based on the subsequence.
A communications apparatus, comprising:

the logic circuit is used for respectively acquiring a first bit and a second bit, wherein the type of the first bit is a known bit, and the type of the second bit comprises at least one of a frozen bit, a parity bit or an information bit; generating a pilot sequence based on the first bit; encoding said second bit to obtain an encoded sequence, performing the method of any one of claims 12 to 17;

an output interface circuit for sending an encoded message to a decoding device, the encoded message including the pilot sequence and the encoded sequence.
A communications apparatus, comprising:

a memory for storing a program;

a processor for executing the program stored by the memory, the program, when executed, causing the communication device to perform the method of any of claims 1-11 or 12-17.
The apparatus of claim 37, wherein the processor comprises the memory.
The device of claim 37 or 38, wherein the communication device is a chip or an integrated circuit.
A computer readable storage medium having computer readable instructions stored thereon which, when run on a communication device, cause the communication device to perform the method of any of claims 1-11 or 12-17.
A computer program product, which, when run on a communication device, causes the communication device to perform the method of any one of claims 1 to 11 or 12 to 17.