CN114996176A - Memory access method, computing device and storage medium - Google Patents
Memory access method, computing device and storage medium Download PDFInfo
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- CN114996176A CN114996176A CN202210902319.8A CN202210902319A CN114996176A CN 114996176 A CN114996176 A CN 114996176A CN 202210902319 A CN202210902319 A CN 202210902319A CN 114996176 A CN114996176 A CN 114996176A
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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Abstract
Provided are an access method, a computing device and a storage medium. The memory access method comprises the following steps: binary translation is carried out on the client instruction; storing the translated instructions in a target address space of the guest logical address space that is not used by the guest; running the translated instruction in the target address space to obtain first mapping relation information indicating the mapping relation between the logic address of the client and the physical address of the client; and accessing the physical address of the host according to the first mapping relation information. The translated instruction is placed in a target address space of a logic address space of the client, which is not used by the client, so that the translation process of the memory access instruction can be simplified, and the execution performance of the memory access instruction is improved.
Description
Technical Field
The present application relates to the field of virtualization technologies, and in particular, to a memory access method, a computing device, and a storage medium.
Background
Binary translation may be used to translate guest instructions into host instructions, thereby enabling system-wide virtualization across instruction set architectures. In the related art, the binary translation process of the memory access instruction needs to perform multiple address conversions, so that the execution performance of the memory access instruction of the client on the host is reduced.
Disclosure of Invention
The application provides a memory access method, a computing device and a storage medium, which are used for improving the execution performance of a memory access instruction of a client on a host.
In a first aspect, a memory access method is provided, where the method is applied to a host, a virtual machine management system runs on the host, the virtual machine management system is used to manage a guest running on the host, and the host and the guest are based on different instruction set architectures, and the method includes: performing binary translation on the instruction of the client to obtain a translated instruction; storing the translated instructions in a target address space, wherein the target address space is an address space in a logical address space of the guest that is not used by the guest; executing the translated instruction in the target address space to obtain first mapping relation information, wherein the first mapping relation information is used for indicating a mapping relation between a logic address of the client and a physical address of the client; and according to the first mapping relation information and the second mapping relation information, converting the address of the memory access instruction in the translated instruction into the physical address of the host to access the physical address of the host, wherein the second mapping relation information is used for indicating the mapping relation between the physical address of the client and the physical address of the host.
With reference to the first aspect, in some possible implementation manners, the executing the translated instruction in the target address space to obtain first mapping relationship information includes: running the translated instruction in the target address space to obtain third mapping relation information, wherein the format of the third mapping relation information is a format supported by an MMU (memory management unit) of the client; and performing format conversion on the third mapping relationship information to obtain the first mapping relationship information, wherein the format of the first mapping relationship information is a format supported by an MMU of the host.
With reference to the first aspect, in some possible implementation manners, the converting, according to the first mapping relationship information and the second mapping relationship information, an address of a memory access instruction in the translated instruction into a physical address of the host includes: and converting the address of the memory access instruction in the translated instruction into the physical address of the host machine in a hardware-assisted virtualization mode according to the first mapping relation information and the second mapping relation information.
With reference to the first aspect, in some possible implementation manners, the executing the translated instruction in the target address space to obtain first mapping relationship information includes: capturing a target interrupt generated in the translated instruction running process, wherein the target interrupt is an interrupt triggered by the condition that the first mapping relation information is not established; and responding to the target interrupt, and establishing the first mapping relation information.
With reference to the first aspect, in some possible implementations, the first mapping relationship information is stored in a logical address space of the client.
In a second aspect, a computing device is provided, the computing device being located on a host machine, a virtual machine management system running on the host machine, the virtual machine management system being configured to manage a guest machine running on the host machine, and the host machine and the guest machine being based on different instruction set architectures, the computing device comprising: the translation module is used for carrying out binary translation on the instruction of the client to obtain a translated instruction; a storage module, configured to store the translated instruction in a target address space, where the target address space is an address space in a logical address space of the client that is not used by the client; an obtaining module, configured to run the translated instruction in the target address space to obtain first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between a logical address of the client and a physical address of the client; and the conversion module is used for converting the address of the memory access instruction in the translated instruction into the physical address of the host according to the first mapping relation information and the second mapping relation information so as to access the physical address of the host, wherein the second mapping relation information is used for indicating the mapping relation between the physical address of the client and the physical address of the host.
With reference to the second aspect, in some possible implementations, the obtaining module is configured to run the translated instruction in the target address space to obtain third mapping relationship information, where a format of the third mapping relationship information is a format supported by an MMU of the client; and performing format conversion on the third mapping relationship information to obtain the first mapping relationship information, wherein the format of the first mapping relationship information is a format supported by an MMU of the host.
With reference to the second aspect, in some possible implementation manners, the conversion module is configured to convert an address of a memory access instruction in the translated instruction into a physical address of the host in a hardware-assisted virtualization manner according to the first mapping relationship information and the second mapping relationship information.
With reference to the second aspect, in some possible implementation manners, the obtaining module is configured to capture a target interrupt generated in an operation process of the translated instruction, where the target interrupt is an interrupt triggered by non-establishment of the first mapping relationship information; and responding to the target interrupt, and establishing the first mapping relation information.
With reference to the second aspect, in some possible implementations, the first mapping relationship information is stored in a logical address space of the client.
In a third aspect, a computing device is provided, comprising: a memory for storing code; a processor configured to execute the code stored in the memory to perform the method according to the first aspect or any one of the possible implementations of the first aspect.
In a fourth aspect, a computer-readable storage medium is provided, on which code for performing the method according to the first aspect or any one of its possible implementations is stored.
In a fifth aspect, a computer program code is provided, comprising instructions for performing the method according to the first aspect or any one of the possible implementations of the first aspect.
The translated instruction is placed in the logic address space of the client, which is beneficial to executing address conversion by using a hardware auxiliary means, the translation process of the virtualized management system to the memory access instruction is reduced, and the execution performance of the memory access instruction is improved.
Drawings
Fig. 1 is a diagram illustrating an exemplary system architecture of a host to which an embodiment of the present invention is applicable.
Fig. 2 is a schematic flow chart of a memory access method provided in an embodiment of the present application.
Fig. 3 is an exemplary diagram of a storage manner of a translated instruction according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a computing device according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
Fig. 1 is a diagram illustrating an exemplary system architecture of a host (or host platform) to which the embodiments of the present invention can be applied. As shown in fig. 1, the bottom layer of the host 100 is provided with hardware 110 that supports host operation. The hardware 110 may include, for example, one or more of the following: a Central Processing Unit (CPU), a Memory Management Unit (MMU), and the like. The MMU may be an MMU that supports hardware virtual machine technology. For example, the MMU may support nested page table techniques or extended page table techniques. On top of the hardware 110, there is running an operating system 120 of the host. The host 100 may run various types of applications 130 through the operating system 120.
The host 100 supports a guest mode of operation (i.e., a guest or guest platform can be run on the host). To maintain and/or manage the guest operating mode, a virtual machine management system 140 may be run on the host 100. The Virtual Machine management system 140 may be a Virtual Machine Manager (VMM) or an emulator.
The virtual machine management system 140 may be used to manage guest machines 150 (including guest machine 150a and guest machine 150b in fig. 1) running on host machine 100. For example, the virtual machine management system 140 may provide the hardware environment, such as CPU, memory, etc., required for the operation of the client 150.
The instruction set architecture upon which host 100 and client 150 are based may be different. For example, the instruction set architecture upon which host 100 is based may be an arm instruction set architecture; the instruction set mechanism upon which client 150 is based may be the x86 architecture. As another example, the instruction set architecture upon which host 100 is based may be the x86 instruction set architecture; the instruction set mechanism upon which client 150 is based may be an arm architecture. In addition, clients 150a and 150b may be based on the same instruction set architecture or may be based on different instruction set architectures.
Since host 100 and guest 150 are based on different instruction set architectures, if guest 150 is desired to run on host 100, the instructions of guest 150 need to be binary translated first. The following briefly introduces binary translation techniques.
The binary translation technology is a technology for directly translating and operating binary instructions of an executable program, and is an important means for realizing the compatibility of different instruction set architectures. In binary translation techniques, the platform before instruction translation may be referred to as a guest platform and the platform after instruction translation may be referred to as a host platform. By translating the binary instructions of the client to the host platform, the client platform system can be operated on the host platform, so that the full-system virtualization of the cross-instruction-set architecture is realized.
At present, a binary translation engine mainly adopts a pure software simulation method to realize the simulation of a memory access instruction. However, simulating the access instruction based on the binary translation technology results in low execution efficiency of the access instruction, and the main reason is that multiple address conversions are required to be performed to realize the simulation of the access instruction based on the binary translation technology.
Specifically, in the binary translation engine, the guest instruction is translated and then runs in the logical address space of the host, and the memory access instruction of the guest needs to perform the following 3 times of address conversion when being executed: 1. the binary translation engine converts a client logical Address (or a Guest Virtual Address (GVA)) into a client Physical Address (GPA); 2. the binary translation engine converts the physical Address of the client into a logical Address of a Host (or called Host Virtual Address, HVA)); 3. the Host translates the Host logical Address to a Host Physical Address (HPA). Of the 3 address translations described above, the first 2 address translations are performed entirely by software, which incurs a large amount of overhead. Generally, a memory access instruction of a client often needs more than ten instructions to simulate, and the efficiency is very low.
In view of the above problem, the memory access method provided in the embodiment of the present application is described in more detail below with reference to fig. 2.
Fig. 2 is a schematic flowchart illustrating a memory access method provided in an embodiment of the present application. The method of fig. 2 may be applied to a host. The host may be any type of computing device (or electronic device) that supports virtualization technologies, such as a server, a desktop, a laptop, etc. The host may be implemented, for example, using the system architecture shown in FIG. 1.
Referring to fig. 2, in step S210, an instruction of a client is binary translated to obtain a translated instruction. The binary translation referred to in step S210 may include dynamic translation and/or static translation. For example, the guest instructions may be statically translated first. The translated instructions may then be fully optimized. Dynamic translation can then be used to compensate for scenarios that cannot be resolved by static translation (e.g., dynamic translation is used to translate jump instructions that cannot be translated during static translation). Of course, dynamic translation of guest instructions may be performed directly in other embodiments.
In step S220, the translated instruction is stored (or placed) in the target address space. The target address space is part of the logical address space of the client. In some embodiments, the target address space refers to an address space in the logical address space of the client that is not used by the client (or the client operating system). That is, instructions executed and/or data generated by the guest operating system are not stored in the segment of target address space. Storing the translated instructions in an address space that is not used by the guest (or the guest operating system) can avoid the translated instructions from affecting the layout of the memory space for instructions and/or data of the guest operating system, and can also avoid conflicts between the translated instructions and the instructions and/or data of the guest operating system.
The target address space may be a reserved address space of the logical address space at design time (e.g., an abnormal address space of an operating system). Alternatively, the target address space may be a reserved segment of unused address space in the operating system's legal address space. The target address space may be created by way of an internal placement driver or the like.
Taking FIG. 3 as an example, the target address space may be a contiguous segment of address space in the client logical address space. The target address space may be located between a user logical address space and a kernel logical address space of the client.
The translated instructions stored in the target address space may include one or more of the following information: kernel translation block, user translation block. In addition, the target address space may also store emulation data (or architecture emulation data) generated during the emulation of a client's instructions. For example, the target address space may store additional variables, simulation registers, etc. used by the translated instructions when running.
As mentioned previously, the target address space belongs to the client logical address space. The physical address space corresponding to the logical address space may be provided by the virtual machine management system. The mapping between the logical address space and the physical address space may be maintained by a virtual machine management system. In addition, the virtual machine management system can also be responsible for the allocation and release process of the logical address space.
In step S230, the translated instruction in the target address space is executed. Before the translated instruction is executed, the operating environment of the virtual machine management system can be configured, and the program counter points to the starting address of the translated instruction stored in the logic space of the client machine. After the operation of a certain translated instruction sequence is finished, the next instruction sequence can be executed according to the jump target. In addition, the virtual machine management system may provide a register context required for the translated instructions to run. The virtual machine management system can capture the guest logical space switching process and synchronize to the register context at runtime.
By performing step S230, the first mapping relationship information may be acquired. The first mapping information may be used to indicate a mapping between a logical address of the client (or called a virtual address of the client) and a physical address of the client. The first mapping relationship information may be, for example, page table information (describing a mapping relationship between a logical page and a physical page).
The first mapping relationship information may be stored in a client physical address space.
In step S240, according to the first mapping relationship information and the second mapping relationship information, an address of a memory access instruction (a memory address accessed by the memory access instruction) in the translated instruction is converted into a physical address of the host, so as to access the physical address of the host. The second mapping information may be used to indicate a mapping between physical addresses of the guest and physical addresses of the host. The second mapping relationship information may be, for example, page table information. Step S240 directly converts the address of the access instruction into the physical address of the host through two-stage address conversion, thereby simplifying the translation process of the access instruction and improving the execution performance of the access instruction. Therefore, the embodiment of the application provides a full-system virtualization technology of a cross-instruction-set architecture, and high-performance virtualization of the cross-instruction-set architecture is achieved.
In order to further improve the execution performance of the memory access instruction, the address of the memory access instruction in the translated instruction can be converted into the physical address of the host machine in a hardware-assisted virtualization mode according to the first mapping relationship information and the second mapping relationship information. For example, the host MMU may support embedded page tables, extended page tables, or similar techniques, allowing two levels of translation of guest logical addresses to guest physical addresses, and guest physical addresses to host physical addresses. In some embodiments, the second level address translation may be done directly by caching the GVA-GPA mapping and the HVA-HPA mapping in the host TLB at the same time.
Since the guest and host are based on different instruction set architectures, the format of the mapping information supported by the MMU of the guest is typically different from the format of the mapping information supported by the MMU of the host. Therefore, in some embodiments, after the translated instruction in the target address space is executed, the third mapping relationship information may be obtained first (the format of the third mapping relationship information is supported by the MMU of the client), and then the third mapping relationship information may be subjected to format conversion to obtain the first mapping relationship information (the format of the first mapping relationship information is supported by the MMU of the host). Through the format conversion of the mapping relation information, the problem of compatibility of the mapping relation information under different instruction set architectures can be solved.
It was mentioned above that the first mapping information may be obtained based on an interrupt mechanism. For example, a target interrupt generated during the execution of the translated instruction may be captured (the target interrupt refers to an interrupt triggered by the first mapping relationship information not being established, and may be referred to as a page fault interrupt, for example); in response to the target interrupt, the first mapping relationship information may be established and maintained by the virtual machine management system. The above process may be performed by the virtual machine management system, that is, the virtual machine management system may capture a mapping process of a logical address of a client to a physical address of the client based on the above process. The following describes the interrupt (including the target interrupt) handling process of the virtual machine management system in detail.
For example, before running the translated instructions, the virtual machine management system may check whether there is an unprocessed interrupt in the current vCPU (virtual CPU of the guest), and if so, process the interrupt. If the translated instructions generate an interrupt when running on the vCPU, the virtual machine management system can decide whether the interrupt should be injected into the guest or handled by the virtual machine management system itself. For example, the virtual machine management system vCPU generates an interrupt due to a current instruction execution exception when running, and the exception belonging to the client is arbitrated by the virtual machine management system, for example: mapping between guest logical and physical addresses is not established, guest instruction execution errors, etc. In this case, the virtual machine management system needs to interrupt the current instruction, inject an interrupt into the guest, and continue to execute the current instruction after the processing of the guest interrupt handler is completed. If the vCPU of the vm management system generates an external interrupt from the vm management system interrupt controller while running, and the vm checks that the interrupt needs to be routed to the current client, for example: interrupts generated by the client, etc., the virtual machine management system may choose whether to interrupt the execution of the current instruction sequence. And for interruption which does not need to interrupt the current instruction sequence, the virtual machine management system makes a relevant mark on the vCPU and processes when the translated next instruction sequence is operated. For example, the virtual machine management system may provide a routine to select a next piece of guest instructions to repeatedly perform the aforementioned process based on the jump target of the current translated instruction sequence.
Method embodiments of the present application are described in detail above in conjunction with fig. 1-3, and apparatus embodiments of the present application are described in detail below in conjunction with fig. 4-5. It is to be understood that the description of the method embodiments corresponds to the description of the apparatus embodiments, and therefore reference may be made to the preceding method embodiments for parts not described in detail.
Fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application. The computing device 400 shown in fig. 4 is located on a host machine, the host machine runs a virtual machine management system, the virtual machine management system is used for managing a client machine running on the host machine, and the host machine and the client machine are based on different instruction set architectures, and the computing device 400 comprises a translation module 410, a storage module 420, an acquisition module 430 and a conversion module 440.
The storage module 420 may be configured to store the translated instructions in a target address space, where the target address space is an address space in the logical address space of the guest that is not used by the guest.
The obtaining module 430 may be configured to execute the translated instruction in the target address space to obtain first mapping information, where the first mapping information is used to indicate a mapping relationship between a logical address of the client and a physical address of the client.
The conversion module 440 may be configured to convert an address of a memory access instruction in the translated instruction into a physical address of the host according to the first mapping relationship information and second mapping relationship information, so as to access the physical address of the host, where the second mapping relationship information is used to indicate a mapping relationship between a physical address of the client and a physical address of the host.
Optionally, in some embodiments, the obtaining module 430 may be configured to run the translated instruction in the target address space to obtain third mapping relationship information, where a format of the third mapping relationship information is a format supported by an MMU of the client; and performing format conversion on the third mapping relationship information to obtain the first mapping relationship information, wherein the format of the first mapping relationship information is a format supported by an MMU of the host.
Optionally, in some embodiments, the conversion module 440 may be configured to convert an address of a memory access instruction in the translated instructions into a physical address of the host in a hardware-assisted virtualization manner according to the first mapping relationship information and the second mapping relationship information.
Optionally, in some embodiments, the obtaining module 430 may be configured to capture a target interrupt generated during the execution of the translated instruction, where the target interrupt is an interrupt triggered by non-establishment of the first mapping relationship information; and responding to the target interrupt, and establishing the first mapping relation information.
Optionally, in some embodiments, the first mapping relationship information is stored in a logical address space of the client.
Fig. 5 is a schematic structural diagram of a computing device according to another embodiment of the present application. The computing device 500 shown in fig. 5 may include a memory 510 and a processor 520. In some embodiments, the computing device 500 shown in fig. 5 may also include an input/output interface 530 and a transceiver 540. The memory 510, the processor 520, the input/output interface 530 and the transceiver 540 are connected via an internal connection path, the memory 510 is used for storing instructions, and the processor 520 is used for executing the instructions stored in the memory 520 to execute the memory access method described in any of the previous embodiments.
It should be understood that, in the embodiment of the present application, the processor 520 may adopt a general-purpose Central Processing Unit (CPU), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits, and is configured to execute a relevant program to implement the technical solutions provided in the embodiments of the present application.
It should also be appreciated that the transceiver 540 is also known as a communication interface, and that communications between the computing device 500 and other devices or communication networks are accomplished using transceiver means such as, but not limited to, transceivers.
The memory 510 may include both read-only memory and random-access memory, and provides instructions and data to the processor 520. A portion of processor 520 may also include non-volatile random access memory. For example, processor 520 may also store information of the device type.
In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 520. The method for requesting uplink transmission resources disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 510, and the processor 520 reads the information in the memory 1010 and completes the steps of the method in combination with the hardware. To avoid repetition, it is not described in detail here.
It should be understood that in the embodiments of the present application, the processor may be a Central Processing Unit (CPU), and the processor may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.
It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be read by a computer or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Versatile Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (16)
1. A memory access method is applied to a host machine, a virtual machine management system runs on the host machine, the virtual machine management system is used for managing a client machine running on the host machine, and the host machine and the client machine are based on different instruction set architectures,
the method comprises the following steps:
performing binary translation on the instruction of the client to obtain a translated instruction;
storing the translated instructions in a target address space, wherein the target address space is an address space in a logical address space of the guest that is not used by the guest;
executing the translated instruction in the target address space to obtain first mapping relation information, wherein the first mapping relation information is used for indicating a mapping relation between a logic address of the client and a physical address of the client;
and according to the first mapping relation information and the second mapping relation information, converting the address of the memory access instruction in the translated instruction into the physical address of the host to access the physical address of the host, wherein the second mapping relation information is used for indicating the mapping relation between the physical address of the client and the physical address of the host.
2. The method of claim 1, wherein the executing the translated instruction in the target address space to obtain first mapping information comprises:
running the translated instruction in the target address space to obtain third mapping relation information, wherein the format of the third mapping relation information is a format supported by an MMU (memory management unit) of the client;
and performing format conversion on the third mapping relationship information to obtain the first mapping relationship information, wherein the format of the first mapping relationship information is a format supported by an MMU of the host.
3. The method according to claim 2, wherein the converting an address of a memory access instruction in the translated instructions into a physical address of the host according to the first mapping relationship information and the second mapping relationship information includes:
and converting the address of the memory access instruction in the translated instruction into the physical address of the host machine in a hardware-assisted virtualization mode according to the first mapping relation information and the second mapping relation information.
4. The method of claim 1, wherein said executing the translated instruction in the target address space to obtain first mapping information comprises:
capturing a target interrupt generated in the translated instruction running process, wherein the target interrupt is an interrupt triggered by the condition that the first mapping relation information is not established;
and responding to the target interrupt, and establishing the first mapping relation information.
5. The method of claim 4, wherein the establishing the first mapping information in response to the target interrupt comprises:
sending the target interrupt to the client to run an interrupt handler of the client, so as to obtain third mapping relation information, wherein the format of the third mapping relation information is a format supported by an MMU of the client;
converting, by the virtual machine management system, the third mapping relationship information into the first mapping relationship information, where a format of the first mapping relationship information is a format supported by an MMU of the host.
6. The method according to any of claims 1-5, wherein the first mapping relationship information is stored in the target address space.
7. The method of any of claims 1-5, wherein the target address space is further used to store temporary data needed for the execution of the translated instruction.
8. The method of claim 1, further comprising:
and responding to the modification of the mapping relation between the logical address of the client and the physical address of the client by the client, and correspondingly modifying the first mapping relation information stored in the target address space.
9. A computing device located on a host machine having a virtual machine management system running thereon, the virtual machine management system being configured to manage a guest running on the host machine, and the host machine and the guest machine being based on different instruction set architectures,
the computing device includes:
the translation module is used for carrying out binary translation on the instruction of the client to obtain a translated instruction;
a storage module, configured to store the translated instruction in a target address space, where the target address space is an address space in a logical address space of the client that is not used by the client;
an obtaining module, configured to run the translated instruction in the target address space to obtain first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between a logical address of the client and a physical address of the client;
and the access module is used for accessing the physical address of the host according to the first mapping relation information.
10. The computing device according to claim 9, wherein the access module is configured to convert an address of a memory access instruction in the translated instruction into a physical address of the host according to the first mapping relationship information and second mapping relationship information, so as to access the physical address of the host, where the second mapping relationship information is used to indicate a mapping relationship between a physical address of the guest and a physical address of the host.
11. The computing device of claim 9, wherein the obtaining module is configured to run the translated instruction in the target address space to obtain third mapping relationship information, and a format of the third mapping relationship information is a format supported by an MMU of the client; and performing format conversion on the third mapping relationship information to obtain the first mapping relationship information, wherein the format of the first mapping relationship information is a format supported by an MMU of the host.
12. The computing device of claim 11, wherein the conversion module is configured to convert an address of a memory access instruction in the translated instruction into a physical address of the host in a hardware-assisted virtualization manner according to the first mapping relationship information and the second mapping relationship information.
13. The computing device according to claim 9, wherein the obtaining module is configured to capture a target interrupt generated during the execution of the translated instruction, where the target interrupt is an interrupt triggered by non-establishment of the first mapping relationship information; and responding to the target interrupt, and establishing the first mapping relation information.
14. The computing device of any of claims 9-13, wherein the first mapping information is stored in a logical address space of the client.
15. A computing device, comprising:
a memory for storing code;
a processor for executing code stored in the memory to perform the method of any of claims 1-8.
16. A computer-readable storage medium having stored thereon code for performing the method of any one of claims 1-8.
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