CN114256168A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN114256168A
CN114256168A CN202110835836.3A CN202110835836A CN114256168A CN 114256168 A CN114256168 A CN 114256168A CN 202110835836 A CN202110835836 A CN 202110835836A CN 114256168 A CN114256168 A CN 114256168A
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China
Prior art keywords
electrode
semiconductor chip
conductive
conductive bonding
semiconductor device
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Pending
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CN202110835836.3A
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English (en)
Inventor
小林达也
川城史义
富田悠志
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Publication of CN114256168A publication Critical patent/CN114256168A/zh
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Abstract

本发明的一个实施方式提供一种可靠性高的半导体装置。实施方式的半导体装置具有：半导体芯片，在第1面上具有第1电极；金属板；以及第1导电性接合片，位于半导体芯片的第1面与金属板之间，将第1电极与金属板接合。

Description

半导体装置
本申请享受以日本专利申请2020-159922号(申请日：2020年9月24日)为基础申请的优先权。本申请通过参照该基础申请而包含该基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
随着半导体模块的大电流化，要求增加对半导体芯片彼此进行连接的布线的允许电流量。
发明内容
本发明的一个实施方式提供一种可靠性较高的半导体装置。
根据本实施方式，提供一种半导体装置，具有：半导体芯片，在第1面具有第1电极；金属板；以及第1导电性接合片，位于半导体芯片的第1面与金属板之间，将第1电极与金属板接合。
附图说明
图1是实施方式的半导体装置的截面图。
图2是基于实施方式的导电性接合片的连接的说明图。
图3是基于实施方式的导电性接合片的连接的说明图。
图4是实施方式的半导体装置的制造方法的流程图。
图5～图10是实施方式的半导体装置的制造方法的工序图。
图11是实施方式的半导体装置的截面图。
图12是实施方式的半导体装置的截面图。
图13是实施方式的半导体装置的截面图。
具体实施方式
以下，参照附图对本公开的一个实施方式进行说明。另外，在本说明书所附加的附图中，为了便于容易进行图示和理解，适当地将比例尺以及纵横的尺寸比等相对于实物进行变更并夸张。
以下，使用附图对实施方式进行说明。另外，在附图中，对于相同或者类似的部位标注相同或者类似的符号。
在本说明中，有时对于相同或者类似的部件标注相同的符号，并省略重复的说明。
在本说明书中，为了表示构件等的位置关系，将附图的上方记载为“上”，将附图的下方记载为“下”。本说明书中，“上”、“下”的概念并不一定是表示与重力的朝向之间的关系的用语。
进而，关于在本说明书中使用的对形状、几何学条件以及它们的程度进行确定的例如“平行”、“正交、“相同”等用语、长度、角度的值等，不束缚于严格的含义，而使包含能够期待相同功能的程度的范围来解释。
(第1实施方式)
第1实施方式涉及一种半导体装置。第1实施方式更具体而言涉及一种功率半导体模块。图1表示实施方式的半导体装置100的截面图。图1的半导体装置100的截面图表示半导体装置100的主要部分。
图1的半导体装置100具有基板10、半导体芯片20、第1导电性接合片31、第2导电性接合片32、第1金属层41以及布线51、52。在图1中，在基板10上设置有两个半导体芯片20。
基板10具有绝缘性的支承体11以及金属膜12。基板10例如是印刷基板。支承体11例如是树脂、SiN、AlN、Al2O3等陶瓷。金属膜12是基板10的布线层。在支承体11的与金属膜12侧相反一侧也可以设置有金属膜。金属膜12含有从由Au、Ag、Cu、Ni、Pd以及Pt形成的组中选出的一种以上的金属。金属膜12的膜厚典型为100μm以上1000μm以下。金属膜12经由第2导电性接合片32而与半导体芯片20的第2电极23接合。
半导体芯片20具有半导体元件21、以及设置在半导体元件21的表面上的第1电极22及第2电极23。在图1中，在基板10上设置有两个半导体芯片20。在半导体装置100中，虽然未图示，但包括10个以上的半导体芯片20，这些半导体芯片20电连接。更具体而言，半导体元件21是IGBT(Insulated Gate Bipolar Transistor)、MOSFET、肖特基势垒二极管、PIN二极管等功率半导体元件。图1示出半导体芯片20的一部分电极。第1电极22A以及第1电极22B设置于半导体元件21的第1面。第2电极23设置于半导体元件21的与第1面相反侧的第2面。第1电极22例如是发射极、源极或者阳极。第2电极23例如是集电极、漏极或者阴极。第1电极22以及第2电极23优选除了Al以外，进一步含有从由Au、Ag、Cu、Ni、Pd以及Pt形成的组中选出的一种以上的金属。第1电极22以及第2电极23的表面优选通过Ni/Au、Ni/Ag、Ni/Cu、Ni/Pd等进行电镀。另外，可以采用倒装片构造，而上下的电极构成也可以颠倒。
第1导电性接合片31以及第2导电性接合片32是将部件彼此接合的导电性的片。第1导电性接合片31设置在半导体芯片20的电极22(22A、22B)与第1金属板41(41A、41B)之间。第2导电性接合片32设置在半导体芯片20的电极23与金属膜12之间。以下，有时将第1导电性接合片31以及第2导电性接合片32统称而简称为导电性接合片。
导电性接合片含有Ag粒子。在导电性接合片中也可以含有微量的树脂等有机物。导电性接合片例如含有从一次粒子径为10nm以上5μm以下的Ag粒子、一次粒子径为10nm以上5μm以下的Cu粒子、以及一次粒子径为10nm以上5μm以下的Ni粒子形成的组中选出的一种以上的金属粒子。通过对含有一次粒子径为1nm以上500nm以下的金属粒子的片状的导电性芯片贴装接合材料进行加压加热而烧结，由此得到导电性接合片。导电性片的厚度优选为10μm以上200μm以下，更优选为20μm以上50μm以下。在导电性接合片的内部有时包括外切圆直径为10nm以上2μm以下的空隙。片状的导电性芯片贴装接合材料含有Ag粒子、低沸点粘结剂以及热分解性的丙烯酸树脂、聚碳酸酯树脂等。导电性接合片有时残存有片状的导电性芯片贴装接合材料中含有的有机物及其分解物的一部分。
在实施方式中，不使用涂布或者印刷的导电膏，而是对片状的导电性芯片贴装接合材料进行加压加热而烧结来进行接合。当使用导电膏时，有时在涂布、印刷时产生偏移，并且在加压时溢出到半导体芯片20的侧面，并进一步爬升到半导体芯片2的侧面。涂布、印刷的偏移成为由于接合面积减少而导致的传导性以及可靠性降低的原因。此外，有可能由于偏移而从接合部件间的溢出变大。如果由于偏移而引起的溢出较少，则影响较少，但当由于偏移而引起的溢出较多时，有可能由于爬升而产生短路、绝缘耐压不良，或者溢出的部分剥离而产生短路。如果是基于导电性接合片的接合，则几乎不存在由于加压而引起的变形，因此这种由于溢出、爬升而引起的短路的可能性非常低。此外，由于是片状的材料，因此能够转印到电极面、与半导体芯片20接合的部件上，能够基于位置以及形状与电极面相匹配的导电性接合片来进行部件间的连接。
图2以及图3表示基于导电性接合片的连接的说明图。在图2以及图3中示出第1导电性片31，但对于第2导电性片32也相同。在图2中示出第1电极22与第1金属板41之间的第1导电性接合片31的位置以及大小。图3是第1电极22与第1金属板41之间的第1导电性接合片31的局部截面图，示出第1导电性接合片31的位置以及截面形状。图2的实线所示的矩形表示第1电极31以及第1金属板41的外周边。虚线所示的矩形表示第1导电性接合片31的外周边。第1导电性接合片31为，将片状的导电性芯片贴装接合材料转印到金属板41或者第1电极22上而在加压状态下加热，因此相对于电极22的位置以及形状的偏移稳定且较少。在使用了膏的情况下，由于膏的粘度较高，因此难以进行高精度的接合面积的调整。为了防止对导电膏进行烧结之后的溢出而以比接合面小的方式对膏进行涂布等，或者，为了可靠地在整面进行接合而比接合面大地进行涂布等，由此进行稳定的接合。当使用片状的导电性芯片贴装接合材料时，由于能够进行转印，因此能够减少位置偏移、大小的偏差。此外，片状的导电性芯片贴装接合材料即使加压、变形也较少，因此溢出难以爬升。如图3所示，溢出的部分难以以沿着半导体芯片20的侧面的方式爬升。从半导体芯片20朝第1金属板41方向将半导体芯片20的第1电极22的外周边与第1导电性接合片31的外周边重叠时的距离的最大值优选为0.1mm以下。此外，从半导体芯片20朝第1金属板41方向将半导体芯片20的第1电极22的外周边与第1导电性接合片31的外周边重叠时的距离的平均值优选为0.1mm以下。从半导体芯片20朝第1金属板41方向将半导体芯片20的第1电极21的外周边与第1导电性接合片31的外周边重叠时的距离，优选沿着第1电极22的外周边以1mm间隔进行测定。
此外，如图3所示，第1导电性接合片31的截面形状具有梯形的形状。在第1导电性接合片31未溢出的情况下，第1导电性接合片31的截面形状在整体上具有梯形的形状。即，第1导电性接合片31具有四棱锥台(如果半导体芯片20为四边形以外的多边形，则为多棱锥台)的形状，将第1金属板41侧设为底面，将半导体芯片20侧设为上表面。实施方式中的棱锥台的形状，不仅包括严格的形状，而且包括上表面与底面的大小不同的前端变细的形状。烧结后的第1导电性接合片31的形状成为梯形的形状，由此能够兼顾良好的接合以及降低由于爬升等而引起的短路的可能性。棱锥台形的第1导电性接合片31的上表面侧所对置的面与底面侧所对置的面，能够根据转印的条件而调换。当棱锥台形的第1导电性接合片31的上表面与底面之间的面积差较大时，非接合面的比例变高。因此，棱锥台形的第1导电性接合片31的上表面的面积优选为棱锥台形的第1导电性接合片31的底面的面积的90％以上99％以下，更优选为95％以上99％以下。上述面积也可以根据截面中的上表面的长度以及底面的长度来求出。
相对于第1电极22的外周边，第1导电性接合片31的外周边朝外侧伸出的部分为溢出的部分，向内侧进入的部分为非接合部分。当溢出的部分以及非接合部分相对于第1电极22的面积的比例较低时，接合部分的传导性较高而可靠性较高。因此，在从半导体芯片20朝第1金属板41方向将半导体芯片20的第1电极22的外周边与第1导电性接合片31的外周边重叠的情况下，第1导电性接合片31的外周边相对于第1电极22的外周边朝外侧伸出的部分的面积、与第1导电性接合片31的外周边相对于第1电极22的外周边朝内侧进入的部分的面积之和，优选为第1电极22的面积的5％以下，更优选为3％以下。
第2导电性接合片32也与第1导电性接合片31相同。因此，从半导体芯片20朝金属膜12方向将半导体芯片20的第2电极23的外周边与第2导电性接合片32的外周边重叠时的距离的最大值优选为0.1mm以下。此外，从半导体芯片20朝金属膜12方向将半导体芯片20的第2电极23的外周边与第2导电性接合片32的外周边重叠时的距离的平均值优选为0.1mm以下。此外，在从半导体芯片20朝金属膜12方向将半导体芯片20的第2电极23的外周边与第2导电性接合片32的外周边重叠的情况下，第2导电性接合片32的外周边相对于第2电极23的外周边朝外侧伸出的部分的面积、与第2导电性接合片32的外周边相对于第2电极23的外周边朝内侧进入的部分的面积之和，优选为第1电极22的面积的5％以下，更优选为3％以下。
第1金属板41A、41B经由第1导电性接合片31而与第1半导体芯片20的第1电极22A、22B连接。第1金属板41A与第1金属板41B间通过布线52连接。第1金属板41A、41B经由布线51而与基板10的金属膜12电连接。
第1金属板41例如优选为Cu、Mo或者W的板。此外，也可以对这些板实施镀镍金等。第1金属板41的厚度典型为30μm以上1mm以下。能够考虑电流容量、散热性等来适当选择。
布线51、52将半导体芯片20之间、或者半导体芯片20与金属膜12之间电连接。布线51例如使用Al、Al/Cu等铝包覆材。布线51、52优选为接合线、带、金属柱等导电体。在图1中示出假定为接合线或者带的布线51、52。
图4表示第1实施方式的半导体装置100的制造方法的流程图。在流程图中示出半导体装置100的制造方法的一部分工序。举出两个对片状的导电性芯片贴装接合材料进行加压烧结而通过导电性接合片进行接合的方法。图4左侧的流程涉及半导体芯片20与第1金属板41的接合。图4右侧的流程涉及半导体芯片20与基板10的金属膜12的接合。在图4中示出进行加压烧结的流程，但根据片状的导电性芯片贴装接合材料的种类不同，也可以不进行加压而在大气压下进行烧结。
第一个流程具有向第1金属板41转印片状的导电性芯片贴装接合材料的工序(S01)、在半导体芯片20上贴合转印了片状的导电性芯片贴装接合材料的第1金属板41的工序(S02)、以及对第1金属板41与半导体芯片20间施加压力而进行烧结的工序(S11)。通过施加压力而进行烧结，由此利用片状的导电性芯片贴装接合材料中的金属粒子将第1金属板41与半导体芯片20的第1电极21之间进行接合。
第二个流程具有向半导体芯片20转印片状的导电性芯片贴装接合材料的工序(S03)、在金属膜12上贴合转印了片状导电性芯片贴装接合材料的基板10的金属膜12的工序(S04)、以及对半导体芯片20与基板10之间施加压力而进行烧结的工序(S11)。通过施加压力而进行烧结，由此利用片状的导电性芯片贴装接合材料中的金属粒子将基板10的金属膜12与半导体芯片20的第2电极22之间进行接合。
以下，示出图5至图10的半导体装置100的制造方法的工序图而对半导体装置100的制造方法进行说明。在图5的工序图中示出向第1金属板41上转印片状的导电性芯片贴装接合材料33的处理。在贴合了具有比第1金属板41大的面积的片状的导电性芯片贴装接合材料33之后，通过加热和压力而以与第1金属板41的形状相匹配的方式转印片状的导电性芯片贴装接合材料33。为了控制片状的导电性芯片贴装接合材料33向第1金属板41的转印面积，也可以在片状的导电性芯片贴装接合材料33上形成掩模材而进行转印。之后，为了贴合于半导体芯片20的第1面的两个第1电极22A、22B上，相对于一个半导体芯片20准备两个在第1金属板41A、41B上转印了片状的导电性芯片贴装接合材料33A、33B的部件。在粘贴第1金属板41的半导体芯片20的第1电极22为一个的情况下，对于每一个半导体芯片20准备1个上述部件。此时，根据需要，使用形成有栅极布线用的开口部的第1金属板41。
在图6的工序图中，将在第1金属板41A、41B上转印了片状的导电性芯片贴装接合材料33A、33B的部件，贴合于半导体芯片20的第1面的第1电极22A、22B上并进行临时固定。
在图7的工序图中，对图6所示的部件进行烧结，将第1金属板41A、41B与半导体芯片20进行接合。通过烧结，片状的导电性芯片贴装接合材料33A、33B为，虽然第1导电性接合片31A、31B的金属粒子处于烧结不完全的状态，但通过与接合相关的烧结而金属粒子的凝聚发展而成为将第1金属板41A、41B与半导体芯片20的第1电极22A、22B进行接合的导电性接合片。然后，得到第1金属板41A、41B与半导体芯片20的第1电极22A、22B通过第1导电性接合片31A、31B接合了的部件。在将第1金属板41A、41B与半导体芯片20进行接合的烧结中为了提高接合强度，优选进行适当的加压。
在图8的工序图中，在第1金属板41A、41B与半导体芯片20的第1电极22A、22B通过第1导电性接合片31A、31B接合了的部件中，向设置于半导体芯片20的与第1面相反侧的第2面上的第2电极23转印片状的导电性芯片贴装接合材料34。优选与第2电极23的形状相匹配地进行转印。图8所示的工序图示出转印了片状的导电性芯片贴装接合材料34的部件。优选贴合比半导体芯片20的第2面大的片状的导电性芯片贴装接合材料34，并通过加热和压力来进行转印。
在图9的工序图中，将转印了片状的导电性芯片贴装接合材料34的半导体芯片20粘贴于基板10的金属膜12的面上。在粘贴后，对片状的导电性芯片贴装接合材料34进行烧结，而得到半导体芯片20与基板10的金属膜12通过第2导电性接合片32接合了的图10的工序图所示的部件。在图10的部件上形成布线51、52而得到半导体装置100。
将半导体芯片20的两个面通过导电性接合片进行接合，由此能够形成可靠性较高且电流容量较大的布线。
(第2实施方式)
第2实施方式涉及一种半导体装置。图11表示第2实施方式的半导体装置101的截面图。图11所示的半导体装置101与第1实施方式的半导体装置100的不同点在于，代替第1金属板41而使用第2金属板42。在第1实施方式和第2实施方式中，对于共同的内容省略其说明。
在半导体装置101中，两个半导体芯片20通过一个第2金属板42连接。虽然未图示，但在第2金属板42上设置有栅极布线用的开口部，未图示的布线与栅极连接。
在制造第2实施方式的半导体装置101的情况下，能够向半导体芯片20的第1电极22A转印片状的导电性芯片贴装接合材料，而与第2金属板42接合。此外，也可以将片状的导电性芯片贴装接合材料转印到第2金属板42，而与半导体芯片20的第1电极22A接合。在第2实施方式中，能够将两个以上的半导体芯片20同时粘贴于第2金属板42而进行接合。因而，即使芯片数量增多，也能够通过较少的工序数来制造半导体装置101。
(第3实施方式)
第3实施方式涉及一种半导体装置。图12表示第3实施方式的半导体装置102的截面图。图12所示的半导体装置102与第2实施方式的半导体装置101的不同点在于，将金属柱53用作为布线而将基板10的金属面12与第2金属板42连接，以及在第2金属板42上设置凸部并将凸部经由第1导电性片31而与半导体芯片20连接。在第1实施方式、第2实施方式以及第3实施方式中，对于共同的内容省略其说明。
能够在第2金属部42上设置凸部，例如，具有容易进行定位这样的优点。此外，能够在第1导电性接合片31的侧面、第2金属部42的与半导体芯片20对置的面上设置绝缘性树脂61。在将半导体芯片20与第2金属板42之后形成绝缘性树脂61，由此能够强化第1导电性片31周围的绝缘性以及耐湿性。
此外，在第3实施方式中，能够在第2金属部42与金属膜12之间设置金属柱53等布线而将第2金属部42与金属膜12之间进行连接。通过使用金属柱53，能够增加布线的电流容量。金属柱53与第2金属部42之间也优选通过导电性接合片进行接合。此外，金属柱53与金属膜12之间也优选通过导电性接合片进行接合。
(第4实施方式)
第4实施方式涉及一种半导体装置。图13表示第4实施方式的半导体装置103的截面图。图13所示的半导体装置102与第2实施方式的半导体装置101的不同点在于，不使用布线而使第2金属板42弯曲来将基板10的金属面12与第2金属板42进行连接，以及在第2金属板42上设置凹部并在凹部中经由第1导电性片31而与半导体芯片20连接。在第1实施方式至第3实施方式以及第4实施方式中，对于共同的内容省略其说明。
能够在第2金属部42上设置凹部，例如，具有容易进行定位这样的优点。当考虑半导体芯片20的粘贴容易度等时，凹部的深度优选比第1导电性片31的厚度深。此外，虽然未图示，但也优选在第1导电性接合片31的侧面、第2金属部42的与半导体芯片20对置的面上设置绝缘性树脂。
此外，在第4实施方式中，第2金属板42不经由布线地与金属膜12连接。第2金属板42与金属膜12可以使用导电性接合片来接合，也可以通过超声波接合等来直接接合。通过进行超声波接合，接合的可靠性提高，半导体装置103的可靠性提高。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子而提示的，并不意图对发明的范围进行限定。这些新的实施方式能够以其他各种方式加以实施，在不脱离发明的主旨的范围内能够进行各种省略、置换、变更。这些实施方式及其变形包含于发明的范围及主旨中，并且包含于专利请求范围所记载的发明和与其等同的范围中。

Claims (7)

1.一种半导体装置，具有：
半导体芯片，在第1面上具有第1电极；
金属板；以及
第1导电性接合片，位于上述半导体芯片的第1面与上述金属板之间，将上述第1电极与上述金属板接合。
2.根据权利要求1所述的半导体装置，其中，
上述第1导电性接合片含有从由一次粒子径为10nm以上5μm以下的Ag粒子、一次粒子径为10nm以上5μm以下的Cu粒子、以及一次粒子径为10nm以上5μm以下的Ni粒子形成的组中选出的一种以上的金属粒子。
3.根据权利要求1或2所述的半导体装置，其中，
从上述半导体芯片朝上述金属板方向将上述第1电极的外周边与上述第1导电性接合片的外周边重叠时的距离的最大值为0.1mm以下。
4.根据权利要求1或2所述的半导体装置，其中，
从上述半导体芯片朝上述金属板方向将上述第1电极的外周边与上述第1导电性接合片的外周边重叠时的距离的平均值为0.1mm以下。
5.根据权利要求1或2所述的半导体装置，其中，
在从上述半导体芯片朝上述金属板方向将上述第1电极的外周边与上述第1导电性接合片的外周边重叠的情况下，上述第1导电性接合片的外周边相对于上述第1电极的外周边朝外侧伸出的部分的面积与上述第1导电性接合片的外周边相对于上述第1电极的外周边朝内侧进入的部分的面积之和，为上述第1电极的面积的5％以下。
6.根据权利要求1或2所述的半导体装置，还具有：
基板，具有金属膜；以及
第2导电性接合片，
在上述半导体芯片的与第1面相反侧的第2面上具有第2电极，
上述第2电极与上述金属膜通过第2导电性接合片接合。
7.根据权利要求1或2所述的半导体装置，其中，
上述半导体装置包括多个上述半导体芯片，
上述多个半导体芯片经由上述第1导电性接合片而与上述金属板接合。
CN202110835836.3A 2020-09-24 2021-07-23 半导体装置 Pending CN114256168A (zh)

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