CN113937156A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN113937156A
CN113937156A CN202111181712.4A CN202111181712A CN113937156A CN 113937156 A CN113937156 A CN 113937156A CN 202111181712 A CN202111181712 A CN 202111181712A CN 113937156 A CN113937156 A CN 113937156A
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region
substrate
ions
top surface
area
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CN113937156B (en
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潘嘉
杨继业
邢军军
陈冲
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

A semiconductor structure and a method of forming the same, wherein the structure comprises: a substrate doped with first ions; the deep groove structures are positioned in the substrate and are mutually independent, each deep groove structure comprises a first area, a second area and a doping blocking area between the first area and the second area, second ions are doped in the first area and the second area, the conductivity types of the second ions and the first ions are opposite, third ions are doped in the doping blocking area, and the conductivity types of the third ions and the first ions are the same; a body region located in the substrate between adjacent deep trench structures; a gate structure located within the body region and the substrate; a source region located in the body region between the gate structure and the deep trench structure, the source region being higher than the barrier doping region; and the collector region is positioned at the bottom of the substrate, the surface of the collector region is exposed from the bottom surface of the substrate, and the collector region and the bottom of the deep groove structure are separated by the substrate. To provide an insulated gate bipolar transistor which is compatible with better withstand voltage performance, lower on-state voltage drop and less turn-off loss.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
In a switching power supply device with medium and high power, an Insulated Gate Bipolar transistor (IGBT for short) has the advantages of high input impedance, simple and rapid driving, and also has the advantages of low on-state voltage drop and large capacity, so that the IGBT is more and more widely applied to modern power electronic technology.
Fig. 1 is a schematic structural diagram of an insulated gate bipolar transistor in the prior art. As shown in fig. 1, the prior art insulated gate bipolar transistor includes: the semiconductor device comprises a silicon substrate 10, wherein N-ions are doped in the silicon substrate 10, and the silicon substrate 10 is a drift region; a P + doped region 11 located at the bottom of the silicon substrate 10, wherein the P + doped region 11 is a collector region; a P-well region 12 located within the silicon substrate 10; an N + source region 13 located on the upper portion of the P-well region 12, the drift region and the N + source region 13 being separated by the P-well region 12; the gate 14 is positioned at two sides of the P-well region 12, the gate 14 is in contact with the side wall surfaces of the P-well region 12 and the N + source region 13, and by inputting an opening signal to the gate 12, a channel for connecting the drift region and the emitter region is formed in the region of the P-well region 12 close to the gate 12; a P + connection layer 15 penetrating through the N + source region 13 and extending into the P well region 12, the P + connection layer 15 being used for leading out the P well region 12; and an emitter conductive layer 16 located on the surface of the N + source region 13 and the surface of the P + connection layer 15.
However, with the development of integrated circuits, higher requirements are placed on the performance of the existing insulated gate bipolar transistor. Therefore, there is a need for an insulated gate bipolar transistor that combines better voltage endurance, lower on-state voltage drop, and less turn-off loss (EOFF) to improve the performance of the prior art insulated gate bipolar transistor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of an insulated gate bipolar transistor.
To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a substrate doped with first ions, the substrate having opposing top and bottom surfaces; the deep groove structures are positioned in the substrate and are mutually independent, each deep groove structure comprises a first area, a second area and a doping blocking area between the first area and the second area, the first area and the second area are arranged in a direction vertical to the top surface of the substrate, the surface of the first area is exposed on the top surface of the substrate, second ions are doped in the first area and the second area, the conductivity types of the second ions are opposite to that of the first ions, third ions are doped in the doping blocking areas, and the conductivity types of the third ions are the same as that of the first ions; the body region is positioned in the substrate between the adjacent deep groove structures and is higher than the contact surface of the barrier doping region and the second region; the grid structure is positioned in the body region and the substrate, and the top surface of the substrate is exposed out of the top surface of the grid structure; a source region located in the body region between the gate structure and the deep trench structure, the source region being higher than the barrier doping region; and the collector region is positioned at the bottom of the substrate, the surface of the collector region is exposed from the surface of the bottom of the substrate, and the collector region and the bottom of the deep groove structure are separated by the substrate.
Optionally, a minimum distance between the barrier doping region and the surface of the first region exposed by the top surface of the substrate is above 1 micron.
Optionally, the height of the blocking doping region in a direction perpendicular to the top surface of the substrate ranges from 1 micrometer to 10 micrometers.
Optionally, in a direction perpendicular to the top surface of the substrate, a minimum distance between a contact surface of the barrier doping region and the second region and the body region is greater than 0 micron and less than or equal to 3 microns.
Optionally, the doping concentration of the third ions is higher than the doping concentration of the first ions.
Optionally, the doping concentration of the doped third ions in the barrier doping region ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
Optionally, the first ion and the third ion are N-type ions, and the second ion is a P-type ion.
Optionally, fourth ions are doped in the collector region, the fourth ions are P-type ions, and the doping concentration of the fourth ions is greater than that of the second ions.
Optionally, the body region is doped with P-type ions, and the source region is doped with N-type ions.
Optionally, the gate structure includes: the gate dielectric layer is positioned between the gate electrode and the substrate, and between the gate electrode and the body region and the source region.
Optionally, the top surface of the substrate exposes surfaces of the body region and the source region, and the semiconductor structure further includes: the interlayer dielectric layer is positioned on the top surface of the substrate, the top surface of the grid structure, the exposed surfaces of the body region and the source region and the exposed surface of the first region on the top surface of the substrate; the first conductive structure is positioned in the interlayer dielectric layer and is connected with the grid structure; and the second conductive structure is positioned in the interlayer dielectric layer and is connected with the body region and the source region.
Optionally, the method further includes: and the third conductive structure is connected with the collector region.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate doped with first ions, the substrate having opposing top and bottom surfaces; forming a plurality of mutually independent deep groove structures in the substrate, wherein the deep groove structures comprise a first region, a second region and a doping blocking region between the first region and the second region, the first region and the second region are arranged in a direction vertical to the top surface of the substrate, the surface of the first region is exposed on the top surface of the substrate, second ions are doped in the first region and the second region, the conductivity types of the second ions are opposite to that of the first ions, third ions are doped in the doping blocking region, and the conductivity types of the third ions are the same as that of the first ions; after the deep groove structures are formed, forming a body region, a source region and a grid structure in the substrate between the adjacent deep groove structures, wherein the body region is higher than the contact surface of the barrier doping region and the second region, the grid structure is positioned in the body region and the substrate, the top surface of the substrate is exposed out of the top surface of the grid structure, the source region is positioned in the body region between the grid structure and the deep groove structures, and the source region is higher than the barrier doping region; after the body region, the source region and the gate structure are formed, a collector region is formed at the bottom of the substrate, the surface of the collector region is exposed from the surface of the bottom of the substrate, and the collector region and the bottom of the deep groove structure are spaced by the substrate.
Optionally, the method for forming a plurality of mutually independent deep trench structures in the substrate includes: forming a plurality of initial deep groove structures which are independent from each other and are doped with second ions in the substrate, wherein the initial deep groove structures comprise a first area, a second area and an initial blocking doping area between the first area and the second area, and the first area and the second area are arranged along the direction vertical to the top surface of the substrate; and performing ion implantation on the initial barrier doping region from the surface of the first region by adopting a high-energy ion implantation process to form the deep groove structure and the barrier doping region, wherein the implantation energy of the high-energy ion implantation process is more than the preset first implantation energy.
Optionally, the method for forming a plurality of initial deep trench structures includes: forming a deep trench mask layer on the top surface of the substrate, wherein the deep trench mask layer exposes part of the top surface of the substrate; etching the substrate by taking the deep groove mask layer as a mask, and forming a plurality of mutually independent deep grooves in the substrate; and forming the initial deep groove structure in the deep groove.
Optionally, the method of performing ion implantation from the surface of the first region to the initial barrier doping region by using a high-energy ion implantation process further includes: and after the initial deep groove structure is formed, performing ion implantation from the surface of the first region to the initial barrier doping region by taking the deep groove mask layer as a mask.
Optionally, the preset first implantation energy is 2000 KeV.
Optionally, the implantation energy of the high-energy ion implantation process is below 4000 KeV.
Optionally, the process parameters of the high-energy ion implantation process further include: the implant dose is 1E11 atoms per square centimeter to 1E14 atoms per square centimeter.
Optionally, the top surface of the substrate exposes surfaces of the body region and the source region, and the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on the top surface of the substrate, the top surface of the gate structure, the exposed surfaces of the body region and the source region and the exposed surface of the first region on the top surface of the substrate after forming the body region, the source region and the gate structure and before forming the collector region; forming a first conductive structure in the interlayer dielectric layer, wherein the first conductive structure is connected with the grid structure; and forming a second conductive structure in the interlayer dielectric layer, wherein the second conductive structure is connected with the body region and the source region.
Optionally, the method further includes: and after the collector region is formed, forming a third conductive structure on the surface of the collector region.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the semiconductor structure provided by the technical scheme of the invention, the deep groove structure is positioned in the substrate, and the conductivity type of the second ions doped in the first region and the second region is opposite to that of the first ions doped in the substrate, so the first region and the second region of the deep groove structure and the substrate part adjacent to the first region and the second region of the deep groove structure form a super junction structure. The super junction structure can not only improve the voltage endurance capability of the device, but also increase the minority carrier concentration in the drift region (substrate) under the condition of maintaining the voltage endurance capability. On the basis, the blocking doping region is doped with third ions with the same conductivity type as the first ions (namely, the conductivity type of the third ions is opposite to that of the second ions), and the body region is higher than the contact surface of the blocking doping region and the second region, so that the physical isolation between the body region and the second region is realized by the blocking doping region, and minority carriers injected from the collector region and entering the body region through the deep groove structure are blocked at a certain distance from the body region through the blocking doping region, so that the minority carriers entering the body region are reduced. Therefore, minority carriers injected from the collector region are better gathered in the drift region (substrate) part below the body region and the gate structure, and the minority carrier concentration of the whole drift region is improved. Therefore, the on-resistance of the drift region can be reduced, the on-state voltage drop of the insulated gate bipolar transistor can be reduced, and meanwhile, the turn-off loss of the insulated gate bipolar transistor can be improved. In conclusion, the performance of the insulated gate bipolar transistor is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art IGBT configuration;
fig. 2 to 7 are schematic cross-sectional views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, with the development of integrated circuits, higher requirements are placed on the performance of the existing insulated gate bipolar transistors. Therefore, there is a need for an insulated gate bipolar transistor that combines better voltage endurance, lower on-state voltage drop, and less turn-off loss.
In order to solve the above technical problems, an aspect of the present invention provides a semiconductor structure and a method for forming the same, in which the semiconductor structure comprises: a substrate doped with first ions, the substrate having opposing top and bottom surfaces; the deep groove structures are positioned in the substrate and are mutually independent, each deep groove structure comprises a first area, a second area and a doping blocking area between the first area and the second area, the first area and the second area are arranged in a direction vertical to the top surface of the substrate, the surface of the first area is exposed on the top surface of the substrate, second ions are doped in the first area and the second area, the conductivity types of the second ions are opposite to that of the first ions, third ions are doped in the doping blocking areas, and the conductivity types of the third ions are the same as that of the first ions; the body region is positioned in the substrate between the adjacent deep groove structures and is higher than the contact surface of the barrier doping region and the second region; the grid structure is positioned in the body region and the substrate, and the top surface of the substrate is exposed out of the top surface of the grid structure; a source region located in the body region between the gate structure and the deep trench structure, the source region being higher than the barrier doping region; and the collector region is positioned at the bottom of the substrate, the surface of the collector region is exposed from the surface of the bottom of the substrate, and the collector region and the bottom of the deep groove structure are separated by the substrate. Therefore, an insulated gate bipolar transistor is provided which combines better withstand voltage performance, lower on-state voltage drop, and less turn-off loss.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 7 are schematic cross-sectional views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 2, a substrate 100 doped with first ions is provided, the substrate 100 having a top surface 101 and a bottom surface 102 opposite to each other.
In the present embodiment, the material of the substrate 100 includes a semiconductor material. Specifically, the material of the substrate 100 includes silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In this embodiment, the first ions are N-type ions. Namely: the substrate 100 is an N-type substrate.
Specifically, the N-type ions include phosphorus ions or arsenic ions.
In another embodiment, the first ions may also be P-type ions to form a device structure with a conductivity type completely opposite to that of the present embodiment.
Next, forming a plurality of mutually independent deep trench structures in the substrate 100, where the deep trench structures include a first region, a second region and a doping blocking region between the first region and the second region, the first region and the second region are arranged in a direction perpendicular to the top surface 101 of the substrate 100, the top surface 101 of the substrate 100 is exposed out of the surface of the first region, the first region and the second region are doped with second ions, the second ions and the first ions have opposite conductivity types, the doping blocking region is doped with third ions, and the third ions and the first ions have the same conductivity type. Please refer to fig. 3 to 4 for steps of forming the deep trench structure.
Referring to fig. 3, a plurality of initial deep trench structures 110 are formed in the substrate 100 independently.
The material of the initial deep trench structure 110 includes a semiconductor material.
In the present embodiment, the material of the initial deep trench structure 110 includes silicon.
The initial deep trench structure 110 is doped with second ions having opposite conductivity types to the first ions.
In this embodiment, the second ions are P-type ions.
Specifically, the P-type ions include boron ions or indium ions.
The initial deep trench structure 110 includes: a first region I, a second region II arranged in a direction perpendicular to the top surface 101 of the substrate 100, and an initial barrier doping region a between the first region I and the second region II.
The initial barrier doping region A is used for forming a barrier doping region in a subsequent process.
In this embodiment, the method for forming a plurality of initial deep trench structures 110 includes: forming a deep trench mask layer 120 on the top surface 101 of the substrate 100, wherein the deep trench mask layer 120 exposes a part of the top surface 101 of the substrate 100; etching the substrate 100 by using the deep trench mask layer 120 as a mask, and forming a plurality of mutually independent deep trenches (not shown) in the substrate 100; the initial deep trench structure 120 is formed within the deep trench.
In this embodiment, the material of the deep trench mask layer 120 includes photoresist.
In this embodiment, the process of etching the substrate 100 by using the deep trench mask layer 120 as a mask includes at least one of a dry etching process and a wet etching process.
In the present embodiment, the process of forming the initial deep trench structure 120 in the deep trench includes an epitaxial growth process.
Referring to fig. 4, ion implantation is performed from the surface of the first region I to the initial barrier doping region a to form a deep trench structure 130 and a barrier doping region B.
Specifically, the deep trench structure 130 includes: the substrate comprises a first area I, a second area II and a blocking doping area B between the first area I and the second area II, wherein the first area I and the second area II are arranged along a direction vertical to the top surface 101 of the substrate 100, and the top surface 101 of the substrate 100 is exposed out of the surface of the first area I.
The first region I and the second region II are doped with second ions, the barrier doped region B is doped with third ions, and the conductivity types of the third ions and the first ions are the same.
Since the deep trench structure 130 is located in the substrate 100, and the conductivity type of the second ions doped in the first region I and the second region II is opposite to that of the first ions doped in the substrate 100, the first region I and the second region II of the deep trench structure 130, and the portion of the substrate 100 adjacent to the first region I and the second region II of the deep trench structure 130 constitute a Super Junction structure (Super Junction). The super junction structure can not only improve the withstand voltage capability of an insulated gate bipolar transistor (hereinafter referred to as an IGBT device), but also increase the minority carrier concentration in the drift region (substrate 100) with the withstand voltage capability maintained.
Specifically, for the N-type substrate 100, the hole concentration of the drift region during turn-on is increased.
On this basis, since the barrier doping region B is doped with third ions having the same conductivity type as the first ions (i.e., the opposite conductivity type to the second ions), and the subsequently formed body region is higher than the contact surface 131 (shown in fig. 4) of the barrier doping region B and the second region I, the barrier doping region B achieves physical isolation between the body region and the second region II. The minority carriers (holes) injected from the collector region into the body region through the deep trench structure 130 are blocked by the blocking doping region B at a distance from the body region, thereby reducing the minority carriers (holes) entering the body region. Furthermore, minority carriers (holes) injected by the collector region are better gathered in the body region and a drift region (the substrate 100) part below a gate structure formed later, and the concentration of the minority carriers (holes) in the whole drift region is improved. Therefore, the on-resistance of the drift region can be reduced, the on-state voltage drop of the IGBT device can be reduced, and meanwhile the turn-off loss of the IGBT device can be improved. In conclusion, the performance of the IGBT device is improved.
In this embodiment, the third ions are N-type ions.
In this embodiment, the method for performing ion implantation from the surface of the first region I to the initial block doping region a includes: after the initial deep trench structure 130 is formed, ion implantation is performed from the surface of the first region I to the initial block doping region a by using the deep trench mask layer 120 as a mask and using a high-energy ion implantation process.
Compared with the method of forming the blocking doping region and the region (the first region I) above the blocking doping region by an epitaxial growth process, the process difficulty of the high-energy ion implantation process is lower, and therefore, by adopting the high-energy ion implantation process, the blocking doping region B having a certain minimum distance from the top surface (the surface of the first region I) of the initial deep trench structure 110 can be simply and efficiently formed in the initial deep trench structure 110. To achieve formation of the deep trench structure 130.
In this embodiment, the implantation energy of the high-energy ion implantation process is greater than or equal to a predetermined first implantation energy, so as to implant ions into the initial barrier doping region a.
Specifically, the preset first implantation energy is 2000 KeV. Namely, the implantation energy of the high-energy ion implantation process is above 2000 KeV.
The implantation energy of the high-energy ion implantation is too low to form a blocking doped region B at a preset initial blocking region A, namely: the minimum distance between the formed barrier doping region B and the top surface of the deep trench structure 130 is too small. Therefore, on one hand, a subsequently formed body region is easily lower than a contact surface between the blocking doped region B and the second region II, so that the blocking doped region B cannot achieve good blocking of minority carriers (holes). On the other hand, the source region formed subsequently is easily contacted with the blocking doping region B, which causes a short circuit between the source region and the substrate 100 and cannot perform switching control through the subsequently formed gate structure, thereby causing the reliability of the IGBT device to be deteriorated. Therefore, by making the injection energy of the high-energy ion injection process more than 2000KeV, the blocking doping region B can achieve better blocking of minority carriers (holes), and the reliability of the IGBT device is also considered.
In the present embodiment, the minimum distance H1 between the blocking doping region B and the exposed surface of the first region I of the top surface 101 of the substrate 100 is greater than 1 micron. And, the height range H2 (shown in fig. 4) of the blocking doping region B is 1 to 10 micrometers in a direction perpendicular to the top surface 101 of the substrate 100.
Accordingly, in a direction perpendicular to the top surface 101 of the substrate 100, a minimum distance H3 (shown in fig. 5) between the body region and the contact surface 131 of the barrier doping region B and the second region II is greater than 0 micrometer and less than or equal to 3 micrometers.
In this embodiment, the implantation energy of the high-energy ion implantation process is under 4000 KeV.
If the energy of the high-energy ion implantation is too high, the process difficulty of the high-energy ion implantation may be increased. Therefore, the implantation energy range of the high-energy ion implantation process is set to be lower than 4000KeV, so that the process difficulty of high-energy ion implantation can be reduced.
In summary, when the implantation energy of the high-energy ion implantation process is 2000KeV to 4000KeV, on one hand, the blocking doping region B can achieve better blocking of minority carriers (holes) and the reliability of the IGBT device is considered, and on the other hand, the process difficulty of the high-energy ion implantation is favorably reduced.
In this embodiment, the doping concentration of the third ions is higher than the doping concentration of the first ions.
The doping concentration of the third ions is higher than that of the first ions, so that the blocking capability of the blocking doping region B for holes injected from the collector region to enter the body region is further improved.
Preferably, the doping concentration of the third ions doped in the barrier doping region B ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
In this embodiment, the process parameters of the high-energy ion implantation process further include: the implant dose is 1E11 atoms per square centimeter to 1E14 atoms per square centimeter.
The barrier doping region B in the above doping concentration range can be formed by making the implantation dose of the high-energy ion implantation process be 1E11 atoms per square centimeter to 1E14 atoms per square centimeter.
In the present embodiment, after the formation of the deep trench structure 130, the deep trench mask layer 120 is removed. The process of removing the deep trench mask layer 120 includes an ashing process, and the like.
Referring to fig. 5, after the deep trench structures 130 are formed, body regions 140, source regions 150, and gate structures 160 are formed in the substrate 100 between adjacent deep trench structures 130.
In the present embodiment, the body region 140 is higher than the contact surface 131 of the barrier doping region B and the second region II. The gate structure 160 is located in the body region 140 and the substrate 100, and the top surface 101 of the substrate 100 exposes the top surface of the gate structure 160. The source region 150 is located in the body region 140 between the gate structure 160 and the deep trench structure 130, and the source region 150 is higher than the blocking doping region B.
In the present embodiment, the body region 140 is doped with P-type ions.
In the present embodiment, the source region 150 is heavily doped with N-type ions.
In this embodiment, the gate structure 160 includes: a gate electrode and a gate dielectric layer, the gate dielectric layer being located between the gate electrode and the substrate 100, and between the gate electrode and the body region 140 and the source region 150.
Specifically, the top surface 101 of the substrate 100 exposes the surfaces of the body region 140 and the source region 150.
In the present embodiment, the method of forming the gate structure 160 includes: forming a first mask layer (not shown) on the surface of the substrate 100, wherein the first mask layer exposes a part of the surface of the substrate 100 between the adjacent deep trench structures 130; etching the substrate 100 by using the first mask layer as a mask, and forming a gate opening (not shown) in the substrate 100; forming a gate dielectric layer (not shown) on the inner wall surface of the gate opening; after forming the gate dielectric layer, a gate electrode is formed in the gate opening to form the gate structure 160.
In the present embodiment, the method of forming the body region 140 and the source region 150 includes: performing ion implantation on the substrate 100 between the gate structure 160 and the deep trench structure 130 to form the body region 140, wherein the depth of the body region 140 is smaller than the height of the gate structure 160 in a direction perpendicular to the top surface 101 of the substrate 100; the ion implantation is performed on the portion of the body region 140 between the gate structure 160 and the deep trench structure 130, so as to form the source region 150 in the body region 140.
In other embodiments, the body region and the source region may also be formed prior to the gate structure.
Referring to fig. 6, an interlayer dielectric layer 170 is formed on the top surface 101 of the substrate 100, the top surface of the gate structure 160, the exposed surfaces of the body region 140 and the source region 150, and the exposed surface of the first region I of the top surface 101 of the substrate 100.
The material of the interlayer dielectric layer 170 includes a dielectric material.
In the present embodiment, the process of forming the interlayer dielectric layer 170 includes a chemical vapor deposition process and the like.
With continued reference to fig. 6, a first conductive structure (not shown) is formed in the interlayer dielectric layer 170, and the first conductive structure is connected to the gate structure 160; a second conductive structure 180 is formed in the interlayer dielectric layer 170, and the second conductive structure 180 connects the body region 140 and the source region 150.
The first conductive structure is used to extract the gate structure 160 (the gate of the IGBT device).
The second conductive structure is used to extract the body region 140 and the source region 150 (emitter of the IGBT device).
In this embodiment, the method for forming the first conductive structure and the second conductive structure 180 in the interlayer dielectric layer 170 includes: forming a second mask layer (not shown) on the surface of the interlayer dielectric layer 170, wherein the second mask layer exposes a part of the surface of the interlayer dielectric layer 170; etching the interlayer dielectric layer 170 by using the second mask layer as a mask until a first opening (not shown) and a second opening (not shown) are formed, wherein the first opening exposes a part of the top surface of the gate structure 160, and the second opening exposes parts of the top surfaces of the source region 150 and the body region 140; conductive material is filled in the first and second openings to form the first and second conductive structures 180.
In other embodiments, the first epitaxial layer may also be patterned according to different mask layers to form a first opening and a second opening, respectively.
Next, referring to fig. 7, a collector region 190 is formed at the bottom of the substrate 100, the bottom surface 102 of the substrate 100 exposes the surface of the collector region 190, and the collector region 190 and the bottom of the deep trench structure 130 are spaced apart from each other by the substrate 100.
In this embodiment, the collector region is doped with fourth ions.
Specifically, the fourth ions are P-type ions, and the doping concentration of the fourth ions is greater than that of the second ions.
In this embodiment, before forming the collector region 190, the substrate 100 is thinned from the bottom surface 102 of the substrate 100 by using a back-of-wafer thinning process.
In this embodiment, the method for forming the collector region 190 includes: after thinning the substrate 100, an ion implantation process is performed on the bottom surface 102 of the substrate 100 to form a collector region 190 at the bottom of the substrate 100.
In this embodiment, after the collector region 190 is formed, a bottom interlayer dielectric layer (not shown) is formed on the bottom surface 102 of the substrate 100 and the exposed surface of the collector region 190; a third conductive structure (not shown) is formed in the bottom interlayer dielectric layer, and the third conductive structure is connected with the collector region 190 to lead out the collector region 190 (collector of the IGBT device).
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, with reference to fig. 7, including: a substrate 100 doped with first ions, the substrate 100 having opposing top 101 and bottom 102 surfaces; the deep trench structures 130 are located in the substrate 100 and are independent of each other, the deep trench structures 130 include a first region I, a second region II and a blocking doped region B between the first region I and the second region II, the first region I and the second region II are arranged in a direction perpendicular to the top surface 101 of the substrate 100, the top surface 101 of the substrate 100 is exposed out of the surface of the first region I, second ions are doped in the first region I and the second region II, the second ions and the first ions have opposite conductivity types, the blocking doped region B is doped with third ions, and the third ions and the first ions have the same conductivity type; the body region 140 is positioned in the substrate 100 between the adjacent deep trench structures 130, and the body region 140 is higher than the contact surface 131 of the barrier doping region B and the second region II; a gate structure 160 located in the body region 140 and the substrate 100, the top surface 101 of the substrate 100 exposing a top surface of the gate structure 160; a source region 150 located in the body region 140 between the gate structure 160 and the deep trench structure 130, the source region 150 being higher than the blocking doping region B; and the collector region 190 is located at the bottom of the substrate 100, the bottom surface 102 of the substrate 100 exposes the surface of the collector region 190, and the collector region 190 is spaced from the bottom of the deep trench structure 130 by the substrate 100.
Since the deep trench structure 130 is located within the substrate 100 and the conductivity type of the second ions doped in the first region I and the second region II is opposite to the conductivity type of the first ions doped within the substrate 100, the first region I and the second region II of the deep trench structure 130 and the portion of the substrate 100 adjacent to the first region I and the second region II of the deep trench structure 130 constitute a super junction structure. The super junction structure can not only improve the voltage endurance of the IGBT device, but also increase the minority carrier concentration in the drift region (substrate 100) under the condition of maintaining the voltage endurance.
On this basis, since the barrier doping region B is doped with third ions having the same conductivity type as the first ions (i.e., the opposite conductivity type to the second ions), and the body region 140 is higher than the contact surface 131 between the barrier doping region B and the second region I, the barrier doping region B realizes physical isolation between the body region 140 and the second region II. The minority carriers injected from the collector region 190, which enter the body region 140 through the deep trench structure 130, are blocked by the blocking doping region B at a distance from the body region 140, thereby reducing the minority carriers entering the body region 140. Further, minority carriers injected from the collector region 190 are better collected in the body region 140 and the drift region (substrate 100) portion under the gate structure 160, and the minority carrier concentration of the entire drift region is improved. Therefore, the on-resistance of the drift region can be reduced, the on-state voltage drop of the IGBT device can be reduced, and meanwhile the turn-off loss of the IGBT device can be improved. In conclusion, the performance of the IGBT device is improved.
In some practical applications, the turn-on voltage drop (VCE) of the IGBT device formed by the semiconductor structure in this embodiment can be as low as 1.452 v.
In the present embodiment, the material of the substrate 100 includes a semiconductor material. Specifically, the material of the substrate 100 includes silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In this embodiment, the first ions are N-type ions. Namely: the substrate 100 is an N-type substrate. Thus, the minority carriers are holes. Specifically, the N-type ions include phosphorus ions or arsenic ions.
In another embodiment, the first ions may also be P-type ions to form a device structure with a conductivity type completely opposite to that of the present embodiment.
In this embodiment, the second ions are P-type ions. Specifically, the P-type ions include boron ions or indium ions.
In this embodiment, the third ions are N-type ions.
In this embodiment, the body region 140 is doped with P-type ions, and the source region 150 is heavily doped with N-type ions.
In this embodiment, the collector region 190 is doped with fourth ions, the fourth ions are P-type ions, and the doping concentration of the fourth ions is greater than that of the second ions.
In the present embodiment, the minimum distance H1 between the blocking doping region B and the exposed surface of the first region I of the top surface 101 of the substrate 100 is greater than 1 micron.
If the minimum distance between the blocking doping region B and the top surface of the deep trench structure 130 is too small, the source region 150 is easily contacted with the blocking doping region B, and the source region 150 and the substrate 100 are short-circuited and cannot be switched through the gate structure 160, thereby deteriorating the reliability of the IGBT device. In addition, the minimum distance between the blocking doping region B and the top surface of the deep trench structure 130 is too small to facilitate the body region 140 to be higher than the contact surface 131 between the blocking doping region B and the second region II, thereby causing the blocking capability of the blocking doping region B for minority carriers (holes) to be deteriorated. Therefore, by making the minimum distance H1 between the blocking doped region B and the exposed surface of the first region I of the top surface 101 of the substrate 100 be greater than or equal to 1 μm, the reliability of the IGBT device can be better ensured, and at the same time, the blocking capability of the blocking doped region B for minority carriers (holes) is improved.
In the present embodiment, the height range H2 of the blocking doping region B is 1 to 10 micrometers in a direction perpendicular to the top surface 101 of the substrate 100.
The height range H2 of the blocking doping region B is too small to make the body region 140 higher than the contact surface 131 between the blocking doping region B and the second region II, thereby causing the blocking capability of the blocking doping region B for minority carriers (holes) to be poor. The height range H2 of the barrier doping region B is too large, so that the process difficulty of forming the barrier doping region B is increased, and the waste of the performance of the IGBT device is also caused. Therefore, with the appropriate height range H2, the blocking capability of the blocking doping region B for minority carriers (holes) can be improved, and the waste of the IGBT device in performance can be reduced.
Accordingly, in a direction perpendicular to the top surface 101 of the substrate 100, the minimum spacing H3 between the body region and the contact faces 131 of the barrier doping region B and the second region II is greater than 0 micron and less than or equal to 3 microns.
In this embodiment, the doping concentration of the third ions is higher than the doping concentration of the first ions.
Since the doping concentration of the third ions is higher than that of the first ions, the blocking capability of the blocking doping region B for holes injected from the collector region 190 to enter the body region 140 is further improved.
Preferably, the doping concentration of the third ions doped in the barrier doping region B ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
In this embodiment, the gate structure 160 includes: a gate electrode and a gate dielectric layer, the gate dielectric layer being located between the gate electrode and the substrate 100, and between the gate electrode and the body region 140 and the source region 150.
Specifically, the top surface 101 of the substrate 100 exposes the surfaces of the body region 140 and the source region 150
In this embodiment, the semiconductor structure further includes: the interlayer dielectric layer 170 is positioned on the top surface 101 of the substrate 100, the top surface of the gate structure 160, exposed surfaces of the body region 140 and the source region 150, and exposed surfaces of the first region I of the top surface 101 of the substrate 100; a first conductive structure (not shown) located in the interlayer dielectric layer 170, and connected to the gate structure 160; a second conductive structure 180 located in the interlayer dielectric layer 170, wherein the second conductive structure 180 connects the body region 140 and the source region 150.
The material of the interlayer dielectric layer 170 includes a dielectric material.
The first conductive structure is used to extract the gate structure 160 (the gate of the IGBT device).
The second conductive structure is used to extract the body region 140 and the source region 150 (emitter of the IGBT device).
In this embodiment, the semiconductor structure further includes: a bottom interlevel dielectric layer (not shown) located on the bottom surface 102 of the substrate 100 and on the surface of the exposed collector region 190; and a third conductive structure (not shown) in the bottom interlayer dielectric layer, wherein the third conductive structure is connected with the collector region 190 to lead out the collector region 190 (collector of the IGBT device).
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (21)

1. A semiconductor structure, comprising:
a substrate doped with first ions, the substrate having opposing top and bottom surfaces;
the deep groove structures are positioned in the substrate and are mutually independent, each deep groove structure comprises a first area, a second area and a doping blocking area between the first area and the second area, the first area and the second area are arranged in a direction vertical to the top surface of the substrate, the surface of the first area is exposed on the top surface of the substrate, second ions are doped in the first area and the second area, the conductivity types of the second ions are opposite to that of the first ions, third ions are doped in the doping blocking areas, and the conductivity types of the third ions are the same as that of the first ions;
the body region is positioned in the substrate between the adjacent deep groove structures and is higher than the contact surface of the barrier doping region and the second region;
the grid structure is positioned in the body region and the substrate, and the top surface of the substrate is exposed out of the top surface of the grid structure;
a source region located in the body region between the gate structure and the deep trench structure, the source region being higher than the barrier doping region;
and the collector region is positioned at the bottom of the substrate, the surface of the collector region is exposed from the surface of the bottom of the substrate, and the collector region and the bottom of the deep groove structure are separated by the substrate.
2. The semiconductor structure of claim 1, wherein a minimum spacing between the barrier doping region and a surface of the first region exposed at the top surface of the substrate is above 1 micron.
3. The semiconductor structure of claim 2, wherein a height of the barrier doping region in a direction perpendicular to the top surface of the substrate is in a range of 1 micron to 10 microns.
4. The semiconductor structure of claim 1, wherein a minimum spacing between a contact of the barrier doping region and the second region and the body region in a direction perpendicular to the top surface of the substrate is greater than 0 microns and less than or equal to 3 microns.
5. The semiconductor structure of claim 1, wherein a doping concentration of the third ions is higher than a doping concentration of the first ions.
6. The semiconductor structure of claim 5, wherein a doping concentration of the third ions doped within the barrier doping region ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
7. The semiconductor structure of claim 1, wherein the first and third ions are N-type ions and the second ions are P-type ions.
8. The semiconductor structure of claim 7, wherein the collector region is doped with fourth ions, the fourth ions are P-type ions, and a doping concentration of the fourth ions is greater than a doping concentration of the second ions.
9. The semiconductor structure of claim 1, wherein the body region is doped with P-type ions and the source region is doped with N-type ions.
10. The semiconductor structure of claim 1, wherein the gate structure comprises: the gate dielectric layer is positioned between the gate electrode and the substrate, and between the gate electrode and the body region and the source region.
11. The semiconductor structure of claim 1, wherein a top surface of the substrate exposes surfaces of the body and source regions, the semiconductor structure further comprising: the interlayer dielectric layer is positioned on the top surface of the substrate, the top surface of the grid structure, the exposed surfaces of the body region and the source region and the exposed surface of the first region on the top surface of the substrate; the first conductive structure is positioned in the interlayer dielectric layer and is connected with the grid structure; and the second conductive structure is positioned in the interlayer dielectric layer and is connected with the body region and the source region.
12. The semiconductor structure of claim 1, further comprising: and the third conductive structure is connected with the collector region.
13. A method of forming a semiconductor structure, comprising:
providing a substrate doped with first ions, the substrate having opposing top and bottom surfaces;
forming a plurality of mutually independent deep groove structures in the substrate, wherein the deep groove structures comprise a first region, a second region and a doping blocking region between the first region and the second region, the first region and the second region are arranged in a direction vertical to the top surface of the substrate, the surface of the first region is exposed on the top surface of the substrate, second ions are doped in the first region and the second region, the conductivity types of the second ions are opposite to that of the first ions, third ions are doped in the doping blocking region, and the conductivity types of the third ions are the same as that of the first ions;
after the deep groove structures are formed, forming a body region, a source region and a grid structure in the substrate between the adjacent deep groove structures, wherein the body region is higher than the contact surface of the barrier doping region and the second region, the grid structure is positioned in the body region and the substrate, the top surface of the substrate is exposed out of the top surface of the grid structure, the source region is positioned in the body region between the grid structure and the deep groove structures, and the source region is higher than the barrier doping region;
after the body region, the source region and the gate structure are formed, a collector region is formed at the bottom of the substrate, the surface of the collector region is exposed from the surface of the bottom of the substrate, and the collector region and the bottom of the deep groove structure are spaced by the substrate.
14. The method of claim 13, wherein forming a plurality of mutually independent deep trench structures in the substrate comprises: forming a plurality of initial deep groove structures which are independent from each other and are doped with second ions in the substrate, wherein the initial deep groove structures comprise a first area, a second area and an initial blocking doping area between the first area and the second area, and the first area and the second area are arranged along the direction vertical to the top surface of the substrate; and performing ion implantation on the initial barrier doping region from the surface of the first region by adopting a high-energy ion implantation process to form the deep groove structure and the barrier doping region, wherein the implantation energy of the high-energy ion implantation process is more than the preset first implantation energy.
15. The method of forming a semiconductor structure of claim 14, wherein forming a plurality of initial deep trench structures comprises: forming a deep trench mask layer on the top surface of the substrate, wherein the deep trench mask layer exposes part of the top surface of the substrate; etching the substrate by taking the deep groove mask layer as a mask, and forming a plurality of mutually independent deep grooves in the substrate; and forming the initial deep groove structure in the deep groove.
16. The method of claim 15, wherein the step of implanting ions from the surface of the first region into the initial barrier doping region using a high energy ion implantation process further comprises: and after the initial deep groove structure is formed, performing ion implantation from the surface of the first region to the initial barrier doping region by taking the deep groove mask layer as a mask.
17. The method of forming a semiconductor structure of claim 14, wherein the predetermined first implant energy is 2000 KeV.
18. The method of claim 17, wherein said high energy ion implantation process has an implantation energy of less than 4000 KeV.
19. The method of claim 18, wherein the process parameters of the high energy ion implantation process further comprise: the implant dose is 1E11 atoms per square centimeter to 1E14 atoms per square centimeter.
20. The method of forming a semiconductor structure of claim 13, wherein a top surface of the substrate exposes surfaces of the body region and the source region, the method further comprising: forming an interlayer dielectric layer on the top surface of the substrate, the top surface of the gate structure, the exposed surfaces of the body region and the source region and the exposed surface of the first region on the top surface of the substrate after forming the body region, the source region and the gate structure and before forming the collector region; forming a first conductive structure in the interlayer dielectric layer, wherein the first conductive structure is connected with the grid structure; and forming a second conductive structure in the interlayer dielectric layer, wherein the second conductive structure is connected with the body region and the source region.
21. The method of forming a semiconductor structure of claim 13, further comprising: and after the collector region is formed, forming a third conductive structure on the surface of the collector region.
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