CN113410296A - Silicon controlled rectifier structure - Google Patents
Silicon controlled rectifier structure Download PDFInfo
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- CN113410296A CN113410296A CN202110673779.3A CN202110673779A CN113410296A CN 113410296 A CN113410296 A CN 113410296A CN 202110673779 A CN202110673779 A CN 202110673779A CN 113410296 A CN113410296 A CN 113410296A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 37
- 239000010703 silicon Substances 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 256
- 239000000463 material Substances 0.000 claims abstract description 47
- 238000002955 isolation Methods 0.000 claims description 12
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
The application provides a silicon controlled rectifier structure relates to semiconductor technical field. In the present application, the thyristor structure includes an electrode structure and a semiconductor structure, and the electrode structure is electrically connected to the semiconductor structure. The semiconductor structure comprises at least one layer of N-type semiconductor material and at least one layer of P-type semiconductor material. At least one of the at least one N-type semiconductor material layer and the at least one P-type semiconductor material layer is a target semiconductor layer, and the target semiconductor layer comprises a plurality of sub-regions which are distributed in sequence and have different doping concentrations and/or different doping elements. Based on the structure design, the problem of poor dynamic characteristics in the existing silicon controlled structure can be improved.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a silicon controlled rectifier structure.
Background
The controllable silicon is used as an important power semiconductor device, and the application range is continuously expanded. In more application environments, the performance requirement on the controllable silicon is higher. However, the inventors have found that the conventional thyristor structure has a problem of poor dynamic characteristics.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a thyristor structure to solve the problem of poor dynamic characteristics in the conventional thyristor structure.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
a silicon controlled structure comprising an electrode structure and a semiconductor structure, the electrode structure being electrically connected to the semiconductor structure, the semiconductor structure comprising:
at least one N-type semiconductor material layer;
at least one P-type semiconductor material layer;
at least one of the at least one N-type semiconductor material layer and the at least one P-type semiconductor material layer is a target semiconductor layer, and the target semiconductor layer comprises a plurality of sub-regions which are distributed in sequence and have different doping concentrations and/or different doping elements.
In a preferred option of this embodiment of the present invention, in the silicon controlled rectifier structure, the at least one N-type semiconductor material layer includes a first semiconductor layer and a fourth semiconductor layer, and the at least one P-type semiconductor material layer includes a second semiconductor layer and a third semiconductor layer;
the second semiconductor layer is located on one side of the first semiconductor layer, the third semiconductor layer is located on one side, away from the second semiconductor layer, of the first semiconductor layer, and the fourth semiconductor layer is located on one side, away from the first semiconductor layer, of the second semiconductor layer.
In a preferred option of this embodiment of the present invention, in the silicon controlled rectifier structure, the at least one N-type semiconductor material layer further includes a fifth semiconductor layer, and the fifth semiconductor layer is located on a side of the third semiconductor layer away from the first semiconductor layer.
In a preferred option of this embodiment, in the silicon controlled rectifier structure, the second semiconductor layer and the third semiconductor layer are the target semiconductor layer respectively.
In a preferred option of this embodiment, in the silicon controlled rectifier structure, the fourth semiconductor layer and the fifth semiconductor layer are the target semiconductor layer respectively.
In a preferred option of this embodiment, in the silicon controlled rectifier structure, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer and the fifth semiconductor layer are the target semiconductor layers respectively.
In a preferred option of this embodiment of the present invention, in the silicon controlled rectifier structure, in a direction in which the plurality of semiconductor material layers included in the semiconductor structure are sequentially stacked, each of the target semiconductor layers includes a plurality of sub-regions that are sequentially stacked and distributed and have different doping concentrations and/or different doping elements.
In a preferred option of the embodiment of the present application, in the silicon controlled rectifier structure, in a direction in which the plurality of semiconductor material layers included in the semiconductor structure are sequentially stacked, each of the target semiconductor layers includes a plurality of sub-regions that are sequentially stacked and distributed and in which doping concentrations are sequentially increased or decreased.
In a preferred option of this embodiment of the present invention, in the above silicon controlled structure, the at least one N-type semiconductor material layer and the at least one P-type semiconductor material layer sequentially stacked include at least one target surface in two surfaces in the stacking direction:
the target surface comprises an anode region and a cathode region, the anode region and the cathode region are respectively in contact with the electrode structure, the anode region and the electrode structure form ohmic contact after heavy doping treatment, and the cathode region is not subjected to heavy doping treatment.
In a preferred option of the embodiment of the present application, in the silicon controlled rectifier structure, the target surface further includes an isolation region, and the isolation region is not heavily doped.
The application provides a silicon controlled rectifier structure is through forming a plurality of subregion that the doping concentration that distributes in proper order is different and/or the doping element is different in target semiconductor layer for can form the different doping concentration and/or the doping element of a plurality of levels, thereby promote the dynamic characteristic of silicon controlled rectifier, and then improve the not good problem of dynamic characteristic that exists in the silicon controlled rectifier structure now.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic structural diagram of a thyristor structure provided in an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure.
Fig. 3 is a second schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure.
Fig. 4 is a third schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure.
Fig. 5 is a fourth schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure.
Fig. 6 is a fifth schematic structural view of a semiconductor structure according to an embodiment of the present application.
Fig. 7 is a schematic distribution diagram of a surface region of a semiconductor structure according to an embodiment of the present disclosure.
Fig. 8 is a second schematic structural diagram of a thyristor structure according to an embodiment of the present application.
Icon: 100-a thyristor structure; 110-a semiconductor structure; a layer of 111-N type semiconductor material; l1 — first semiconductor layer; l4 — fourth semiconductor layer; l5-fifth semiconductor layer; a 115-P type semiconductor material layer; l2 — second semiconductor layer; l3 — third semiconductor layer; 120-electrode structure; 121-cathode anode configuration; 122-gate structure; 130-an anode region; 140-a cathode region; a 150-gate region; 160-isolation region.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1, the present embodiment provides a thyristor structure 100. The thyristor structure 100 may include a semiconductor structure 110 and an electrode structure 120.
In detail, the semiconductor structure 110 is electrically connected to the electrode structure 120. The semiconductor structure 110 includes at least one layer 111 of N-type semiconductor material and at least one layer 115 of P-type semiconductor material. At least one of the at least one N-type semiconductor material layer 111 and the at least one P-type semiconductor material layer 115 is a target semiconductor layer, and the target semiconductor layer includes a plurality of sub-regions (e.g., region 1, region 2, and region 3 shown in fig. 1) with different doping concentrations and/or different doping elements distributed in sequence.
Based on the method, by forming a plurality of sub-regions with different doping concentrations and/or different doping elements which are distributed in sequence in the target semiconductor layer, a plurality of levels of different doping concentrations and/or different doping elements can be formed, so that the dynamic characteristics of the silicon controlled rectifier are improved, and the problem of poor dynamic characteristics in the existing silicon controlled rectifier structure 100 is solved.
It is understood that, in an alternative example, in conjunction with fig. 2, the at least one N-type semiconductor material layer 111 includes a first semiconductor layer L1 and a fourth semiconductor layer L4, and the at least one P-type semiconductor material layer 115 includes a second semiconductor layer L2 and a third semiconductor layer L3.
The second semiconductor layer L2 is located on the side of the first semiconductor layer L1, the third semiconductor layer L3 is located on the side of the first semiconductor layer L1 away from the second semiconductor layer L2, and the fourth semiconductor layer L4 is located on the side of the second semiconductor layer L2 away from the first semiconductor layer L1. Based on this, a one-way thyristor including the first semiconductor layer L1, the second semiconductor layer L2, the third semiconductor layer L3, and the fourth semiconductor layer L4 may be formed.
It is understood that, in another alternative example, in conjunction with fig. 3, the at least one N-type semiconductor material layer 111 includes a first semiconductor layer L1, a fourth semiconductor layer L4, and a fifth semiconductor layer L5, and the at least one P-type semiconductor material layer 115 includes a second semiconductor layer L2 and a third semiconductor layer L3.
The second semiconductor layer L2 is located on one side of the first semiconductor layer L1, the third semiconductor layer L3 is located on one side of the first semiconductor layer L1 away from the second semiconductor layer L2, the fourth semiconductor layer L4 is located on one side of the second semiconductor layer L2 away from the first semiconductor layer L1, and the fifth semiconductor layer L5 is located on one side of the third semiconductor layer L3 away from the first semiconductor layer L1. Based on this, a triac including the first semiconductor layer L1, the second semiconductor layer L2, the third semiconductor layer L3, the fourth semiconductor layer L4, and the fifth semiconductor layer L5 may be formed.
It is to be understood that, on the basis of the above example, in an alternative example, the fourth semiconductor layer L4 may cover a partial region of the second semiconductor layer L2 on the basis that the fourth semiconductor layer L4 is located on the side of the second semiconductor layer L2 away from the first semiconductor layer L1.
In addition, a portion of the second semiconductor layer L2 not covered by the fourth semiconductor layer L4 on the side of the second semiconductor layer L2 away from the first semiconductor layer L1 is located in the same plane as the side of the fourth semiconductor layer L4 away from the first semiconductor layer L1.
It is to be understood that, on the basis of the above example, in an alternative example, the fifth semiconductor layer L5 may cover a partial region of the third semiconductor layer L3 on the basis that the fifth semiconductor layer L5 is located on the side of the third semiconductor layer L3 away from the first semiconductor layer L1.
In addition, a portion of the third semiconductor layer L3 not covered by the fifth semiconductor layer L5 on the side of the third semiconductor layer L3 away from the first semiconductor layer L1 is located in the same plane as the side of the fifth semiconductor layer L5 away from the first semiconductor layer L1.
It is understood that, in an alternative example, in conjunction with fig. 4, the second semiconductor layer L2 and the third semiconductor layer L3 may be the target semiconductor layer, respectively, and the first semiconductor layer L1, the fourth semiconductor layer L4, and the fifth semiconductor layer L5 may not belong to the target semiconductor.
That is, the second semiconductor layer L2 and the third semiconductor layer L3 may include a plurality of sub-regions having different doping concentrations and/or different doping elements, respectively, which are sequentially distributed. The first semiconductor layer L1, the fourth semiconductor layer L4 and the fifth semiconductor layer L5 may not include a plurality of sub-regions with different doping concentrations and/or different doping elements distributed in sequence, such as only one doping concentration, or only one doping element.
It is understood that, in another alternative example, in conjunction with fig. 5, the fourth semiconductor layer L4 and the fifth semiconductor layer L5 may be the target semiconductor layers, respectively, and the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may not belong to the target semiconductor.
That is, the fourth semiconductor layer L4 and the fifth semiconductor layer L5 may include a plurality of sub-regions having different doping concentrations and/or different doping elements, respectively, which are sequentially distributed. The first semiconductor layer L1, the second semiconductor layer L2 and the third semiconductor layer L3 may not include a plurality of sub-regions with different doping concentrations and/or different doping elements distributed in sequence, such as only one doping concentration, only one doping element, etc.
It is to be understood that, in another alternative example, in conjunction with fig. 6, the second semiconductor layer L2, the third semiconductor layer L3, the fourth semiconductor layer L4, and the fifth semiconductor layer L5 may be the target semiconductor layers, respectively, and the first semiconductor layer L1 may not belong to the target semiconductor.
That is, the second semiconductor layer L2, the third semiconductor layer L3, the fourth semiconductor layer L4, and the fifth semiconductor layer L5 may include a plurality of sub-regions having different doping concentrations and/or different doping elements, respectively, which are sequentially distributed. The first semiconductor layer L1 may not include a plurality of sub-regions with different doping concentrations and/or different doping elements distributed in sequence, such as only one doping concentration, only one doping element, etc.
It is understood that in an alternative example, for the N-type semiconductor material layer 111, the doping elements may include, but are not limited to, one or more of nitrogen, phosphorus, arsenic, antimony, bismuth, and the like. For the P-type semiconductor material layer 115, the doping elements may include, but are not limited to, one or more of boron, aluminum, gallium, indium, thallium, and the like.
It is understood that, on the basis of the above example, in order to make the dynamic characteristics of the silicon controlled rectifier structure 100 better, in an alternative example, in a direction in which the semiconductor structure 110 includes a plurality of semiconductor material layers that are sequentially stacked, each of the target semiconductor layers includes a plurality of sub-regions that are sequentially stacked and distributed and have different doping concentrations and/or different doping elements.
It is understood that, in an alternative example, in a direction in which the semiconductor structure 110 includes a plurality of semiconductor material layers stacked in sequence, each of the target semiconductor layers includes a plurality of sub-regions which are sequentially stacked and have sequentially increasing doping concentrations.
It is understood that, in an alternative example, in a direction in which the semiconductor structure 110 includes a plurality of semiconductor material layers stacked in sequence, each of the target semiconductor layers includes a plurality of sub-regions distributed in a stacked manner in sequence and having doping concentrations reduced in sequence.
It is to be understood that, in an alternative example, the directions of sequentially increasing or decreasing the plurality of sub-regions included in each target semiconductor layer may not be the same or may be different.
For example, in an alternative example, the first semiconductor layer L1 may not belong to the target semiconductor layer, and the other semiconductor layers located on both sides of the first semiconductor layer L1 include a plurality of sub-regions which are sequentially stacked and distributed and whose doping concentrations are sequentially increased in a direction from a side of the semiconductor layer close to the first semiconductor layer L1 to a side of the semiconductor layer away from the first semiconductor layer L1.
It is to be understood that, on the basis of the above example, in an alternative example, the at least one N-type semiconductor material layer 111 and the at least one P-type semiconductor material layer 115 may be sequentially stacked, and include at least one target surface in both surfaces in the stacking direction after being stacked.
With reference to fig. 7, the target surface includes an anode region 130 and a cathode region 140, the anode region 130 and the cathode region 140 are respectively in contact with the electrode structure 120, the anode region 130 forms ohmic contact with the electrode structure 120 after being heavily doped, and the cathode region 140 is not heavily doped.
Based on this, since the anode region 130 is heavily doped and the cathode region 140 is not heavily doped, the silicon controlled rectifier structure 100 can have ohmic contact characteristics, and can also avoid the problem that the trigger current is increased after the cathode region 140 is heavily doped, which causes the reduction of the current trigger sensitivity of the silicon controlled rectifier structure 100.
It is understood that heavily doping the anode region 130 may refer to heavily doping at least a region of the anode region 130 that is in contact with the electrode structure 120. The heavily doped area is not particularly limited, for example, the heavily doped area may be larger than an area of a region of the anode region 130 contacting the electrode structure 120, or the heavily doped area may be equal to an area of a region of the anode region 130 contacting the electrode structure 120.
It is understood that, in the above example, the anode region 130 may refer to a region corresponding to the P-type semiconductor material layer 115, and the cathode region 140 may refer to a region corresponding to the N-type semiconductor material layer 111.
It will be appreciated that on the basis of the above example, in an alternative example, the target surface may further comprise a gate region 150 and an isolation region 160.
The isolation region 160 is located between the anode region 130 and the cathode region 140, and the gate region 150, and the isolation region 160 is not heavily doped, so that the problems of gate short and the like can be avoided.
Based on this, in an alternative example, the region not heavily doped may include only the cathode region 140. In another alternative example, the region not heavily doped may include only the isolation region 160. In another alternative example, the regions that are not heavily doped may include the cathode region 140 and the isolation region 160.
It is to be understood that in the above examples, the specific patterns of the anode region 130, the cathode region 140, the gate region 150 and the isolation region 160 are not limited, and may be other patterns than the example shown in fig. 7, for example.
It will be appreciated that in an alternative example, in conjunction with fig. 8, the electrode structure 120 may include a cathode anode structure 121 and a gate structure 122. The cathode-anode structure 121 is in contact with the anode region 130 and the cathode region 140 to be electrically connected. The gate structure 122 may be in contact with the gate region 150 for electrical connection. The number of the cathode/anode structures 121 is at least two, and when one of the cathode structures is used as a cathode structure, the other can be used as an anode structure.
It is understood that, in an alternative example, both surfaces in the stacking direction after the at least one N-type semiconductor material layer 111 and the at least one P-type semiconductor material layer 115 are stacked may belong to the target surface, wherein one target surface may include the anode region 130, the cathode region 140, the gate region 150, and the isolation region 160, and the other target surface may include the anode region 130 and the cathode region 140.
To sum up, the silicon controlled rectifier structure 100 that this application provided is through forming a plurality of subregion that the doping concentration that distributes in proper order is different and/or the doping element is different in the target semiconductor layer for can form the different doping concentration and/or the doping element of a plurality of levels, thereby promote the dynamic characteristic of silicon controlled rectifier, and then improve the not good problem of dynamic characteristic that exists among the silicon controlled rectifier structure 100 now.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A silicon controlled structure comprising an electrode structure and a semiconductor structure, the electrode structure being electrically connected to the semiconductor structure, the semiconductor structure comprising:
at least one N-type semiconductor material layer;
at least one P-type semiconductor material layer;
at least one of the at least one N-type semiconductor material layer and the at least one P-type semiconductor material layer is a target semiconductor layer, and the target semiconductor layer comprises a plurality of sub-regions which are distributed in sequence and have different doping concentrations and/or different doping elements.
2. The silicon controlled structure according to claim 1, wherein the at least one layer of N-type semiconductor material comprises a first semiconductor layer and a fourth semiconductor layer, and the at least one layer of P-type semiconductor material comprises a second semiconductor layer and a third semiconductor layer;
the second semiconductor layer is located on one side of the first semiconductor layer, the third semiconductor layer is located on one side, away from the second semiconductor layer, of the first semiconductor layer, and the fourth semiconductor layer is located on one side, away from the first semiconductor layer, of the second semiconductor layer.
3. The silicon controlled structure according to claim 2, wherein the at least one layer of N-type semiconductor material further comprises a fifth semiconductor layer on a side of the third semiconductor layer remote from the first semiconductor layer.
4. The silicon controlled structure according to claim 3, wherein the second semiconductor layer and the third semiconductor layer are the target semiconductor layers, respectively.
5. The silicon controlled structure according to claim 3, wherein the fourth semiconductor layer and the fifth semiconductor layer are the target semiconductor layers, respectively.
6. The silicon controlled structure according to claim 3, wherein the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer are the target semiconductor layers, respectively.
7. The silicon controlled rectifier structure according to claim 1, wherein in a direction in which a plurality of semiconductor material layers included in the semiconductor structure are sequentially stacked, each of the target semiconductor layers includes a plurality of sub-regions which are sequentially stacked and distributed and have different doping concentrations and/or different doping elements.
8. The SCR structure of claim 7, wherein each target semiconductor layer comprises a plurality of sub-regions sequentially stacked and having sequentially increasing or decreasing doping concentrations in a direction in which the plurality of semiconductor material layers of the semiconductor structure are sequentially stacked.
9. The silicon controlled structure according to any one of claims 1-8, wherein the at least one layer of N-type semiconductor material and the at least one layer of P-type semiconductor material sequentially stacked include at least one target surface in two surfaces in a stacking direction:
the target surface comprises an anode region and a cathode region, the anode region and the cathode region are respectively in contact with the electrode structure, the anode region and the electrode structure form ohmic contact after heavy doping treatment, and the cathode region is not subjected to heavy doping treatment.
10. The silicon controlled structure of claim 9, wherein the target surface further comprises an isolation region, the isolation region not being heavily doped.
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| US20170287892A1 (en) * | 2016-03-31 | 2017-10-05 | Stmicroelectronics (Tours) Sas | Power component protected against overheating |
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| JP2020027815A (en) * | 2018-08-09 | 2020-02-20 | 国立大学法人名古屋大学 | Power semiconductor device and manufacturing method of the same |
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| GB2612636A (en) * | 2021-11-08 | 2023-05-10 | Mqsemi Ag | Semiconductor device |
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