CN113315500A

CN113315500A - Predriver stage with adjustable bias

Info

Publication number: CN113315500A
Application number: CN202110178336.7A
Authority: CN
Inventors: 马蒂因·弗里达斯·斯诺埃
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2020-02-27
Filing date: 2021-02-07
Publication date: 2021-08-27

Abstract

Embodiments of the present application relate to a predrive stage with adjustable bias. An electrical system (500) includes a power supply (502) and a circuit (504) coupled to the power supply (502) and including an operational amplifier (506). The operational amplifier (506) includes an input stage (202) and a pre-driver stage (204, 300, 400) coupled to the input stage (202), wherein the pre-driver stage (204, 300, 400) includes a first input terminal (304), a second input terminal (306), and a power supply terminal (302). The operational amplifier (506) also includes an output stage (210), the output stage (210) having a bipolar transistor coupled to the pre-driver stage (204, 300, 400). The pre-driver stage (204, 300, 400) is configured to: detecting a voltage difference across the first and second input terminals (304, 306) of the pre-driver stage (204, 300, 400); and providing an adjustable bias current (Iadjust) based on the voltage difference.

Description

Predriver stage with adjustable bias

CROSS-REFERENCE TO RELATED APPLICATIONS

Priority is claimed in U.S. provisional application No. 62/982,142 entitled "a Low Power BiCMOS Output Pre-Driver Stage with Class AB bias" (a Low-Power BiCMOS Output Pre-Driver Stage with Class AB Biasing) filed on 27/2/2020, which is incorporated herein by reference in its entirety.

Technical Field

Embodiments of the present application relate to an electrical system, in particular, to an operational amplifier including a predriver stage with adjustable bias.

Background

The rapid development of electronic devices and Integrated Circuit (IC) technology has led to the commercialization of IC products. With the development of new electronic devices and the advancement of IC technology, new IC products are beginning to be commercialized. One example of an IC product that is needed in electronic devices is an operational amplifier. In one example operational amplifier, bipolar transistors are used in at least one stage of the operational amplifier. Example output stage topologies for operational amplifiers include class a, class B, class AB, or class C topologies, where these topologies vary with the time period over which the active element(s) pass current, which is expressed as a fraction of the input signal waveform period. In a class a amplifier, the active components and associated bias circuitry are turned on throughout the entire input signal period, which is the most inefficient option. In a class B amplifier, each of the two active elements is only on during half the period of the input signal, which is more efficient than a class a amplifier, but cross-over distortion results when switching on between the active elements. In a class AB amplifier, each of the two active elements is turned on for more than half of the input signal period, which enables the amount of crossover distortion to be significantly reduced or eliminated. In class C amplifiers, the on-time of the active element is much less than half the input period, resulting in high efficiency and distortion.

For class AB amplifiers, providing bias current to both active elements is a significant problem affecting overall quiescent current and power consumption/heat dissipation. With the rapid development of multi-channel electronic systems, power consumption/heat dissipation of IC components, such as operational amplifiers, becomes a challenge, as well as presenting design and cost issues. Efforts to reduce power consumption/heat dissipation of operational amplifiers with class AB output stages are ongoing.

Disclosure of Invention

According to at least one example embodiment of the present disclosure, an electrical system includes a power supply, and a circuit coupled to the power supply and including an operational amplifier. The operational amplifier includes an input stage and a pre-driver stage coupled to the input stage, wherein the pre-driver stage includes a first input terminal, a second input terminal, and a power supply terminal. The operational amplifier also includes an output stage having a bipolar transistor coupled to the pre-driver stage. The pre-driver stage is configured to: detecting a voltage difference across the first and second input terminals of the pre-driver stage; and providing an adjustable bias current based on the voltage difference.

According to at least one example embodiment of the present disclosure, an operational amplifier includes an input stage and a pre-driver stage coupled to the input stage. The pre-driver stage includes: a first input terminal; a second input terminal; and a bias current control circuit coupled to the first and second input terminals and configured to provide an adjustable bias current based on a voltage difference across the first and second input terminals. The operational amplifier also includes an output stage having a bipolar transistor coupled to the pre-driver stage.

According to at least one example embodiment of the present invention, a predriver circuit includes first and second input terminals. The pre-driver circuit also includes a class AB bias current generator configured to output a control current as a function of a voltage difference across the input terminals. The pre-driver circuit also includes a current mirror coupled to the class AB bias current generator, wherein the current mirror is configured to add an adjustable bias current to a fixed bias current of the pre-driver circuit based on the control current.

Drawings

Fig. 1 is a schematic diagram showing an operational amplifier circuit according to the conventional art.

FIG. 2 is a diagram showing an operational amplifier according to an example embodiment;

FIG. 3 is a diagram showing a bipolar and complementary metal oxide semiconductor (BiCMOS) pre-driver stage according to an example embodiment;

FIG. 4 is a schematic diagram showing a BiCMOS predriver stage according to an example embodiment; and

FIG. 5 is a block diagram showing an electrical system, according to an example embodiment.

Detailed Description

Predriver stage topologies with adjustable bias current and related circuits and systems are described herein. In one example, the predriver stage is used to provide a base current for a bipolar junction transistor (a "BJT" or just a "bipolar" transistor herein) of the output stage of the operational amplifier, where the output stage uses a class AB bias. In the described examples, the described predriver stage topology improves power efficiency over other predriver stage topologies by supporting lower quiescent currents. In some examples, the pre-driver stage uses a small fixed bias current to ensure fast response of the pre-driver stage components. Further, the pre-driver stage adds an adjustable bias current to the fixed bias current, wherein the adjustable bias current increases as a voltage difference across the first and second input terminals of the pre-driver stage increases. In one example, the voltage difference represents a difference between an input Voltage (VIN) at the first input terminal and a reference Voltage (VREF) at the second input terminal. In another example, the voltage difference represents a differential signal (Vina and Vinb) between the first and second input terminals. In either case, the absolute magnitude of the voltage difference across the first and second input terminals may be used to change the adjustable bias current. With a fixed bias current and an adjustable bias current, the predriver stage is able to provide sufficient base current for the output stage while maintaining a low quiescent current. In one example, the pre-driver stage is a bipolar and Complementary Metal Oxide Semiconductor (CMOS) pre-driver stage to provide high input impedance. In another example, the pre-driver stage is a bipolar pre-driver stage. In either case, the reduction of quiescent current in a predriver stage topology as described is important in a circuit or system where quiescent current has a significant impact on power consumption or heat dissipation. For a better understanding, various pre-driver level options and related issues are described using the following figures.

Fig. 1 is a schematic diagram showing an operational amplifier circuit 100 according to an example. The operational amplifier circuit 100 includes an output stage formed by two transistors (Q13 and Q14) connected in series between a power supply terminal 102 and a ground terminal 108. Between Q13 and Q14 is an output terminal 106. The operational amplifier circuit 100 also includes an input voltage (Vin) terminal 104 and a reference voltage (Vref) terminal. When a voltage difference occurs across the Vin terminal 104 and the Vref terminal, the operational amplifier circuit 100 operates to provide an output signal at the output terminal 106 based on the voltage difference. Specifically, the operational amplifier circuit 100 controls the output signal at the output terminal 106 using a pre-driver circuit formed by transistors Q1-Q12, resistor R1, current sources I1-I4, capacitors C1 and C2, and a class AB control circuit 110.

As shown in fig. 1, when the voltage level at the Vin terminal 104 rises relative to the voltage level at the Vref terminal 105, current from the power supply terminal flows through Q2 to the base terminal of Q13, thereby raising the voltage of Q13 and thus lowering its collector current. After a delay, the current from the power supply terminal 102 flows through Q1, Q3, and Q6 to the base terminal of Q14, causing Q14 to increase the collector current, which, along with the decreased collector current of Q13, decreases the voltage on the output terminal 108. For the predriver stage, half of the base current of Q14 is provided directly, and the other half of the base current is provided via the current mirror of class AB control circuit 110. To ensure that Q13 and Q14 operate properly and provide a target output current of 20mA, some minimum level of current is required. The minimum bias current of I1 to I4 is Iout/beta²Where β is the transistor current gain. For Iout ═ 20mA and a minimum β of 50, at least 24uA is needed (4 uA for each of I1-I4, 4uA for each of the two central branches). While the gain stage 100 provides good total harmonic distortion and high current drive, the 24uA quiescent current for the predriver stage represents significant power consumption.

Fig. 2 is a diagram showing an operational amplifier 200 according to an example embodiment. In fig. 2, operational amplifier 200 includes

several stages

202, 204, 210, and 212 as shown, where each of

stages

202, 204, and 212 includes a first (upper) input, a second (lower) input, a first (upper) output, and a second (lower) output, and where stage 210 includes a first (upper) input, a second (lower) input, and a single output.

In the example of fig. 2, the first stage 202 is a stage having a first gain (gm)₁) The second stage 204 is a second stage having a second gain (gm)₂) And the third stage 210 is a pre-driver stage having a third gain (gm)₃) Wherein the first stage 202, the second stage 204, and the third stage 210 are connected in series. In some examples, there is a fourth gain (gm)₄) Is part of a feed-forward loop between the

differential inputs

214A and 214B and the first and second outputs of the second stage 204. As shown, the operational amplifier 200 also includes a number of capacitors C3-C6. Specifically, C3 is coupled between the second output of the first stage 202 and the ground terminal 216, C4 is coupled between the second input and the output of the third stage 210, C5 is coupled between the first output of the first stage 202 and the output of the third stage 210, and C6 is coupled between the first input of the third stage 210 and the output of the third stage 210. In other examples, the arrangement of stages and/or other components in an operational amplifier, such as operational amplifier 200, may be different than that shown in fig. 2. In one example, the fourth stage 212 is omitted.

In the example of fig. 2, the second stage 204 is a BiCMOS pre-driver stage with a VIN-dependent bias control circuit 208. In other examples, the second stage 204 is a bipolar pre-driver stage with a VIN-dependent bias control circuit 208. In either case, the quiescent current of the second stage 204 is reduced compared to the pre-driver stage of the operational amplifier circuit 100 of fig. 1, while supporting the same Iout level (e.g., 20 mA). The use of CMOS transistors (e.g., NMOS transistors M1 and M2 in fig. 3 and 4) in the second stage 204 (as in the BiCMOS predriver stage example) also has the advantage of high input impedance and infinite base current for some transistors (e.g., Q3 and Q4 in fig. 3 and 4). In the bipolar pre-driver example, the input impedance is not as high as the BiCMOS pre-driver example, but the quiescent current is still lower than the pre-driver stage of the operational amplifier circuit 100 of fig. 1.

In some examples, VIN-dependent bias control circuit 208 uses class AB biasing, where transistors M1 and M2 (see fig. 3 and 4) are biased by a constant or fixed bias current and an adjustable bias current that varies as a function of the absolute magnitude of the differential voltage between the input terminals or between the input terminal and the reference voltage terminal. With a fixed bias current and an adjustable bias current as described herein, VIN-dependent bias control circuit 208 is able to provide a base current to drive the transistors of output stage 210.

Fig. 3 is a diagram showing a BiCMOS predriver stage 300 (an example of the second stage 204 in fig. 2), according to an example embodiment. As shown, the BiCMOS pre-driver stage 300 includes a set of transistors Q1-Q8, a resistor R1, and current sources I1 and I2 with the arrangement described in fig. 1 for the pre-driver stage. More specifically, Q1, Q2, Q5, and Q6 are PNP bipolar transistors, and Q3, Q4, Q7, and Q8 are NPN bipolar transistors. As shown, the BiCMOS predriver stage 300 includes terminals such as a power supply terminal 302, a ground terminal 320,

input voltage terminals

304 and 306, and output terminals 308 and 310. Although input terminal 306 is represented in fig. 3 as an input voltage (e.g., Vinb) terminal, it should be understood that in other examples, input terminal 306 is a VREF terminal. In addition, the BiCMOS predriver stage 300 includes NMOS transistors M1 and M2 and diodes D1-D4 in the arrangement shown.

In the example of fig. 3, the BiCMOS predriver stage 300 includes a VIN-dependent bias control circuit 312 (an example of the VIN-dependent bias control circuit 208 in fig. 2) having an output coupled to the base terminals of Q5 and Q6. As the figure shows, VIN dependent bias control circuit 312 includes a class AB bias generator 314 that outputs a control current (Iboost)316 that increases as the voltage difference at

input terminals

304 and 306 increases. In some example embodiments, control current 316 increases as | Vina-Vinb | increases, where Vina is the voltage level at input terminal 304 and Vinb is the voltage level at input terminal 306. These

input terminals

304 and 306 are also coupled to a class AB bias generator 314, resulting in VIN-dependent bias control as described herein. In the example of fig. 3, VIN-dependent bias control circuit 312 also includes a current mirror 318 (based on transistors Q15-Q17 in the arrangement shown), where the input to current mirror 318 is control current 316. The output of current mirror 318 is provided to the base terminals of Q5 and Q6.

As shown in the example of fig. 3, the collector terminal of Q5 is coupled to ground terminal 320 via Q7, wherein the base terminal of Q7 is coupled to the collector terminals of Q5 and Q7, and wherein the emitter terminal of Q7 is coupled to the ground terminal. Further, the collector terminal of Q6 is coupled to ground terminal 320 via Q8, with the base terminal of Q8 coupled to the base terminal of Q7. Further, the collector terminals of Q6 and Q8 are coupled together, and the emitter terminal of Q8 is coupled to the ground terminal 320. Further, the collector terminals of Q6 and Q8 are coupled together, and the emitter terminal of Q8 is coupled to the ground terminal 320. As shown, the collector terminals of Q6 and Q8 are also coupled to an NPN output terminal 310, which provides a base current to an NPN bipolar transistor (e.g., Q14 in fig. 1) of an output stage, such as output stage 210 in fig. 2.

In the example of fig. 3, the emitter terminals of Q1 and Q2 are coupled to the power supply terminal 302. Further, the base terminals of Q1 and Q2 are coupled together and to the collector terminals of Q1 and Q3. As shown, the collector terminals of Q2 and Q4 are coupled to PNP output terminal 308, which provides base current to a PNP bipolar transistor (e.g., Q13 in fig. 1) of an output stage, such as output stage 210 in fig. 2.

Using the BiCMOS predriver stage 300, the quiescent current of the gain stage (e.g., the second stage 204 of fig. 2) is reduced while supporting the same Iout level (e.g., 20mA) as compared to the gain stage 100 of fig. 1. The use of CMOS transistors (e.g., NMOS transistors M1 and M2 in fig. 3) in the BiCMOS predriver stage 300 also has the advantage of high input impedance and infinite base current for some transistors (e.g., Q3 and Q4 in fig. 3). In some examples, VIN-dependent bias control circuit 312 uses class AB bias generator 314 to provide an adjustable current, where M1 and M2 are biased by a constant or fixed current provided by I1 and I2 and an adjustable current from VIN-dependent bias control circuit 312. Based on the fixed current and the adjustable current, the base current is output to the output terminals 308 and 310 of the BiCMOS predriver stage 400 to drive the transistors (e.g., Q13 and Q14 in fig. 1) of the output stage. In other example embodiments, M1 and M2 are replaced with NPN bipolar transistors. In this example, the pre-driver stage still provides a fixed bias current and an adjustable bias current, with reduced input impedance compared to the BiCMOS pre-driver stage 300, as described herein.

Figure 4 is a schematic diagram showing a BiCMOS predriver stage 400, according to an example embodiment. As shown, the BiCMOS predriver stage 400 includes the same components described for the BiCMOS predriver stage 300 of fig. 3, with additional details of the VIN-dependent bias control circuit 312A in fig. 4 (an example of the VIN-dependent bias control circuit 312 in fig. 3) being given. In the example of fig. 4, VIN-dependent bias control circuit 312A includes a class AB bias generator 314A (an example of class AB bias generator 314), with transistors Q18-Q21 and resistor R2 arranged as shown. In fig. 4, Q18 through 21 and R2 of class AB bias generator 314A have the same topology as Q3 through Q6 and R1. As shown, the base terminals of Q3 and Q18 are coupled to the same terminal (labeled a in fig. 4), the base terminals of Q4 and Q19 are coupled to the same terminal (labeled B in fig. 4), the base terminals of Q5 and Q20 are coupled to the same terminal (labeled C in fig. 4), and the base terminals of Q6 and Q21 are coupled to the same terminal (labeled D in fig. 4).

In fig. 4, M1 of BiCMOS predriver stage 400 is a first NMOS transistor having its drain terminal coupled to power supply terminal 302, its gate terminal coupled to first input terminal 304, and its source terminal coupled to the base terminal of a first bipolar transistor (e.g., Q3) of the BiCMOS predriver stage. Further, M2 of BiCMOS predriver stage 400 is a second NMOS transistor having its drain terminal coupled to power supply terminal 302, its gate terminal coupled to a VREF or Vinb terminal (e.g., input terminal 306), and its source terminal coupled to the base terminal of a second bipolar transistor of the BiCMOS predriver stage. In some examples, BiCMOS predriver circuit 400 has topological portions (e.g., Q3-Q6 and R1) that include: a first bipolar transistor (e.g., Q3); a second bipolar transistor (e.g., Q4) having a collector terminal coupled to the output stage (at output terminal 308); a third bipolar transistor (e.g., Q5) having a base terminal coupled to the base terminal of the first bipolar transistor (e.g., Q3) via first and second diodes (e.g., D1 and D2) in series, wherein cathodes of the first and second diodes are toward the base terminal of the third bipolar transistor (e.g., Q5); and a fourth bipolar transistor (e.g., Q6) having a collector terminal connected to the output stage (at the output terminal 310) and a base terminal coupled to the base terminal of the second bipolar transistor (e.g., Q4) via third and fourth diodes (e.g., D3 and D4 in fig. 3 and 4) in series, with cathodes of the third and fourth diodes facing the base terminal of the fourth bipolar transistor (e.g., Q6).

As shown in fig. 3 and 4, the emitter terminals of the first and third bipolar transistors (e.g., Q3 and Q5) are coupled together. In addition, emitter terminals of the second and fourth bipolar transistors (e.g., Q4 and Q6) are coupled together. Further, emitter terminals of the first and third bipolar transistors (e.g., Q3 and Q5) are coupled to emitter terminals of the second and fourth bipolar transistors (e.g., Q4 and Q6) via a resistor (e.g., R1). In addition, the base terminals of the first, second, third and fourth bipolar transistors (coupled to A, B, C and the D terminal in fig. 4) of BiCMOS predriver stage 400 are coupled to a class AB bias current generator 314A. In some example embodiments, the class AB bias current generator 312A has a transistor topology (e.g., Q18-Q21 and R2 in fig. 4) equal to another topological portion of the BiCMOS pre-driver stage (e.g., Q3-Q6 and R1 in fig. 4). In the topology of fig. 4, there is no need for separate sensing of Vina or Vinb. Conversely, Q8-Q11 of the class AB bias generator 314A are coupled to terminals A-D, as shown. Although this can produce positive feedback, by making R2> R1, the gain of this loop is much less than 1.

FIG. 5 is a block diagram showing an electrical system 500, according to an example embodiment. As shown, the electrical system 500 includes a power source 502 (e.g., a battery, switching converter, or other power source) and circuitry 504 coupled to the power source 502. The circuit 504 includes an operational amplifier 506 (an example of the operational amplifier 200 in fig. 2) having a second stage 204. As described herein, the second stage 204 is a BiCMOS pre-driver stage with VIN-dependent bias control circuit 208 as described herein, wherein the BiCMOS pre-driver stage has the advantages of low quiescent current and high input impedance (due to M1 and M2). In other examples, the second stage 204 is a bipolar pre-driver stage with a VIN-dependent bias control circuit 208. In either case, the second stage 206 is configured to provide an adjustable bias voltage as described herein. As shown, in fig. 5, the circuit 504 includes other components 508 (e.g., input-side components or output-side components). Reduced power consumption is beneficial in many multi-channel industrial systems where a large number of operational amplifiers, such as operational amplifier 506, are used at high supply voltages. Thus, reduced power consumption may reduce heat generation and simplify the thermal design thereof.

The term "coupled" is used throughout this description. The terms may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this description. For example, if device a generates a signal to control device B to perform an action, then in a first instance device a is coupled to device B through a direct connection, or in a second instance device a is coupled to device B through intermediate component C if intermediate component C does not change the functional relationship between device a and device B such that device B is controlled by device a via the control signal generated by device a.

Modifications in the described embodiments are possible, and other embodiments are possible within the scope of the claims.

Claims

1. An electrical system, comprising:

a power source;

a circuit coupled to the power supply and including an operational amplifier having:

an input stage;

a pre-driver stage coupled to the input stage, wherein the pre-driver stage includes a first input terminal, a second input terminal, and a power supply terminal; and

an output stage having a bipolar transistor coupled to the pre-driver stage, wherein the pre-driver stage is configured to:

detecting a voltage difference across the first and second input terminals of the pre-driver stage; and

an adjustable bias current is provided based on the voltage difference.

2. The electrical system of claim 1, wherein the pre-driver stage includes a bias current control circuit configured to provide the adjustable bias current based on a voltage difference due to an input voltage (Vina) at the first input terminal of the pre-driver stage and another voltage (Vinb) at the second input terminal of the pre-driver stage, wherein the adjustable bias current is a function of | Vina-Vinb |.

3. The electrical system of claim 2, wherein the bias current control circuit is configured to add the adjustable bias current to a fixed bias current of the pre-driver stage, and wherein the adjustable bias current increases as | Vina-Vinb | increases.

4. The electrical system of claim 3, wherein the bias current control circuit comprises:

a class AB bias current generator configured to output a control current as a function of Vina and Vinb; and

a current mirror coupled to the class AB bias current generator, wherein the current mirror is configured to add the adjustable bias current to the fixed bias current of the pre-driver stage based on the control current.

5. The electrical system of claim 1, wherein the pre-driver stage is a bipolar pre-driver stage comprising:

a first NPN bipolar transistor having a collector terminal coupled to the power supply terminal, a base terminal coupled to the first input terminal, and an emitter terminal coupled to a base terminal of a second NPN bipolar transistor of the bipolar pre-driver stage; and

a third NPN bipolar transistor having a collector terminal coupled to the power supply terminal, a base terminal coupled to the second input terminal, and an emitter terminal coupled to a base terminal of a fourth NPN bipolar transistor of the bipolar pre-driver stage.

6. The electrical system of claim 1, wherein the pre-driver stage is a bipolar and complementary metal oxide semiconductor (BiCMOS) pre-driver stage comprising:

a first n-type metal-oxide-semiconductor (NMOS) transistor having a drain terminal coupled to the power supply terminal, a gate terminal coupled to the first input terminal, and a source terminal coupled to a base terminal of a first bipolar transistor of the BiCMOS pre-driver stage; and

a second NMOS transistor having a drain terminal coupled to the power supply terminal, a gate terminal coupled to the second input terminal, and a source terminal coupled to a base terminal of a second bipolar transistor of the BiCMOS pre-driver stage.

7. The electrical system of claim 6, wherein the BiCMOS predriver circuit has a topology portion comprising:

the first bipolar transistor;

the second bipolar transistor having a collector terminal coupled to the output stage;

a third bipolar transistor having a base terminal coupled to the base terminal of the first bipolar transistor via first and second diodes in series, wherein cathodes of the first and second diodes face the base terminal of the third bipolar transistor; and

a fourth bipolar transistor having its collector terminal coupled to the output stage and having its base terminal coupled to the base terminal of the second bipolar transistor via a third and fourth diode in series, wherein cathodes of the third and fourth diodes face the base terminal of the fourth bipolar transistor,

wherein the emitter terminals of the first and third bipolar transistors are coupled together,

wherein emitter terminals of the second and fourth bipolar transistors are coupled together, an

Wherein the emitter terminals of the first and third bipolar transistors are coupled to the emitter terminals of the second and fourth bipolar transistors via resistors.

8. The electrical system of claim 7, wherein the base terminals of the first, second, third, and fourth bipolar transistors of the BiCMOS predriver stage are coupled to the class AB bias current generator.

9. The electrical system of claim 8, wherein the class AB bias current generator has a transistor topology that is equal to the topology portion of the BiCMOS predriver stage.

10. An operational amplifier, comprising:

an input stage; and

a pre-driver stage coupled to the input stage, wherein the pre-driver stage includes:

a first input terminal;

a second input terminal; and

a bias current control circuit coupled to the first and second input terminals and configured to provide an adjustable bias current based on a voltage difference across the first and second input terminals; and

an output stage having a bipolar transistor coupled to the pre-driver stage.

11. The operational amplifier of claim 10, wherein the bias current control circuit is configured to increase the adjustable bias current in response to an increase in an absolute value of a voltage difference across the first terminal and the second terminal.

12. The operational amplifier of claim 11, wherein the bias current control circuit is configured to add the adjustable bias current to a fixed bias current of the pre-driver stage.

13. The operational amplifier of claim 10, wherein the pre-driver stage is a bipolar and complementary metal oxide semiconductor (BiCMOS) pre-driver stage comprising:

a first n-type metal-oxide-semiconductor (NMOS) transistor having a drain terminal coupled to a power supply terminal of the pre-driver stage, a gate terminal coupled to the first input terminal, and a source terminal coupled to a base terminal of a first bipolar transistor of the BiCMOS pre-driver stage; and

14. The operational amplifier of claim 11, wherein the bias current control circuit comprises:

a class AB bias current generator configured to output a control current as a function of an absolute value of the voltage difference across the input terminals; and

a current mirror coupled to the class AB bias current generator, wherein the current mirror is configured to add the adjustable bias current to the fixed bias current of the BiCMOS pre-driver stage based on the control current.

15. The operational amplifier of claim 13, wherein the BiCMOS predriver stage has a topology portion comprising:

the first bipolar transistor;

16. The operational amplifier of claim 15, wherein the base terminals of the first, second, third and fourth bipolar transistors of the BiCMOS pre-driver stage are coupled to the class AB bias current generator.

17. The operational amplifier of claim 16, wherein the class AB bias current generator has a transistor topology that is partially equal to the topology of the BiCMOS pre-driver stage.

18. A pre-driver circuit, comprising:

first and second input terminals;

a class AB bias current generator configured to output a control current as a function of a voltage difference across the input terminals; and

a current mirror coupled to the class AB bias current generator, wherein the current mirror is configured to add an adjustable bias current to a fixed bias current of the pre-driver circuit based on the control current.

19. The pre-driver circuit of claim 18, wherein the pre-driver circuit is a bipolar and complementary metal oxide semiconductor (BiCMOS) pre-driver circuit comprising:

a first n-type metal-oxide-semiconductor (NMOS) transistor having a drain terminal coupled to a power supply terminal, a gate terminal coupled to the first input terminal, and a source terminal coupled to a base terminal of a first bipolar transistor of the BiCMOS pre-driver stage; and

20. The predriver circuit of claim 19, wherein the BiCMOS predriver stage has a topology portion, the topology portion including:

the first bipolar transistor;

21. The predriver circuit of claim 20, wherein the base terminals of the first, second, third, and fourth bipolar transistors of the BiCMOS predriver stage are coupled to the class AB bias current generator.

22. The predriver circuit of claim 21, wherein the class AB bias current generator has a transistor topology that is equal to the topology portion of the BiCMOS predriver stage.