CN113191975A

CN113191975A - Image distortion correction method and device

Info

Publication number: CN113191975A
Application number: CN202110478136.3A
Authority: CN
Inventors: 汪涛; 陈智; 陈欢
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2021-04-29
Filing date: 2021-04-29
Publication date: 2021-07-30

Abstract

The embodiment of the application discloses an image distortion correction method and device, and the method comprises the following steps: calculating at least one first distortion coordinate, wherein each first distortion coordinate is a coordinate of one first sequence block in a distorted image, and the distorted image is stored in the DDR; loading first image data in the distorted image into a first SRAM based on the at least one first distortion coordinate; and carrying out distortion correction processing on the first image data, calculating at least one second distortion coordinate, and loading the second image data in the distorted image into a second SRAM. The image data in at least one distortion coordinate range are loaded to the SRAM from the DDR at one time, interaction times of the image distortion correction process and the DDR are reduced, the image data are loaded to the SRAM from the DDR through a ping-pong mechanism to be subjected to distortion correction, efficiency of accessing the DDR through an algorithm is improved, and then correction speed of the image distortion correction algorithm is improved.

Description

Image distortion correction method and device

Technical Field

The present application relates to the field of image processing technologies, and in particular, to a method and an apparatus for correcting image distortion.

Background

The conventional lenses include a normal lens, a wide-angle lens and a fisheye lens, wherein the normal lens has a small viewing angle of about 30 ° to 60 °, the wide-angle lens has a relatively wide viewing angle of about 90 ° to 140 °, and the fisheye lens is a special lens in the wide-angle lens, and the viewing angle of the fisheye lens reaches or exceeds the range that human eyes can see, and generally reaches 200 ° to 230 °. With the development of scientific technology, in the fields of military affairs, medical treatment, transportation, explosion prevention and the like, people generally use wide-angle lenses to obtain more and larger real scene information, but due to the influence of many factors, a picture shot through the wide-angle lenses can be distorted to a certain extent in the imaging process.

Under the scene that the image shot by the ultra-wide angle distortion lens has image distortion deformation, the image can be restored to be an undistorted image through interpolation of a specific distortion correction algorithm. In the process of distortion correction, image Data needs to be searched from an original distorted image stored in a Double Data Rate (DDR) memory point by point, and then interpolation is performed on the taken Data to insert out an undistorted point, so that correction of the whole frame of image is completed. The currently common method is that one point is output every time of interpolation, and original image data needs to be acquired from the DDR every time of interpolation of one point, so the number of times of outputting the size of an image determines the number of times of interaction with the DDR, and frequent interaction with the DDR greatly affects the algorithm correction speed.

Disclosure of Invention

The embodiment of the application provides an image distortion correction method and device, which can reduce the number of times of interaction with a DDR in the image distortion correction process, improve the efficiency of accessing the DDR by an algorithm, and further improve the correction speed of an image distortion correction algorithm.

In a first aspect, an embodiment of the present application provides an image distortion correction method, where the method includes:

calculating at least one first distortion coordinate, wherein each first distortion coordinate is a coordinate of one first sequence block in a distorted image, and the distorted image is stored in the DDR;

loading first image data in the distorted image into a first Static Random Access Memory (SRAM) based on the at least one first distortion coordinate, wherein the first image data is image data in a range of the at least one first distortion coordinate;

and carrying out distortion correction processing on the first image data, meanwhile, calculating at least one second distortion coordinate, wherein each second distortion coordinate is a coordinate of a second sequence block in a distorted image, and loading the second image data in the distorted image into a second SRAM (static random access memory) based on the at least one second distortion coordinate, wherein the second image data is image data in the range of the at least one second distortion coordinate.

In a second aspect, an image distortion correcting apparatus provided in an embodiment of the present application includes:

the calculation unit is used for calculating at least one first distortion coordinate, each first distortion coordinate is a coordinate of one first sequence block in a distortion image, and the distortion image is stored in the DDR;

a loading unit, configured to load, based on the at least one first distortion coordinate, first image data in the distorted image into a first Static Random Access Memory (SRAM), where the first image data is in a range of the at least one first distortion coordinate;

and the correcting unit is used for carrying out distortion correction processing on the first image data and simultaneously calculating at least one second distortion coordinate, each second distortion coordinate is a coordinate of one second sequence block in a distorted image, and the second image data in the distorted image is loaded into a second SRAM (static random access memory) based on the at least one second distortion coordinate, and is image data in the range of the at least one second distortion coordinate.

In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a memory, a communication interface, and one or more programs, which are stored in the memory and configured to be executed by the processor, and which include instructions for performing some or all of the steps described in the method of the first aspect.

In a fourth aspect, the present application provides a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform some or all of the steps described in the method of the first aspect.

In a fifth aspect, the present application provides a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps described in the method according to the first aspect of the present application. The computer program product may be a software installation package.

By implementing the embodiment of the application, the technical scheme provided by the application calculates at least one first distortion coordinate, each first distortion coordinate is a coordinate of one first sequence block in a distorted image, and the distorted image is stored in the DDR; loading first image data in the distorted image into a first SRAM based on the at least one first distortion coordinate, wherein the first image data is image data within the range of the at least one first distortion coordinate; and carrying out distortion correction processing on the first image data, simultaneously calculating at least one second distortion coordinate, wherein each second distortion coordinate is a coordinate of one second sequence block in a distorted image, and loading the second image data in the distorted image into a second SRAM (static random access memory) based on the at least one second distortion coordinate, wherein the second image data is image data in the range of the at least one second distortion coordinate. According to the method and the device, at least one distortion coordinate of the sequence block in the distortion image is calculated, so that image data in the range of the at least one distortion coordinate can be loaded from the DDR at one time, the interaction times with the DDR in the image distortion correction process are reduced, the image data are loaded into the SRAM from the DDR through a ping-pong mechanism to be subjected to distortion correction, the efficiency of accessing the DDR by an algorithm is improved, and the correction speed of the image distortion correction algorithm is further improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a scene schematic diagram of a distorted image in an image capturing apparatus according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of an image distortion correction method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a distorted coordinate mapping provided by an embodiment of the present application;

fig. 4 is a schematic diagram of an image distortion correction processing based on a ping-pong mechanism according to an embodiment of the present disclosure;

fig. 5a is a block diagram illustrating functional units of an image distortion correcting apparatus according to an embodiment of the present disclosure;

FIG. 5b is a block diagram illustrating functional units of another image distortion correction apparatus according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

First, partial terms related to the embodiments of the present application are explained so as to be easily understood by those skilled in the art.

1. And (3) distortion correction: the distortion correction of the wide-angle lens is to correct the nonlinear distortion generated by the wide-angle lens, and comprises two stages of image calibration and image correction, wherein the image calibration is to calculate internal and external parameters and distortion parameters of the wide-angle lens, and the image correction is to remap and reconstruct the gray level of a distorted image by utilizing the image calibration parameters so as to achieve the correction effect. The distortion is an offset to the linear projection, and in short, the linear projection, that is, a straight line in a scene projected onto a picture also remains as a straight line, but the distortion is an optical distortion, which may be caused by a lens, that a straight line projected onto a picture cannot remain as a straight line. The distortion includes linear distortion and nonlinear distortion, the former includes perspective distortion and the like, and the latter includes radial distortion, tangential distortion, thin prism distortion and the like. Radial distortion refers to the movement of a given image point inward or outward from its ideal position, which is mainly caused by the imperfections in the change of curvature of the lens surface portions in the radial direction, negative radial displacement of the image point is so-called barrel distortion, which causes the laterally located edge points to be more crowded and the imaging fraction to be reduced, while positive radial displacement is called pincushion distortion, which causes the laterally located points to be relatively more diffuse and the imaging fraction to be increased, radial distortion only produces radial deviations, and rays to be deflected more away from the center of the lens. Tangential distortion, which is mainly caused by the lens not being perfectly parallel to the image plane, and thin prism distortion, both produce radial and tangential deviations. The cause of the distortion of the thin prism is mainly caused by defects in the lens design and production and camera assembly processes, such as a slight inclination of the image sensing array or the lens portion.

2. Internal and external parameters and distortion parameters: when a sensor (sensor) and a lens of a set of camera or a video camera are fixed, internal and external parameters and distortion parameters of an image are fixed, so that the mapping of each frame of output image calculated by an image correction algorithm to the coordinate position of an input image is determined.

At present, in a scene that an image shot by a super-wide angle distortion lens has image distortion, a processor reads out corresponding image data in a DDR (digital data Rate) stored distortion image point by point to perform data interpolation, so that the distortion correction of the image is completed. Because one point is output in each interpolation, the processor is required to acquire image data in a corresponding distorted image in each interpolation from the DDR, so that the interaction times of the processor and the DDR depend on the size of the output image, and when the size of the output image is larger, the algorithm correction speed is reduced due to frequent interaction with the DDR.

In order to solve the problems, the application provides an image distortion correction method, by calculating at least one distortion coordinate of a sequence block in a distorted image, image data in the range of the at least one distortion coordinate can be loaded from a DDR at one time, interaction times with the DDR in the image distortion correction process are reduced, image data are loaded from the DDR to an SRAM through a ping-pong mechanism to perform distortion correction, the efficiency of accessing the DDR by an algorithm is improved, and the correction speed of an image distortion correction algorithm is further improved.

Referring to fig. 1, fig. 1 is a schematic view of a scene in which a distorted image is subjected to distortion correction processing in an image capturing apparatus according to an embodiment of the present disclosure. As shown in fig. 1, the sensor 100 acquires an image captured by the lens 200, and then the sensor 100 processes and outputs the pre-correction image to the DDR 300 for storage. When the processor 400 processes the pre-correction image, the processor 400 reads the image data corresponding to the preset sequence block from the DDR 300 into the SRAM 500 according to the mapping relationship between the output image and the coordinate position of the input image, and the image distortion correcting device 411 in the processor 400 performs distortion correction processing on the image data in the SRAM 500 and outputs a distortion-free corrected image, thereby completing the distortion correction of the image.

Further, when the image distortion correction device 411 performs distortion correction processing on the image data in the SRAM 500, the processor may simultaneously read the image data corresponding to the preset sequence block from the DDR 300 into the SRAM 500, so that the image distortion correction device 411 can continuously perform distortion correction processing on the image before correction, thereby reducing the time for the processor to read the data from the DDR, and further improving the correction speed of the image distortion correction algorithm.

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 2, fig. 2 is a flowchart illustrating an image distortion correction method according to an embodiment of the present application, applied to the wireless communication system shown in fig. 1. As shown in fig. 2, the method includes the following steps.

S210, calculating at least one first distortion coordinate, wherein each first distortion coordinate is a coordinate of one first sequence block in a distorted image, and the distorted image is stored in the DDR.

Wherein, in order to reduce the number of interactions with the DDR, the processor can calculate the first distortion coordinate of the first sequence block in the distorted image according to the size of the first sequence block, so that the processor can load the image data in the first distortion coordinate range from the DDR at one time. The first sequence block may be predetermined, for example, the size of the first sequence block may be 8 × 8 matrix block, 16 × 16 matrix block; the first sequence block may also be determined according to a distortion degree of a distorted image, which is not limited in the embodiment of the present application.

Further, the first distortion coordinate is a coordinate of a corresponding point of the boundary of the first sequence block on the distorted image calculated by the processor according to the calibrated coordinate. After the image pickup device and the lens are fixed, the internal and external parameters and the distortion parameters of the image are also fixed, so that the processor can determine the coordinate position of each frame of output image (corrected image) mapped to the input image (distorted image) according to the internal and external parameters and the distortion parameters, and further calculate the first distortion coordinate of the first sequence block.

Optionally, the first distorted coordinate includes a first coordinate and a second coordinate; the calculating at least one first distortion coordinate comprises: calculating at least one offset set based on the size and distortion parameters of the output image, wherein each offset set is a set of offset values of boundary points of the first sequence blocks on the output image and the distorted image; determining at least one set of position coordinates based on the at least one set of offsets, each set of position coordinates being a set of a plurality of position coordinates of boundary points of one of the first sequence of blocks on the distorted image; sorting the coordinates in each position coordinate set, and determining the minimum circumscribed quadrangle of each position coordinate set; acquiring the first coordinate and the second coordinate of each minimum enclosing quadrangle.

In this application, the processor may divide the output image into a plurality of first sequence blocks with the same size, and then map the plurality of output image blocks into the input image according to the calibrated coordinates (the internal and external parameters and the distortion parameters), to obtain the coordinate positions of a plurality of input image blocks, where the output image blocks are the sequence blocks of the first sequence blocks in the corrected image, and the input image blocks are the blocks of the output image blocks mapped into the input image. Specifically, a block table and a coordinate table can be determined through camera equipment calibration, wherein the block table comprises the initial address of an input image block, the block height and the block width; the coordinate table comprises a mapping coordinate relation of the input image and the output image, and the mapping coordinate relation of the input image and the output image comprises row and column addresses of the input image block, row and column addresses of the output image block, row and column coordinates of pixel points in the input image block, row and column coordinates of pixel points in the output image block and the like. Then dividing the output image into a plurality of first sequence blocks with the same size, and mapping the output image block to the input image according to a coordinate table to obtain a plurality of input image blocks; recording the size and the first address of each input image block by using a block table; and mapping each pixel point in the output image block to a pixel point corresponding to the input image according to the block table and the coordinate table.

In particular, the processor may divide the rectified image from left to right and from top to bottom into at least one first sequence of blocks. And calculating the offset of the boundary point of each first sequence block mapped to the corresponding point in the distorted image according to the distortion parameter and the internal and external parameters to obtain a plurality of offset sets. And then calculating coordinates of the boundary point of each first sequence block mapped to the distorted image according to the offset set of each first sequence block to obtain a coordinate set corresponding to each sequence block. The shape of the first sequence of blocks mapped into the distorted image is thus available. Since the distorted image has distortion, the shape of the image block obtained by mapping the first sequence of blocks into the distorted image may be different from the shape of the first sequence of blocks. For example, the first sequence block is an 8 × 8 matrix block, and the mapped image blocks may be in an elliptical shape or an irregular shape, so that the coordinates in the coordinate set are sorted according to the size of the coordinate position, and the minimum circumscribed quadrangle of each image block is found. And finally, taking the vertex of the minimum circumscribed quadrangle as a first distortion coordinate, and storing the first distortion coordinate.

For example, as shown in fig. 3, the first sequence block is an 8 × 8 matrix block, and the corrected image is a 32 × 128 matrix block, and the processor maps 8 sequentially arranged first sequence blocks into the distorted image at a time, resulting in an image block as in (b) of fig. 3. Wherein the overlapping portions between the image blocks in the distorted image indicate that the portion is distorted.

The first coordinate and the second coordinate may be diagonal vertices of a minimum circumscribed quadrangle, respectively. For example, the first coordinate is the upper left corner of the minimum circumscribed quadrangle, the second coordinate is the lower right corner of the minimum circumscribed quadrangle, or the first coordinate is the lower left corner of the minimum circumscribed quadrangle, the second coordinate is the upper right corner of the minimum circumscribed quadrangle, or the first coordinate is the upper right corner of the minimum circumscribed quadrangle, the second coordinate is the lower left corner of the minimum circumscribed quadrangle, or the first coordinate is the lower right corner of the minimum circumscribed quadrangle, and the second coordinate is the upper left corner of the minimum circumscribed quadrangle.

S220, loading first image data in the distorted image into a first Static Random Access Memory (SRAM) based on the at least one first distortion coordinate, wherein the first image data is image data in the range of the at least one first distortion coordinate.

After the first distortion coordinate corresponding to each first sequence block is calculated, in order to reduce the number of times of interaction between the processor and the DDR, the processor may directly load all image data (i.e., first image data) in a plurality of distortion coordinate ranges into the first SRAM, so that the processor may directly read from the first SRAM when performing image distortion correction, thereby reducing the reading time of the image data.

Optionally, the loading, based on the at least one first distortion coordinate, first image data in the distorted image to a first static random access memory SRAM includes: calculating a starting row-column coordinate and a stopping row-column coordinate of each first sequence block in the distorted image based on the first coordinate and the second coordinate; and loading image data corresponding to each starting row-column coordinate to the ending row-column coordinate in the distorted image from the DDR to the first SRAM.

Specifically, an initial row coordinate, a cut-off row coordinate, an initial column coordinate and a cut-off column coordinate corresponding to each image block can be obtained through calculation according to the first distortion coordinate of each image block, the initial row coordinate, the cut-off row coordinate and the cut-off column coordinate are respectively sequenced, the initial row coordinate and the cut-off row coordinate of the first image data are calculated, and the corresponding image data are loaded into the first SRAM from the DDR according to the specific initial column coordinate and the cut-off column coordinate in each row and stored. For example, for a plurality of image blocks in (b) of fig. 3, initial row coordinates and end row coordinates of 8 image blocks in the figure are calculated as (24, 0) and (31,0), and then image data of a gray portion in the figure is loaded into the SRAM from the DDR in accordance with the initial column coordinates and the end column coordinates of each of the 23 th to 32 th rows.

S230, distortion correction processing is carried out on the first image data, at least one second distortion coordinate is calculated at the same time, each second distortion coordinate is a coordinate of one second sequence block in a distorted image, and second image data in the distorted image is loaded into a second SRAM based on the at least one second distortion coordinate, wherein the second image data is image data in the range of the at least one second distortion coordinate.

The processor may read the first image data from the first SRAM, perform an interpolation operation on the first image data, and then output a pixel value and a coordinate interpolated for each image block, thereby obtaining a corrected image. The Interpolation operation may be an Interpolation algorithm in the prior art, such as Nearest neighbor Interpolation (Nearest neighbor Interpolation), bilinear Interpolation, bicubic Interpolation, Lanczos Interpolation, and the like, which is not described herein again.

In this application, when the processor performs distortion correction processing on the first image, at least one second distortion coordinate may be calculated at the same time, and second image data corresponding to the at least one second distortion coordinate is loaded into the second SRAM, where a specific implementation of calculating the second distortion coordinate may refer to a calculation process of the first distortion coordinate, and a specific implementation of loading the second image data into the second SRAM may refer to a loading process of the first image data, which is not described herein again. For example, as shown in fig. 3, when the processor performs an interpolation operation on the first image data in the graph, the processor may simultaneously calculate a second distortion coordinate at which the second sequence of blocks in the remaining output image is mapped into a distorted image.

The calculation speed of the distorted coordinates is high, and after the calculation of the second distorted coordinates is finished, the first SRAM may still be called by the processor, so that the second image data corresponding to the second distorted coordinates can be loaded into another memory space in the SRAM.

In this embodiment of the present application, the second sequence of blocks is located in the remaining image portion of the corrected image, and the size of the second sequence of blocks may be the same as the size of the first sequence of blocks, specifically, the corrected image is divided into image blocks with the same size to perform image correction based on a ping-pong mechanism; the size of the second sequence block may also be different from the size of the first sequence block, for example, the size of the second sequence block may be determined according to the distortion degree of the distorted image, which is not limited in this embodiment of the application.

The first SRAM is configured to store first image data, the second SRAM is configured to store second image data, and the first SRAM is configured to store third image data corresponding to a third sequence block after the distortion correction processing of the first image data is completed. Illustratively, the processor may also partition a third SRAM to store the third image data. The first SRAM and the second SRAM may be different memory blocks divided in the SRAM or memory addresses with different first addresses in the SRAM, which is not limited herein in this embodiment of the application.

Optionally, after the first image data is subjected to the distortion correction processing, the second image data is subjected to the distortion correction processing.

In the specific implementation, after the first image data is subjected to the distortion correction processing, the processor can immediately call the second image data in the second SRAM to perform the distortion correction processing, so that the time for accessing the image data in the DDR is saved, and the speed of image distortion correction can be effectively increased.

Optionally, the method further includes: when distortion correction processing is carried out on the second image data, at least one third distortion coordinate is calculated at the same time, each third distortion coordinate is the coordinate of one third sequence block in the distorted image, and the third image data in the distorted image is loaded into the first SRAM or the third SRAM based on the at least one third distortion coordinate, wherein the third image data is the image data within the range of the at least one third distortion coordinate.

In this embodiment, the processor may map the sequence blocks in the corrected image into the distorted image sequentially from left to right and from top to bottom, so as to perform the distortion correction processing on the image data in the distorted image, and thus when performing the distortion correction processing on the second image data, the processor may simultaneously calculate at least one third distortion coordinate and load the third image data in the distorted image into the first SRAM or a third SRAM, where the third sequence block may be the same as or different from the first sequence block and/or the second sequence block. For example, as shown in fig. 4, the processor first calculates a first distortion coordinate corresponding to the first sequence block, and loads first image data in a first distortion coordinate range from the DDR into the first SRAM; then the processor calls the first SRAM to perform distortion correction processing, calculates a second distortion coordinate corresponding to the second sequence block, and loads second image data in the second distortion coordinate range into the second SRAM from the DDR; and after the first image data is subjected to distortion correction, immediately calling a second SRAM by the processor to perform distortion correction, simultaneously calculating a third distortion coordinate corresponding to a third sequence block by the processor, loading the third image data in a third distortion coordinate range into the third SRAM or the first SRAM from the DDR, and sequentially circulating until the distortion correction of the distorted image of the whole frame is completed.

Optionally, the method further includes: and outputting a corrected image corresponding to the distorted image after the second image data is subjected to distortion correction processing.

Specifically, when the second image data is the last image data that is not corrected in the distorted image, after the distortion correction processing of the second image data is completed, all data output after the distortion correction of the distorted image can be spliced to obtain a corrected image after the distortion correction of the distorted image.

The method comprises the steps of calculating at least one first distortion coordinate, wherein each first distortion coordinate is a coordinate of a first sequence block in a distorted image, and the distorted image is stored in a DDR (double data rate); loading first image data in the distorted image into a first SRAM based on the at least one first distortion coordinate; and carrying out distortion correction processing on the first image data, calculating at least one second distortion coordinate, and loading the second image data in the distorted image into a second SRAM. According to the method and the device, at least one distortion coordinate of the sequence block in the distortion image is calculated, so that image data in the range of the at least one distortion coordinate can be loaded from the DDR at one time, the interaction times with the DDR in the image distortion correction process are reduced, the image data are loaded into the SRAM from the DDR through a ping-pong mechanism to be subjected to distortion correction, the efficiency of accessing the DDR by an algorithm is improved, and the correction speed of the image distortion correction algorithm is further improved.

The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It is understood that the network device comprises corresponding hardware structures and/or software modules for performing the respective functions in order to realize the above functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software implementing the various illustrative elements and algorithm steps described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

Referring to fig. 5a, fig. 5a is a block diagram illustrating functional units of an apparatus 500 for correcting image distortion according to an embodiment of the present application, where the apparatus 500 is applied to an electronic device, and the apparatus 500 includes: a calculation unit 510, a loading unit 520, and a rectification unit 530, wherein,

a calculating unit 510, configured to calculate at least one first distortion coordinate, where each first distortion coordinate is a coordinate of one first sequence block in a distorted image stored in the DDR;

a loading unit 520, configured to load, based on the at least one first distortion coordinate, first image data in the distorted image into a first static random access memory SRAM, where the first image data is in a range of the at least one first distortion coordinate;

the correcting unit 530 is configured to perform distortion correction processing on the first image data, and simultaneously calculate at least one second distortion coordinate, where each second distortion coordinate is a coordinate of one second sequence block in a distorted image, and load the second image data in the distorted image into a second SRAM based on the at least one second distortion coordinate, where the second image data is image data within a range of the at least one second distortion coordinate.

Optionally, the correcting unit 530 is further configured to: and after the first image data is subjected to distortion correction processing, performing distortion correction processing on the second image data.

Optionally, the calculating unit 510 is further configured to: when distortion correction processing is carried out on the second image data, at least one third distortion coordinate is calculated simultaneously, wherein each third distortion coordinate is the coordinate of a third sequence block in the distorted image and is based on the at least one third distortion coordinate; the loading unit 520 is further configured to: and loading third image data in the distorted image into the first SRAM or a third SRAM, wherein the third image data is image data within a range of the at least one third distorted coordinate.

Optionally, as shown in fig. 5b, the functional units of another image distortion correcting apparatus 500 provided in the embodiment of the present application form a block diagram, where the apparatus 500 further includes an output unit 540, and the output unit 540 is configured to: and outputting a corrected image corresponding to the distorted image after the second image data is subjected to distortion correction processing.

Optionally, the first distorted coordinate includes a first coordinate and a second coordinate;

in respect of calculating the at least one first distortion coordinate, the calculation unit is specifically configured to: calculating at least one offset set based on the size and distortion parameters of the output image, wherein each offset set is a set of offset values of boundary points of the first sequence blocks on the output image and the distorted image; determining at least one set of position coordinates based on the at least one set of offsets, each set of position coordinates being a set of a plurality of position coordinates of boundary points of one of the first sequence of blocks on the distorted image; sorting the coordinates in each position coordinate set, and determining the minimum circumscribed quadrangle of each position coordinate set; acquiring the first coordinate and the second coordinate of each minimum enclosing quadrangle.

Optionally, in respect of loading the first image data in the distorted image to the first static random access memory SRAM based on the at least one first distortion coordinate, the loading unit 520 is specifically configured to: calculating a starting row-column coordinate and a stopping row-column coordinate of each first sequence block in the distorted image based on the first coordinate and the second coordinate; and loading image data corresponding to each starting row-column coordinate to the ending row-column coordinate in the distorted image from the DDR to the first SRAM.

It should be appreciated that the apparatus 500 herein is embodied in the form of a functional unit. The term "unit" herein may refer to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (e.g., a shared, dedicated, or group processor) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that support the described functionality. In an optional example, it may be understood by those skilled in the art that the apparatus 500 may be embodied as an electronic device in the foregoing embodiment, and the apparatus 500 may be configured to perform each process and/or step corresponding to the electronic device in the foregoing method embodiment, and in order to avoid repetition, details are not described here again.

The apparatus 500 of each of the above aspects has functions of implementing corresponding steps executed by the electronic device in the above method; the functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software comprises one or more modules corresponding to the functions; for example, the computing unit 510 and the rectifying unit 530 may be replaced by a processor, and perform the transceiving operation and the related processing operation in each method embodiment, respectively.

In an embodiment of the present application, the apparatus 500 may also be a chip or a chip system, for example: system on chip (SoC). Correspondingly, the computing unit may be a computing circuit of the chip, and is not limited herein.

Referring to fig. 6, fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure, where the electronic device includes: one or more processors, one or more memories, one or more communication interfaces, and one or more programs; the one or more programs are stored in the memory and configured to be executed by the one or more processors.

The program includes instructions for performing the steps of:

All relevant contents of each scene related to the method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.

It will be appreciated that the memory described above may include both read-only memory and random access memory, and provides instructions and data to the processor. The portion of memory may also include non-volatile random access memory. For example, the memory may also store device type information.

In the embodiment of the present application, the processor of the above apparatus may be a Central Processing Unit (CPU), and the processor may also be other general processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It is to be understood that reference to "at least one" in the embodiments of the present application means one or more, and "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

And, unless stated to the contrary, the embodiments of the present application refer to the ordinal numbers "first", "second", etc., for distinguishing a plurality of objects, and do not limit the sequence, timing, priority, or importance of the plurality of objects. For example, the first information and the second information are different information only for distinguishing them from each other, and do not indicate a difference in the contents, priority, transmission order, importance, or the like of the two kinds of information.

In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software elements in a processor. The software elements may be located in ram, flash, rom, prom, or eprom, registers, among other storage media that are well known in the art. The storage medium is located in a memory, and a processor executes instructions in the memory, in combination with hardware thereof, to perform the steps of the above-described method. To avoid repetition, it is not described in detail here.

Embodiments of the present application also provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any one of the methods as described in the above method embodiments.

Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially or partially contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a TRP, etc.) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash disk, ROM, RAM, magnetic or optical disk, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A method for image distortion correction, the method comprising:

2. The method of claim 1, further comprising:

and after the first image data is subjected to distortion correction processing, performing distortion correction processing on the second image data.

3. The method of claim 2, further comprising:

when distortion correction processing is carried out on the second image data, at least one third distortion coordinate is calculated at the same time, each third distortion coordinate is the coordinate of one third sequence block in the distorted image, and the third image data in the distorted image is loaded into the first SRAM or the third SRAM based on the at least one third distortion coordinate, wherein the third image data is the image data within the range of the at least one third distortion coordinate.

4. The method of claim 2, further comprising:

and outputting a corrected image corresponding to the distorted image after the second image data is subjected to distortion correction processing.

5. The method of any of claims 1-4, wherein the first distortion coordinate comprises a first coordinate and a second coordinate;

the calculating at least one first distortion coordinate comprises:

calculating at least one offset set based on the size and distortion parameters of the output image, wherein each offset set is a set of offset values of boundary points of the first sequence blocks on the output image and the distorted image;

determining at least one set of position coordinates based on the at least one set of offsets, each set of position coordinates being a set of a plurality of position coordinates of boundary points of one of the first sequence of blocks on the distorted image;

sorting the coordinates in each position coordinate set, and determining the minimum circumscribed quadrangle of each position coordinate set;

acquiring the first coordinate and the second coordinate of each minimum enclosing quadrangle.

6. The method of claim 5, wherein the loading first image data in the distorted image to a first Static Random Access Memory (SRAM) based on the at least one first distortion coordinate comprises:

calculating a starting row-column coordinate and a stopping row-column coordinate of each first sequence block in the distorted image based on the first coordinate and the second coordinate;

and loading image data corresponding to each starting row-column coordinate to the ending row-column coordinate in the distorted image from the DDR to the first SRAM.

7. An image distortion correction apparatus, comprising:

8. An electronic device, comprising a processor, memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-6.

9. A chip system, the chip system comprising at least one processor, a memory and an interface circuit, the memory, the transceiver and the at least one processor being interconnected by a line, the at least one memory having a computer program stored therein; the computer program, when executed by the processor, implements the method of any of claims 1-6.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program causes a computer to perform the steps of the method according to any one of claims 1-6.