CN112835840B

CN112835840B - Serial communication system

Info

Publication number: CN112835840B
Application number: CN202110174443.2A
Authority: CN
Inventors: 王辉华; 邓知先; 谭成午
Original assignee: Shenzhen Invt Transportation Technology Co ltd
Current assignee: Shenzhen Invt Transportation Technology Co ltd
Priority date: 2021-02-07
Filing date: 2021-02-07
Publication date: 2024-06-04
Anticipated expiration: 2041-02-07
Also published as: CN112835840A

Abstract

The application discloses a serial communication system, which comprises a master device and a slave device; the master equipment and the slave equipment both adopt a CPU+FPGA structure, wherein the FPGA is connected with the corresponding CPU in an analog RAM interface mode to realize the communication in the equipment; the FPGA of the master device and the FPGA of the slave device are connected with each other in an analog SPI serial interface mode to realize master-slave communication between the devices. The CPU is operated and controlled by adopting a bus access RAM mode, the effect of sharing the dual-port RAM is realized based on the FPGA of the master-slave equipment, the wiring is simple, the remote communication is suitable, the communication speed is high, the efficiency is high, the protocol is simple, the CPU occupancy rate is effectively reduced, and the communication instantaneity, the bandwidth utilization rate and the anti-interference capability are improved.

Description

Serial communication system

Technical Field

The present application relates to the field of data communication technologies, and in particular, to a serial communication system.

Background

Communication is required when the devices cooperate. For example, between the host controller and the execution unit, control commands need to be communicated to the execution unit in real time, while status information needs to be fed back to the host controller quickly. The communication between the devices is usually realized by bus mode, such as 232, 485, CAN, ethernet, etc., and the interfaces thereof are generally hardware resources of CPU in the devices. Therefore, the CPU needs to spend a lot of running time for management, and the implementation process of the whole communication protocol is complex, so that the real-time performance of the communication data and the bus bandwidth utilization are difficult to control.

In view of this, it has been a great need for a person skilled in the art to provide a solution to the above-mentioned technical problems.

Disclosure of Invention

The application aims to provide a serial communication system so as to effectively improve the real-time performance and the bandwidth utilization rate of data communication.

In order to solve the technical problems, the application discloses a serial communication system, which comprises a master device and a slave device:

the master device and the slave device both adopt a CPU+FPGA structure, wherein the FPGA is connected with the corresponding CPU through an analog RAM interface mode to realize the communication in the device; and the FPGA of the master equipment and the FPGA of the slave equipment are mutually connected in an SPI (serial peripheral interface) simulation mode to realize master-slave communication between the equipment.

Optionally, a frame type definition word is included in a communication data frame sent by the master device to the slave device, and the frame type definition word is used for specifying the information type of the current communication data frame;

Wherein, different information types correspond to different buffer areas, so that the slave device can read and write data for the buffer areas corresponding to the frame type definition words when responding to the master device.

Optionally, the different information types correspond to different priorities, so that when the master device sends the communication data frame to the slave device, the communication data frame to be sent with the highest current priority is specifically sent to the slave device.

Optionally, the information type includes at least one of:

The system comprises a real-time control frame, a periodic control information refreshing frame, a designated address information reading frame, a parameter reading and writing frame, a fast state information reading frame, a slow state information reading frame, a slave machine request response frame and other appointed information reading frames.

Optionally, the FPGA of the master device is specifically configured to, when sending a communication data frame to the slave device:

The corresponding communication data frames are sent at regular time according to a preset sending period; and after the CPU of the master device writes a transmission request mark into the RAM specific address of the FPGA, transmitting a communication data frame appointed by the CPU.

Optionally, the SPI serial interface between the master device and the slave device is connected through an optical fiber.

Optionally, in the master device and the slave device, a data connection line between the CPU and the FPGA includes an address line, a data line, and a control line; the data connection line between the FPGA of the master device and the FPGA of the slave device comprises a clock signal line, a master device transmission line and a slave device transmission line.

Optionally, the master device and the slave device perform SPI serial communication, specifically, reading on a rising edge of a clock signal and writing on a falling edge of the clock signal.

Optionally, a start bit and an end bit are included in the communication data frame between the master device and the slave device;

the start bit is 2 low levels and 1 high level which continuously appear in the clock signal; the end bit is 1 low level for 2 high levels continuously occurring in the clock signal.

Optionally, the frame format of the communication data frame sent by the master device to the slave device is:

start bit + frame type definition word + key control command word + classification packet + check word + end bit;

The frame format of the communication data frame sent from the slave device to the master device is as follows:

start bit + request return frame length + key status information word + classification information reply packet + check word + end bit.

The serial communication system provided by the application has the beneficial effects that: the CPU is operated and controlled by adopting a bus access RAM mode, the effect of sharing the dual-port RAM is realized based on the FPGA of the master-slave equipment, the wiring is simple, the remote communication is suitable, the communication speed is high, the efficiency is high, the protocol is simple, the CPU occupancy rate is effectively reduced, and the communication instantaneity, the bandwidth utilization rate and the anti-interference capability are improved.

Drawings

In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the following will briefly describe the drawings that need to be used in the description of the prior art and the embodiments of the present application. Of course, the following drawings related to embodiments of the present application are only a part of embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any inventive effort, and the obtained other drawings also fall within the scope of the present application.

Fig. 1 is a block diagram of a serial communication system according to an embodiment of the present application;

fig. 2 is a schematic diagram of a format of a communication data frame according to an embodiment of the present application;

fig. 3 is a schematic diagram of a data transceiving flow of a master device according to an embodiment of the present application;

fig. 4 is a schematic diagram of a data transceiving flow of a slave device according to an embodiment of the present application;

fig. 5 is a flowchart of a master device generating a frame type definition word according to an embodiment of the present application.

Detailed Description

The core of the application is to provide a serial communication system so as to effectively improve the real-time performance and bandwidth utilization rate of data communication.

In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Referring to fig. 1, the embodiment of the application discloses a serial communication system, which comprises a master device and a slave device;

The master equipment and the slave equipment both adopt a CPU+FPGA structure, wherein the FPGA is connected with the corresponding CPU in an analog RAM interface mode to realize the communication in the equipment; the FPGA of the master device and the FPGA of the slave device are connected with each other in an analog SPI serial interface mode to realize master-slave communication between the devices.

Specifically, the CPUs (Central Processing Unit, central Processing units) in the master device and the slave device can be specifically realized based on control chips such as an ARM single-chip microcomputer or a DSP (DIGITAL SIGNAL Processing), and the like, and the serial communication between the master device and the slave device is completed by combining the matched use of the FPGA (Field Programmable GATE ARRAY ).

In the master device and the slave device, a block of RAM space is created in the FPGA, and is connected with the CPU in a RAM interface mode, and the CPU can access the RAM through an address data bus. In addition, the FPGA also simulates an SPI interface, and the two FPGAs realize the exchange and synchronization of RAM data between two devices through the communication of the SPI serial interface.

Therefore, the FPGA and the CPU perform data reading and writing in an analog RAM interface mode, the master equipment and the slave equipment are in communication through an FPGA analog SPI serial interface, and after communication data are processed and managed by the FPGA, the effect of sharing the dual-port RAM is achieved between the two CPUs.

It should be noted that sharing a dual-port RAM can directly exchange data, which is the fastest and effective communication mode between two CPUs. In the conventional technology, two CPUs are required to be connected with address lines, data lines, control lines and the like between the dual-port RAM chips respectively, so that the two CPUs are required to be physically connected on the same board or through a backboard bus, the cost is high, and the application limitation is also high. The application achieves the effect of sharing the dual-port RAM through the two FPGAs, avoids complex wiring, simplifies wiring structure and improves anti-interference performance. And more importantly, the problems of high CPU occupation rate and low communication efficiency in the traditional communication can be solved.

Specifically, in one embodiment, based on the above content, the serial communication system provided in the embodiment of the present application, in the master device and the slave device, a data connection line between the CPU and the FPGA includes an address line, a data line, and a control line; the data connection line between the FPGA of the master device and the FPGA of the slave device comprises a clock signal line, a master device transmission line and a slave device transmission line.

Further, in one embodiment, the SPI serial interface between the master device and the slave device may be specifically connected by an optical fiber. By adopting optical fiber communication, the influence of environmental distance can be avoided, the problem that the transmission distance is limited in the traditional dual-port RAM communication mode is solved, and the communication applicability and the anti-interference capability are further improved.

Therefore, the serial communication system provided by the application is operated and controlled by the CPU in a bus access RAM mode, realizes the effect of sharing the dual-port RAM based on the FPGA of the master-slave device, has simple wiring, is suitable for long-distance communication, has high communication speed, high efficiency and simple protocol, effectively reduces the CPU occupancy rate, and improves the communication instantaneity, the bandwidth utilization rate and the anti-interference capability.

As a specific embodiment, in the serial communication system provided by the embodiment of the present application, on the basis of the foregoing, a frame type definition word is included in a communication data frame sent from a master device to a slave device, where the frame type definition word is used to specify an information type of a current communication data frame;

Specifically, in this embodiment, a frame type definition word for indicating the type of information classification is introduced into a communication data frame, and according to a protocol of a predetermined command word, the FPGA of the master device locates a data transmission address according to the frame type definition word, and the slave device immediately parses after receiving the frame type definition word, and sets a data transceiving address pointer. Therefore, the application can ensure that different types of information are stored in the preset storage area, and effectively improves the communication efficiency by carrying out partition processing on the different types of information.

For example, as a specific embodiment, in the serial communication system provided by the embodiment of the present application, on the basis of the foregoing, the information types may specifically include at least one of the following:

As a specific embodiment, in the serial communication system provided by the embodiment of the present application, on the basis of the foregoing, different information types correspond to different priorities, so that when the master device sends a communication data frame to the slave device, the master device specifically sends the communication data frame to be sent with the highest current priority to the slave device.

Specifically, in order to perform scientific and orderly processing on different types of information, the present embodiment sets different processing priorities for different types of communication data frames. After one frame of information is sent out, the FPGA inquires the priority of each communication data frame to be sent again so as to send according to the arrangement of the data priority. Wherein the communication data frame to be transmitted may be identified by setting a corresponding transmission request flag. Based on the setting and the use of the priority, the real-time performance and the bandwidth utilization rate of the communication can be further improved.

As a specific embodiment, in the serial communication system provided by the embodiment of the present application, based on the above, the FPGA of the master device is specifically configured to:

The corresponding communication data frames are sent at regular time according to a preset sending period; and after the CPU of the main device writes a transmission request mark into the RAM specific address of the FPGA, transmitting a communication data frame appointed by the CPU.

Specifically, this embodiment sets two initiation manners of communication data frames. For the fixed information needing to be periodically sent, the information can be initiated by the FPGA at self-timing; for some temporary or urgent information, the CPU may write a corresponding transmission request flag at a specific address in the RAM so that the FPGA initiates an information transmission operation after reading.

Referring to fig. 2, fig. 2 is a schematic diagram of a format of a communication data frame according to an embodiment of the present application. Where CLK is the clock signal, MOSI is the master (master) send signal, MISO is the slave (slave) send signal.

Specifically, the clock signal may be generated by the master device, and the baud rate is agreed according to the hardware capability, and for example, the communication speed is typically 5Mbps, which is an example of ordinary optical fiber communication. The clock signal is output at a fixed level during the non-communication period, and the clock signal is output during the communication period.

In a specific embodiment, the serial communication system provided by the embodiment of the application is based on the above content, and when the master device and the slave device perform SPI serial communication, the master device and the slave device specifically perform SPI serial communication on rising edge reading and falling edge writing of a clock signal. The data byte is sent with the high order preceding and the low order following.

As a specific embodiment, in the serial communication system provided by the embodiment of the present application, on the basis of the above content, a start bit and an end bit are included in a communication data frame between a master device and a slave device; the start bit is 2 low levels and 1 high level which continuously appear in the clock signal; the end bit is 1 low level for 2 high levels that continuously occur in the clock signal. Wherein the end bit may also be referred to as a stop bit. Of course, those skilled in the art may design and use other types of start bits and end bits, which are not limited in this regard.

As a specific embodiment, in the serial communication system provided by the embodiment of the present application, based on the above, a frame format of a communication data frame sent from a master device to a slave device is:

The frame format of the communication data frame sent from the slave device to the master device is:

The purpose of the check word is to check whether the received data is correct, if so, a new data valid flag is set, and the CPU processes the data after receiving the valid flag.

In this embodiment, the data transceiving flow of the master device may specifically refer to fig. 3. Specifically, once a transmission task is required, the master device firstly sets a receiving and transmitting address according to the information type, automatically generates a check word in the transmission process, and effectively sets a data receiving flag bit only when the check is passed for the returned communication data frame. The process specifically comprises the following steps:

S101: judging whether a communication data frame to be transmitted currently exists or not according to the request transmission mark; if yes, enter S102; if not, the process returns to S101.

S102: the transmission buffer address and the reception deposit address are set based on a frame type definition word in the communication data frame.

S103: the start bit is sent.

S104: and sending a frame type definition word, and receiving a request backhaul frame length sent by the slave device.

S105: and sending the key control command word and receiving the key state information word sent by the slave device.

S106: transmitting a classification information packet and receiving a classification information response packet transmitted by the slave device; and calculates a check word.

S107: and sending the check word calculated by the self, and receiving the check word sent by the slave equipment.

S108: judging whether the verification result is normal; if yes, go to S109; if not, the process proceeds to S110.

S109: effectively setting the corresponding data receiving zone bit; proceed to S110.

S110: a stop bit is sent.

Correspondingly, the data transceiving flow of the slave device can refer to fig. 4 in particular. Specifically, the request backhaul frame length refers to the data length required to be read by the master device when the slave device has a new data packet, the data processing request flag is placed in the key state information word, and the slave device effectively sets the data processing request flag only after the received communication data frame passes the verification. The process specifically may include:

s201: judging whether a start bit appears in the clock signal; if yes, go to S202; if not, return to S201.

S202: transmitting request back frame length; the process advances to S203.

S203: judging whether the frame type definition word is received completely or not; if yes, go to S204; if not, return to S202.

S204: the transmission buffer address and the reception deposit address are set according to the frame type definition word.

S205: a control command word is received and a key status information word is returned.

S206: and receiving the classified information packet and returning a classified information response packet.

S207: and receiving the check word sent by the master device.

S208: judging whether the verification is passed or not; if yes, go to S209; if not, the process proceeds to S210.

S209: and effectively setting a corresponding data processing request mark.

S210: and ending the data transmission.

In one embodiment, the disclosed serial communication system may be particularly applicable in a subway traction inverter. The main equipment can be a System Controller (SCU) and consists of an ARM single-chip microcomputer and an FPGA; while the slave device may be embodied as a motor controller (PCU) consisting of a DSP and an FPGA. The SCU is responsible for vehicle control logic, outputting control instructions required for operation to the PCU in real time, receiving PCU state feedback, reading and writing PCU parameters, periodically reading PCU key signals (a fast-change signal is defined as 2ms, a slow-change signal is defined as 10 ms), and monitoring waveforms (sending offset addresses of monitoring signals selected by a user, then receiving feedback values of the selected signals at 4000 times per second and outputting the signals in a oscillometric mode).

In one embodiment, the processing priorities corresponding to the information of several common functions may be, in order from high to low: transmitting control command, reading and writing parameters, returning parameters, reading waveforms, and reading fault information (fault related information). When information of a certain function needs to be sent, the corresponding flag bit is effectively set.

As such, the process of generating the frame type definition word by the master device may be seen in fig. 5, including:

S301: the master device judges whether data is currently being transmitted; if yes, returning to S301 for waiting; if not, the process proceeds to S302.

S302: judging whether a control command sending flag bit is effectively set; if not, enter S303; if yes, the process proceeds to S308.

S303: judging whether the parameter read-write flag bit is effectively set; if not, entering S304; if yes, the process proceeds to S308.

S304: judging whether the parameter return flag bit is effectively set; if not, then enter S305; if yes, the process proceeds to S308.

S305: judging whether the waveform reading flag bit is effectively set; if not, enter S307; if yes, the process proceeds to S306.

S306: judging whether a waveform signal reading period is reached; if not, enter S307; if yes, the process proceeds to S308.

S307: judging whether the information flag bit for faults is effectively set; if yes, the process proceeds to S308.

S308: and generating and transmitting a corresponding frame type definition word.

The fault information can be related information for fault analysis, and can be received and displayed at 1000 times of frequency, and the priority of the fault information is lower than that of the waveform signal received at 4000 times of frequency.

In the application, each embodiment is described in a progressive manner, and each embodiment is mainly used for illustrating the difference from other embodiments, and the same similar parts among the embodiments are mutually referred. For the apparatus disclosed in the examples, since it corresponds to the method disclosed in the examples, the description is relatively simple, and the relevant points are referred to in the description of the method section.

It should also be noted that in this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The technical scheme provided by the application is described in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that the present application may be modified and practiced without departing from the spirit of the present application.

Claims

1. A serial communication system comprising a master device and a slave device;

The master device and the slave device both adopt a CPU+FPGA structure, wherein the FPGA is connected with the corresponding CPU through an analog RAM interface mode to realize the communication in the device; the FPGA of the master device and the FPGA of the slave device are connected with each other in an analog SPI serial interface mode to realize master-slave communication between the devices;

Specifically, the system is applied to a subway traction inverter, the main equipment is a system controller and is composed of an ARM single-chip microcomputer and an FPGA; the slave equipment is a motor controller and consists of a DSP and an FPGA; the system controller is responsible for vehicle control logic, outputting control instructions required by operation to the motor controller in real time, receiving state feedback of the motor controller, reading and writing parameters of the motor controller, periodically reading key signals of the motor controller and monitoring waveforms;

the process of master-slave communication comprises the following steps: the FPGA of the master equipment sets a receiving and transmitting address according to the information type of the communication data frame sent to the slave equipment, and generates a check word in the sending process according to the receiving and transmitting address; when the FPGA of the slave equipment acquires a communication data frame returned by the FPGA according to the check word, checking the returned communication data frame, and effectively setting a data receiving flag bit when the check word passes, so that the CPU processes the data; the frame format of the communication data frame sent to the slave device is not the same as that of the communication data frame returned; the data receiving zone bit comprises a control command sending zone bit, a parameter reading and writing zone bit, a parameter returning zone bit, a waveform reading zone bit and a fault information zone bit, and the priority of each zone bit is as follows in sequence from high to low: the control command sends a flag bit, a parameter read-write flag bit, a parameter return flag bit, a waveform read flag bit and a fault information flag bit.

2. The serial communication system according to claim 1, wherein a frame type definition word is included in a communication data frame transmitted from the master device to the slave device, the frame type definition word specifying an information type of the communication data frame at present;

3. Serial communication system according to claim 2, characterized in that different information types correspond to different priorities, so that the master device, when transmitting communication data frames to the slave device, in particular transmits the communication data frame to be transmitted with the highest current priority to the slave device.

4. The serial communication system of claim 2, wherein the information type comprises at least one of:

5. The serial communication system according to claim 1, wherein the FPGA of the master device is specifically configured to, when sending a communication data frame to the slave device:

6. The serial communication system of claim 1, wherein the SPI serial interface between the master device and the slave device is connected by an optical fiber.

7. The serial communication system according to claim 2, wherein in the master device and the slave device, a data connection line between the CPU and the FPGA includes an address line, a data line, a control line; the data connection line between the FPGA of the master device and the FPGA of the slave device comprises a clock signal line, a master device transmission line and a slave device transmission line.

8. The serial communication system according to claim 7, wherein the master device and the slave device write on a rising edge of a clock signal, in particular on a falling edge of the clock signal, when performing SPI serial communication.

9. The serial communication system of claim 8, wherein the communication data frames between the master device and the slave device each include a start bit and an end bit;

10. The serial communication system according to claim 9, wherein the frame format of the communication data frame transmitted from the master device to the slave device is: