CN112737597A - Multi-rate LDPC coding method with variable frame length and suitable for deep space communication - Google Patents

Multi-rate LDPC coding method with variable frame length and suitable for deep space communication Download PDF

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CN112737597A
CN112737597A CN202011063544.4A CN202011063544A CN112737597A CN 112737597 A CN112737597 A CN 112737597A CN 202011063544 A CN202011063544 A CN 202011063544A CN 112737597 A CN112737597 A CN 112737597A
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王翠莲
郭坚
周东
李珂
赵蕾
杨小瑞
张红军
朱玛
兰天
朱剑冰
韦涌泉
庞亚龙
吴雨航
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Beijing Institute of Spacecraft System Engineering
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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Abstract

The invention relates to a multi-rate LDPC coding method with variable frame length suitable for deep space communication, which comprises the following steps: step one, caching received data frames; setting the value of the code length L; step three, designing the LDPC code with the coding parameter of (4088,1784); fourthly, starting a corresponding LDPC coding process for the received data frame according to the value of the coding code length L; and step five, caching the encoded data, and then outputting the encoded data. The length of the data frames before and after coding is matched with that of the traditional deep space detector, the length of the data frames can be set by a user according to a demand sending instruction, and a multi-rate output scheduling mechanism is adopted, so that the problem of multi-rate switching of output data after coding is solved.

Description

Multi-rate LDPC coding method with variable frame length and suitable for deep space communication
Technical Field
The invention relates to the technical field of spacecraft measurement and control data transmission, in particular to a multi-rate LDPC coding method with a variable frame length, which is suitable for deep space communication.
Background
In the design of the deep space probe, due to the long communication distance, the long transmission delay and the extremely low receiving signal-to-noise ratio, a high-performance channel coding method needs to be designed to provide reliable communication. In the design of a traditional deep space communication system, a single RS + convolutional concatenated code is adopted, and the coding gain is 6-7 dB. In recent years, Low Density Parity Check (LDPC) codes have attracted attention in the field of deep space communications due to their advantages of high coding gain, moderate complexity, parallel coding and decoding, and the like.
The LDPC code recommended by the CCSDS standard and suitable for the deep space communication telemetry \ data transmission channel is a systematic LDPC code with a quasi-cyclic structure, and comprises three information lengths (128 bytes, 512 bytes and 2048 bytes before coding) and three code rates (1/2 bytes, 2/3 bytes and 4/5), and the coding gain is not less than 9 dB. In the current deep space detection task, the coding mode generally adopted by the remote measurement \ data transmission channel is (223, 255) RS coding + (1/2) convolutional coding, the length of a data frame before coding is 220 bytes or 892 bytes, and the length of a corresponding coded frame is 512 bytes or 2048 bytes. Because the deep space probe has complex channel conditions for the ground and the relay link, and different channel environments put different requirements on coding modes and rates, the telemetering \ data transmission channel needs to be compatible with various coding modes and can be switched on track through instructions. The LDPC coding recommended by the CCSDS standard is not compatible with the existing RS + convolutional concatenated coding scheme.
Aiming at the situation, the invention designs a multi-rate LDPC coding method with variable frame length suitable for deep space communication, the data frame length before and after coding is matched with the traditional deep space detector, and the data frame length can be set by a user according to a requirement sending instruction. Meanwhile, a multi-rate output scheduling mechanism is adopted, so that the problem of multi-rate switching of output data after coding is solved. The long frame coding process and the short frame coding process share the LDPC coding module, the scrambling module and the insertion synchronization head module, so that hardware resources are saved, and the complexity of implementation is greatly reduced.
Disclosure of Invention
The invention aims to design a multi-rate LDPC coding method with variable frame length aiming at the task characteristics of high requirement on coding gain, coexistence of multiple frame lengths and need of supporting on-track multi-rate switching in deep space communication.
In order to solve the problems in the prior art, the invention provides a multi-rate LDPC coding method with variable frame length, which is suitable for deep space communication, and comprises the following steps:
step one, caching received data frames;
setting the value of the code length L;
step three, designing the LDPC code with the coding parameter of (4088,1784);
fourthly, starting a corresponding LDPC coding process for the received data frame according to the value of the coding length L;
and step five, caching the encoded data frame, and then outputting the encoded data frame.
Further, in the first step, caching the received data frame is realized by two caching modules, namely a short frame data frame caching module and a long frame data frame caching module; the short frame data frame buffer module is used for buffering the received short frame data frame; the long frame data frame buffer module is used for buffering the received long frame data frame; the cache adopts a ping-pong operation mechanism, and the cache module can generate a storage state flag.
Further, in the second step, the code length is set according to a long-short frame switching instruction sent by a user according to a current task requirement, and L ═ 0' represents a short frame; l ═ 1' denotes a long frame.
Further, when the value of the code length L is '0', the LDPC encoding process is as follows:
(1) when the data in the short frame data frame buffer module is not empty, reading 1760 bit data frame HS；
(2) In data frame HSThe header is padded with 24 bits 0, and the padded data frame MSThe frame length is 1784 bits;
(3) in the LDPC coding module, the data frame M is coded according to the LDPC code in the third stepSPerforming (4088,1784) LDPC encoding to obtain data frame NS。
(4) Dropping data frame NSThe initial 24 bits of padding data to obtain 4064 bits of data PS；
(5) In the scrambling moduleSScrambling is carried out, and the data sequence after scrambling is called QS；
(6) In the insertion of the synchronization head module, at QSThe head part is inserted into a 32-bit synchronous head to obtain a final coded data frame RS，RSThe frame length is 32+ 4064-4096 bits, i.e. 512 bytes.
Further, when the value of the code length L is '1', the LDPC encoding process is as follows:
(1) reading 7136 bit data frame H when data in the long frame data frame buffer module is not emptyL；
(2) Data frame HLSplit into 4 1784 bit data blocks, respectively labeled as MLA、MLB、 MLC、MLD；
(3) In the LDPC coding module, the data blocks M are respectively coded according to the LDPC codes in the step threeLA、MLB、 MLC、MLDPerforming (4088,1784) LDPC encoding to obtain 4 encoded data blocks NLA、NLB、 NLC、NLDThe length of each of the 4 coded data blocks is 4088 bits;
(4) data block NLA、NLB、NLC、NLDAre combined into 1 16352-bit data sequence PL；
(5) In the scrambling moduleLScrambling is carried out, and the data sequence after scrambling is called QL；
(6) In the insertion of the synchronization head module, at QLThe head part is inserted into a 32-bit synchronous head to obtain a final coded data frame RL，RLThe frame length is 32+ 16352-16384 bits, i.e. 2048 bytes.
Furthermore, in different LDPC coding flows, the design states of the LDPC coding module, the scrambling module and the synchronous head insertion module are consistent, and the modules can be shared.
Furthermore, in the fifth step, the buffering of the encoded data frame is realized by two buffering modules, namely a short frame encoded data frame buffering module and a long frame encoded data frame buffering module; the short frame coding data frame buffer module is used for buffering the coded short frame data frame; the long frame coding data frame buffer module is used for buffering the coded long frame data frame.
Further, before outputting the encoded data frame, the method further includes the following steps:
(1) dividing the frequency of a local clock according to the rate switching instruction to generate an equally-spaced pulse signal;
(2) counting the pulse signals, and generating a scheduling mark according to the numerical value of the pulse signals;
(3) when the dispatching mark is effective, inquiring the state of the short frame coded data frame buffer module or the long frame coded data frame buffer module;
(4) and when the short frame coding data frame buffer module or the long frame coding data frame buffer module is not empty, reading the coded data according to bits and outputting the coded data.
Further, when L is equal to '0', a scheduling flag is generated every 4096 pulse signals; when L ═ 1', a scheduling flag is generated every 16384 pulse signals.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention designs a multi-rate LDPC coding method with variable frame length suitable for deep space communication, the length of data frames before and after coding is matched with the length of the traditional deep space detector, and the length of the data frames can be set by a user according to the requirement of sending a long-short frame switching instruction.
2. The invention solves the problem of multi-rate switching of the output data after encoding.
3. The long frame coding process and the short frame coding process share the LDPC coding module, the scrambling module and the insertion synchronization head module, thereby saving hardware resources and greatly reducing the complexity of implementation.
Drawings
FIG. 1 is a block diagram of an embodiment of a multi-rate LDPC encoding method with variable frame length according to the present invention;
fig. 2 is a schematic diagram of a short frame encoding process according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a long frame encoding process according to an embodiment of the present invention;
FIG. 4 is an example of a short frame format according to an embodiment of the present invention;
FIG. 5 is an example of a long frame format provided by an embodiment of the present invention;
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be further described in detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The deep space detector uses LDPC coding to the ground link, the coding gain is required to be not less than 9dB, meanwhile, the coding mode is required to be suitable for a short frame (220 bytes, the frame format is shown in figure 4) and a long frame (892 bytes, the frame format is shown in figure 5), the coded data frames are 512 bytes and 2048 bytes respectively, and switching is carried out through a long frame and short frame switching instruction. The data rate of the coded data output to the responder is adjustable within 32 bps-2048 kbps. The specific treatment steps are as follows:
step one, caching received data frames;
as shown in fig. 1, two receiving buffers are designed at the interface between the encoding module and the combining module. The receiving cache is realized by the BLOCKRAM inside the FPGA, the storage depth of the BLOCKRAM is 2048, and the bit width is 8 bits. The short frame data is stored in block kram1, and 2n-1(n is 1,2,3 …) th frame 220 bytes are stored in addresses 0 to 219, and 2n frame 220 bytes are stored in addresses 1024 to 1243. The long frame data is stored in block ram2, bytes 2n-1 frame 892 are stored at addresses 0 through 891, and bytes 2n frame 892 are stored at addresses 1024 through 1915.
1. When the data in BLOCKRAM1 is not full, the shunting module can continue to write short frame data, otherwise continue to wait;
2. the bifurcating module may continue to write long frame data when the data in BLOCKRAM2 is not full, and continue to wait otherwise.
3. When the data in the BLOCKRAM1 is not empty, the LDPC coding module can start the short frame coding flow, otherwise, the short frame coding flow continues to wait;
4. when the data in block kram2 is not empty, the LDPC coding module may start the long frame coding flow, otherwise continue to wait.
Step two, setting a coding code length L according to a long and short frame switching instruction sent by a user according to the current task requirement, wherein the length L is equal to '0' and represents a short frame; l ═ 1' denotes a long frame
And step three, designing the LDPC code with the coding parameters of (4088, 1784).
1. And constructing the LDPC code with the coding parameters of (4096, 1792).
The dimension of the base matrix of the check matrix H is 18 × 32 and the dimension of the extended matrix is 128 × 128, and therefore, the dimension of the check matrix H is 2304 × 4096. H can be decomposed into H1And H2，H1Representing the part corresponding to the information bit, H2Representing the portion corresponding to the check bits.
Figure BDA0002713094950000051
In the formula (1), H1From mb×kbAn I × I all-zero or non-zero sub-array, ELDenotes an I × I identity matrix, mb＝18，kb＝14，I＝128。
The row-column weight distribution of the LDPC check matrix is as follows:
line weight distribution:
Figure BDA0002713094950000061
the weight distribution is as follows:
Figure BDA0002713094950000062
the LDPC code has an information bit length of 1792 bits, a check bit length of 2304 bits, and encoding parameters of (4096, 1792).
2. And deleting 8 bits of the (4096, 1792) code, deleting the last 8 bits of the information bits, and obtaining the LDPC code with the coding parameters of (4088, 1784).
Fourthly, starting a corresponding LDPC coding process for the received data frame according to the value of the coding code length L;
1. as shown in fig. 2, the short frame encoding process is as follows:
(1) when the data in BLOCKRAM1 is not empty, read 1760 bits of data frame HS。
(2) In data frame HSThe header is padded with 24 bits 0, and the padded data frame MSThe frame length is 1784 bits.
(3) In the LDPC coding module, according to the LDPC code pair M described in the step threeSPerforming (4088,1784) LDPC encoding. The encoding processing flow is as follows, a state variable enc _ state is set in an encoder, and the value is 0-4095. When the enc _ state is more than or equal to 0 and less than or equal to 1783, the encoder outputs 1784 bit information sequence; when 1784 is not more than enc _ state is not more than 1791, the encoder does not output; when 1792 ≦ enc _ state ≦ 4095, the encoder outputs 2304 bit check sequence. The enc _ state outputs 4088 bits of data in a total change period, which is called a coded code word NS。
(4) Remove NSThe initial 24 bits of padding data to obtain 4064 bits of data PS。
(5) In the scrambling moduleSScrambling is carried out, and the scrambled data sequence is called QS. The pseudo-random sequence generating polynomial adopted in the scrambling operation is h (x) x8+x7+x5+x3+1. For each PSThe initial state of the disturbance is all 1.
(6) In the insertion of the synchronization head module, at QSThe head part is inserted into a 32-bit synchronous head to obtain a final coded data frame RS，RSThe frame length is 32+4064 4096 bits (512 bytes).
2. As shown in fig. 3, the long frame encoding process is as follows:
(1) reading 7136 bit data frame H when data in BLOCKRAM2 is not emptyL。
(2) Handle HLSplit into 4 1784 bit data blocks, respectively labeled as MLA、MLB、MLC、 MLD。
(3) In the LDPC coding module, the data block M is processedLA、MLB、MLC、MLDAnd respectively carrying out (4088,1784) LDPC coding, wherein the coding process is the same as the short frame coding process in the step (3). To obtainTo 4 encoded data blocks NLA、NLB、NLC、NLDAnd the length is 4088 bits.
(4) Data block NLA、NLB、NLC、NLDAre combined into 1 16352-bit data sequence PL。
(5) In the scrambling moduleLScrambling is carried out, and the scrambled data sequence is called QL. The pseudo-random sequence generating polynomial adopted in the scrambling operation is h (x) x8+x7+x5+x3+1. For each PLThe initial state of the disturbance is all 1.
(6) In the insertion of the synchronization head module, at QLThe header is inserted with a 32-bit (0x1ACFFC1D) synchronization header to obtain a data frame RL。RLThe frame length is 32+ 16352-16384 bits (2048 bytes).
In the short frame coding flow and the long frame coding flow, the design states of an LDPC coding module, a scrambling module and an insertion synchronization head module are consistent, and the modules can be shared.
And step five, caching the encoded data frame, and then outputting the encoded data frame.
1. The output interface is provided with an output buffer for storing the encoded data frame. The output buffer is realized by BLOCKRAM inside the FPGA. The encoded short frame data is stored in BLOCKRAM3, and the encoded long frame data is stored in BLOCKRAM 4.
2. And setting a clock generation module, dividing the frequency of a local clock according to the rate switching instruction, generating pulse signals with equal intervals, counting the pulse signals and generating a scheduling mark.
(1) In the short frame mode, a scheduling mark is generated every 4096 pulse signals;
(2) in long frame mode, a scheduling flag is generated every 16384 pulses.
3. And when the scheduling mark is effective, inquiring the output buffer state, and when the output buffer is not empty, outputting the coded data to the responder according to bits.
(1) In the short frame mode, the BLOCKRAM3 is inquired and read;
(2) in long frame mode, the BLOCKRAM4 is queried and read.
Although the invention has been described in detail hereinabove by way of general description, specific embodiments and experiments, it will be apparent to those skilled in the art that many modifications and improvements can be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of this invention as claimed.

Claims (9)

1. A multi-rate LDPC coding method with variable frame length suitable for deep space communication is characterized by comprising the following steps:
step one, caching received data frames;
setting the value of the code length L;
step three, designing the LDPC code with the coding parameter of (4088,1784);
fourthly, starting a corresponding LDPC coding process for the received data frame according to the value of the coding code length L;
and step five, caching the encoded data frame, and then outputting the encoded data frame.
2. The method according to claim 1, wherein in the first step, the buffering of the received data frame is implemented by two buffering modules, namely a short frame data frame buffering module and a long frame data frame buffering module; the short frame data frame buffer module is used for buffering the received short frame data frame; the long frame data frame buffer module is used for buffering the received long frame data frame.
3. The method according to claim 2, wherein in the second step, the coding code length is set according to a long-short frame switching instruction sent by a user according to a current task requirement, wherein L ═ 0' represents a short frame; l ═ 1' denotes a long frame.
4. The method according to claim 3, wherein in the fourth step, when the coding length L is '0', the LDPC coding process is as follows:
(1) when the data in the short frame data frame buffer module is not empty, reading 1760 bit data frame HS；
(2) In data frame HSThe header is padded with 24 bits 0, and the padded data frame MSThe frame length is 1784 bits;
(3) in the LDPC coding module, the data frame M is coded according to the LDPC code in the third stepSPerforming (4088,1784) LDPC encoding to obtain data frame NS。
(4) Dropping data frame NSThe initial 24 bits of padding data to obtain 4064 bits of data PS；
(5) In the scrambling moduleSScrambling is carried out, and the data sequence after scrambling is called QS；
(6) In the insertion of the synchronization head module, at QSThe head part is inserted into a 32-bit synchronous head to obtain a final coded data frame RS，RSThe frame length is 32+ 4064-4096 bits, i.e. 512 bytes.
5. The method according to claim 3, wherein in the fourth step, when the coding length L is '1', the LDPC coding process is as follows:
(1) reading 7136 bit data frame H when data in the long frame data frame buffer module is not emptyL；
(2) Data frame HLSplit into 4 1784 bit data blocks, respectively labeled as MLA、MLB、MLC、MLD；
(3) In the LDPC coding module, the data blocks M are respectively coded according to the LDPC codes in the step threeLA、MLB、MLC、MLDPerforming (4088,1784) LDPC encoding to obtain 4 encoded data blocks NLA、NLB、NLC、NLDThe length of each of the 4 coded data blocks is 4088 bits;
(4) data block NLA、NLB、NLC、NLDAre combined into 1 16352-bit data sequence PL；
(5) In the scrambling moduleLScrambling is carried out, and the data sequence after scrambling is called QL；
(6) In the insertion of the synchronization head module, at QLThe head part is inserted into a 32-bit synchronous head to obtain a final coded data frame RL，RLThe frame length is 32+ 16352-16384 bits, i.e. 2048 bytes.
6. The method according to claim 4 or 5, wherein, in different LDPC coding flows, the design states of the LDPC coding module, the scrambling module and the insertion synchronization head module are consistent, and the modules can be shared.
7. The method according to claim 3, wherein in the fifth step, the buffering of the encoded data frame is implemented by two buffering modules, namely a short frame encoded data frame buffering module and a long frame encoded data frame buffering module; the short frame coding data frame buffer module is used for buffering the coded short frame data frame; the long frame coding data frame buffer module is used for buffering the coded long frame data frame.
8. The method according to claim 7, wherein in the fifth step, before outputting the encoded data frame, the method further comprises the following steps:
(1) dividing the frequency of a local clock according to the rate switching instruction to generate an equally-spaced pulse signal;
(2) counting the pulse signals, and generating a scheduling mark according to the numerical value of the pulse signals;
(3) when the scheduling mark is effective, inquiring the state of the short frame coded data frame buffer module or the long frame coded data frame buffer module;
(4) and when the short frame coding data frame buffer module or the long frame coding data frame buffer module is not empty, reading the coded data according to bits and outputting the coded data.
9. The method according to claim 8, wherein in the fifth step, when L is equal to '0', a scheduling flag is generated every 4096 pulse signals; when L ═ 1', a scheduling flag is generated every 16384 pulse signals.
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