CN112600574A

CN112600574A - Digital DDC design method of multi-channel direction finding receiver based on FPGA

Info

Publication number: CN112600574A
Application number: CN202011439788.8A
Authority: CN
Inventors: 刘博�; 张建军; 蒋航; 李鑫儒; 云天嵩
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2020-12-10
Filing date: 2020-12-10
Publication date: 2021-04-02

Abstract

The invention discloses a digital DDC design method of a multi-channel direction finding receiver based on an FPGA, which is characterized in that each channel is provided with a cascade link which can be configured with a DDS, a programmable CIC and a multi-stage filter, each channel of frequency point can be configured through the configurable DDS, each channel of bandwidth can be configured through the programmable CIC, and the multi-stage filter can be used for extracting and filtering and narrow-band filtering. The invention designs a cascade link comprising a configurable DDS, a programmable CIC and a multistage filter, and finishes the conversion of signals acquired by AD into original IQ data after down-conversion, the attenuation of the link is far less than 1dB, the phase relation of an IQ path is consistent with the output of the DDS, the subsequent sensitivity test, direction finding precision and the like are not influenced, and the cascade link can be used as direction finding preprocessing data.

Description

Digital DDC design method of multi-channel direction finding receiver based on FPGA

Technical Field

The invention belongs to the field of ultrashort wave communication, and particularly relates to a digital DDC (direct digital control) design method of a multi-channel direction finding receiver based on an FPGA (field programmable gate array).

Background

With the development of communication technology, in recent years, a large number of low-interception-probability signals, such as burst signals, time-short signals, frequency hopping signals and the like, are found in ultrashort wave communication, and the presence of the signals brings a great challenge to ultrashort wave direction finding and positioning. And the ultrashort wave direction finding not only needs to achieve high direction finding accuracy and sensitivity, but also needs to solve the problems of high probability direction finding, weak signal direction finding, multi-channel real-time direction finding, multi-task real-time direction finding, data backtracking direction finding and the like of low interception probability signals. In order to meet the above requirements, ultrashort wave direction-finding systems must use wideband in combination with narrowband direction-finding, multichannel direction-finding in combination, and various direction-finding methods. The multichannel digital down-conversion technology is a basis for providing preprocessing data for ultra-short wave direction finding, and the quality of original IQ data after digital down-conversion directly influences the subsequent direction finding quality, so that designing a DDC link comprising frequency conversion, truncation, decimation filtering and narrow-band filtering to obtain high-quality and low-loss original IQ data is a central link in a direction finding system and is also a base stone of the whole direction finding system.

Disclosure of Invention

The invention provides a digital DDC design method of a multi-channel direction finding receiver based on an FPGA, which designs a cascade link comprising a configurable DDS, a programmable CIC and a multi-stage filter, and completes the conversion of signals acquired by AD into original IQ data after down-conversion.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a digital DDC design method of a multi-channel direction finding receiver based on an FPGA is characterized in that a cascade link of a configurable DDS, a programmable CIC and a multi-stage filter is arranged in each channel, configurable frequency points of each channel are achieved through the configurable DDS, configurable bandwidth of each channel is achieved through the programmable CIC, and extraction filtering and narrow-band filtering are achieved through the multi-stage filter.

Further, the channels all support 8-channel DDCs, and 8 double-channel configurable DDSs are multiplexed.

Furthermore, after the DDS and the AD sampled data are mixed, IQ paths are respectively input to the two-channel programmable CIC.

Furthermore, the multistage filter adopts two-stage filtering, the first stage is a decimation filter, and the second stage is a narrow-band filter.

Further, the first stage decimation filter is set to have an order of 72.

Further, the second-stage narrow-band filter is set to have an order of 96.

Further, XC7K410T is selected by the FPGA.

Compared with the prior art, the invention has the following beneficial effects:

the invention designs a cascade link comprising a configurable DDS, a programmable CIC and a multistage filter, and finishes the conversion of signals acquired by AD into original IQ data after down-conversion, the attenuation of the link is far less than 1dB, the phase relation of an IQ path is consistent with the output of the DDS, the subsequent sensitivity test, direction finding precision and the like are not influenced, and the cascade link can be used as direction finding preprocessing data.

Drawings

FIG. 1 is a block diagram of a single channel down-conversion link of an embodiment of the present invention;

FIG. 2 is a first stage filter parameter design of an embodiment of the present invention;

FIG. 3 is a first stage filter parameter design of an embodiment of the present invention;

fig. 4 is a diagram showing an output spectrum in MATLAB according to an embodiment of the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

The invention is further described with reference to the following figures and specific embodiments.

The embodiment of the invention provides a narrow-band DDC link design and implementation scheme, the number of channels is seven, each channel supports 8-channel DDC, the sampling rate of DDC narrow-band signals supports 4096ksps to 16ksps, each channel is independently configurable, the bandwidth of the DDC narrow-band signals supports 3.2MHz to 12.5KHz, each channel is independently configurable, and the out-of-band rejection requirement of the narrow-band signals is more than or equal to 95 dB.

1) And (3) link design:

the single channel link block diagram proposed by the present invention is shown in fig. 1, and the architecture of seven-channel multiplexing can be realized. The FPGA model is XC7K410T, the data rate is 102.4MHz, the processing rate is 204.8MHz, and each channel supports 8-channel DDC, so 8 double-channel configurable DDS modules are multiplexed to realize the configurable frequency point of each channel. After the DDS and the AD sampled data are mixed, IQ paths are respectively input into the two-channel programmable CIC, and the configurable bandwidth of each path is realized.

In order to ensure the flatness of 3dBm in-band, 5-order CIC is selected, 1 beat is selected for differential delay, and 5 times is selected for initial extraction multiple, which corresponds to a sampling rate of 4.096 MHz. The CIC decimation configuration is set to be configurable, ranging from 5 to 1280 times.

After extraction and filtering, IQ paths enter an extraction and filtering module in parallel, 16 extraction and filtering modules are multiplexed, a first-stage extraction filter is configured with an order of 72, a passband is 1.6MHz, a stopband is 2.45MHz, in-band flatness is set to be 1dB, out-of-band rejection is 96dB, and the quantization bit width is 17 bits in consideration of DSP resource consumption.

In order to save DSP resources of the FPGA and reduce a stop band of the filter, the second-stage narrow-band filter is configured with the order of 96, the pass band of 1.6MHz and the stop band of 1.7273MHz, the flatness in the band is set to be 1dB, the out-of-band rejection is 96dB, and the quantized bit width is 17 bits in consideration of the DSP resource consumption.

2) Data rate evaluation:

the maximum data rate is: 4.096MHz × 32bit × 8 channels × 7 channels ═ 0.734 Gb/s.

3) Module design and corresponding resource consumption assessment:

a) DDS & multiplier resource occupancy

The DDS & multiplier resource occupancy is shown in table 1.

TABLE 1 DDS & multiplier resource occupancy table

	LUT	REG	BRAM	DSP
					DDS	--	--	2	0
Mult	--	--	0	0
					1 way AD Total	--	--	16	0
7 routes AD Total	--	--	112	0

b) CIC resource occupation

In order to obtain the in-band flatness within 3dBm, the CIC is designed to be extracted by 5-1280 times, and the resource occupation is shown in Table 2.

TABLE 2 CIC resource occupancy table

c) First stage filter design and resource occupation

The corresponding coefficients of the first stage filter are shown in fig. 2, and the quantization bit width is 17 bits. The resource consumption is shown in table 3.

TABLE 3 first stage Filter resource occupancy Table

	LUT	REG	BRAM	DSP
					FIR_1	--	--	0	5
1 way AD Total	--	--	0	80
					7 routes AD Total	--	--	0	560

d) Second stage filter design and resource occupation

The corresponding coefficients of the second stage filter are shown in fig. 3, and the quantization bit width is 17 bits. The resource consumption is shown in table 4.

Table 4 second stage filter resource occupancy table

	LUT	REG	BRAM	DSP
					FIR_1	--	--	0	1
1 way AD Total	--	--	0	16
					7 routes AD Total	--	--	0	112

e) Total algorithm resource occupation

After the FPGA synthesis, the occupied resources are shown in Table 5.

TABLE 5 Algorithm Module resource occupancy Table

	LUT	REG	BRAM	DSP
					DDS&Mult	--	--	112	0
CIC	--	--	0	504
					First stage filter	--	--	0	560
Second stage filter	--	--	0	112
					Total up to	--	--	112	1176
K7410T	254200	508400	795	1540
					Theoretical calculated occupancy rate	--	--	14.09％	76.36％
Integrated post occupancy rate	51％	37％	15％	73％

In summary, after resource evaluation, the algorithm module of the present invention can be implemented on XC7k 410T.

The output result of the invention is imported into an MATLAB observation result, and whether the FFT frequency spectrum is normal or not is observed. An SMA-100B signal source is selected, the output amplitude is set to be-60 dBm, the output frequency point is set to be 76.8MHz, the central frequency point is set to be 26.1MHz through VIO in the FPGA, and then the signal deviates from the central frequency point by 0.5MHz, and the signal is over-sampled and should be 0.5MHz at the right side of the central frequency point. The results of the experiment are shown in FIG. 4.

When the link attenuation of the invention is tested, when a signal source inputs 76.7MHz and 10dBm, the peak value after AD sampling is 25.4MHz and the peak value after AD sampling is as follows: 22000-30000, and the peak value of the output waveform of the FPGA downloader observation algorithm is about 28500. The link attenuation is far less than 1dB, the IQ path phase relation is consistent with the DDS output, subsequent sensitivity test, direction finding precision and the like are not influenced, and the DDS can be used as direction finding preprocessing data.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A digital DDC design method of a multi-channel direction finding receiver based on an FPGA is characterized in that a cascade link of a configurable DDS, a programmable CIC and a multi-stage filter is arranged in each channel, configurable frequency points of each path are achieved through the configurable DDS, configurable bandwidth of each path is achieved through the programmable CIC, and extraction filtering and narrow-band filtering are achieved through the multi-stage filter.

2. The digital DDC design method of the FPGA-based multi-channel direction-finding receiver of claim 1, wherein the channels all support 8-way DDC, and 8 two-channel configurable DDS are multiplexed.

3. The design method for digital DDC of the multi-channel direction-finding receiver based on FPGA of claim 1, wherein the IQ paths are respectively input to the two-channel programmable CIC after mixing the configurable DDS with the AD sampled data.

4. The digital DDC design method of the FPGA-based multi-channel direction finding receiver of claim 1, wherein the multi-stage filter adopts two-stage filtering, the first stage is a decimation filter, and the second stage is a narrow-band filter.

5. The method according to claim 4, wherein the first decimation filter is set to 72 orders.

6. The method according to claim 4, wherein the second-stage narrow-band filter is set to have an order of 96.

7. The digital DDC design method of FPGA-based multi-channel direction-finding receiver of any of claims 1-6, characterized in that the FPGA selects XC7K 410T.