CN112530502A - 具有复制路径的穿硅通孔检查电路 - Google Patents

具有复制路径的穿硅通孔检查电路 Download PDF

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Publication number
CN112530502A
CN112530502A CN202010952553.2A CN202010952553A CN112530502A CN 112530502 A CN112530502 A CN 112530502A CN 202010952553 A CN202010952553 A CN 202010952553A CN 112530502 A CN112530502 A CN 112530502A
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path
semiconductor chip
tsv
circuit
chip
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真壁晴空
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Micron Technology Inc
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Micron Technology Inc
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    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
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Abstract

本申请案涉及具有复制路径的TSV检查电路。本文中揭示一种设备，其包含：第一半导体芯片；第一TSV及第二TSV，其穿透所述第一半导体芯片；第一路径，其包含所述第一TSV；第二路径，其包含所述第二TSV；第一充电电路，其经配置以对所述第一路径进行充电；第二充电电路，其经配置以对所述第二路径进行充电；第一放电电路，其经配置以对所述第一路径进行放电；第二放电电路，其经配置以对所述第二路径进行放电；及比较器电路，其经配置以将所述第一路径的电位与所述第二路径的电位进行比较。

Description

具有复制路径的穿硅通孔检查电路
技术领域
本申请案涉及存储器装置，且特定来说涉及用于存储器装置中的具有复制路径的TSV检查电路。
背景技术
用于存储器装置(例如HBM(高带宽存储器))中的半导体芯片包含若干个TSV(穿硅通孔)，每一TSV经设置以在一些情形中穿透半导体衬底。设置于每一半导体芯片中的TSV经由微凸块而连接到在另一半导体芯片中设置于相同平面位置处的TSV，使得形成穿透多个半导体衬底的信号路径。如果特定TSV具有传导故障或两个TSV之间的连接部分具有连接故障，那么对应信号路径变为有缺陷的的且实际上无法使用。在此情形中，使用备用信号路径来取代具有故障的信号路径，使得故障得以恢复。可不仅在制造阶段中而且在实际使用(即，在接通电力之后的初始化周期)中执行对每一信号路径的检验及利用备用信号路径进行替换。在其中于初始化周期中执行对信号路径的检验的情形中，可被指派给每一信号路径的检验时间可为极短的。因此，不容易针对所有信号路径执行正确检验。
发明内容
本申请案的一方面针对于一种设备，其包括：第一半导体芯片；第一TSV及第二TSV，其穿透所述第一半导体芯片；第一路径，其包含所述第一TSV；第二路径，其包含所述第二TSV；第一充电电路，其经配置以对所述第一路径进行充电；第二充电电路，其经配置以对所述第二路径进行充电；第一放电电路，其经配置以对所述第一路径进行放电；第二放电电路，其经配置以对所述第二路径进行放电；及比较器电路，其经配置以将所述第一路径的电位与所述第二路径的电位进行比较。
本申请案的另一方面针对于一种设备，其包括多个第一半导体芯片，其彼此上下地堆叠，所述多个第一半导体芯片包含各自通过所述多个第一半导体芯片的第一路径及第二路径；及接口芯片，其堆叠于所述多个第一半导体芯片上，使得所述接口芯片耦合到所述第一路径及所述第二路径的第一端中的每一者，所述接口芯片经配置以控制：用第一电压来对所述第一路径及所述第二路径的第二端中的每一者进行充电；及在用所述第一电压来对所述第一路径及所述第二路径的第二端中的每一者进行充电之后，将所述第一路径与所述第二路径的所述第一端的电位进行比较。
本申请案的又一方面针对于一种设备，其包括：半导体芯片；多个第一TSV，其穿透所述半导体芯片；第二TSV，其穿透所述半导体芯片；第一电路，其经配置以选择所述多个第一TSV中的一者；第二电路，其经配置以响应于第一时序信号而将第一电位施加到所述第一TSV中的所述选定一者及所述第二TSV；第三电路，其经配置以响应于第二时序信号而将不同于所述第一电位的第二电位施加到所述第一TSV中的所述选定一者及所述第二TSV；及第四电路，其经配置以将所述第一TSV中的所述选定一者的电位与所述第二TSV的电位进行比较。
附图说明
图1是展示根据本发明的半导体装置的配置的示意图。
图2是展示多个TSV的布局的示意性平面图。
图3是展示连接到存储器核心芯片中的TSV的电路的电路图。
图4是展示连接到接口芯片中的TSV的电路的电路图。
图5是展示其中检验信号路径的第一电路实例的电路图。
图6及图7是展示图5中所展示的电路的操作的时序图。
图8是展示其中检验信号路径的第二电路实例的电路图。
图9是展示其中检验信号路径的第三电路实例的电路图。
图10是展示其中检验信号路径的第四电路实例的电路图。
具体实施方式
下文将参考附图详细地解释本发明的各种实施例。以下详细描述参考附图，所述附图以图解说明方式展示其中可实践本发明的特定方面及实施例。充分详细地描述这些实施例以使所属领域的技术人员能够实践本发明。可利用其它实施例，且可在不背离本发明的范围的情况下做出结构、逻辑及电改变。本文中所揭示的各种实施例未必相互排斥，这是因为一些所揭示实施例可与一或多个其它所揭示实施例组合以形成新实施例。
图1中所展示的半导体装置是具有配置的HBM，在所述配置中，八个存储器核心芯片20到27堆叠于接口芯片10上。然而，本发明可适用的半导体装置并不限于HBM。存储器核心芯片20到27各自为其中集成有包含存储器单元阵列的存储器核心的半导体芯片。接口芯片10为控制存储器核心芯片20到27的半导体芯片。接口芯片10及存储器核心芯片20到26各自具有经设置以穿透半导体衬底的多个TSV 30。所有接口芯片10及存储器核心芯片20到27以面朝下方式(也就是说，以使得其上形成有晶体管及布线图案(均未展示)的主要表面面朝下方式)进行堆叠。因此，在位于最上部层中的存储器核心芯片27中，无需TSV 30。然而，位于最上部层中的存储器核心芯片27可具有TSV 30。设置于存储器核心芯片20到26中的几乎所有TSV 30分别连接到位于相同平面位置处的前表面TSV垫31A。同时，设置于接口芯片10中的大多数TSV 30及设置于接口芯片10上的大多数前表面TSV垫31A存在于彼此不同的平面位置处。在设置于接口芯片10及存储器核心芯片20到26中的TSV 30当中，位于相同平面位置处的TSV 30经由前表面TSV垫31A、TSV凸块31B及后表面TSV垫31C而以级联连接方式彼此连接。以此方式，形成多个信号路径32。经由信号路径32而将从接口芯片10输出的命令及写入数据供应到存储器核心芯片20到27。经由信号路径32而将从存储器核心芯片20到27输出的读取数据供应到接口芯片10。外部端子33设置于接口芯片10上，经由所述外部端子而执行到外部电路的信号传输及从所述外部电路的信号接收。
如图2中所展示，在接口芯片10及存储器核心芯片20到26中的每一者中，TSV 30以矩阵形式进行布置。将选择电路34指派给每一TSV 30。在对信号路径32的检验中使用选择电路34，所述检验在制造阶段以及在接通电力之后的初始化周期中执行。如图2中所展示，将选择信号线Y0、Y1、Y2、Y3、…中的对应一者指派给在x方向上进行布置的TSV 30。将选择信号线X0、X1、X2、X3、…中的对应一者指派给在y方向上进行布置的TSV 30。选择信号线Y0、Y1、Y2、Y3、…分别将选择信号Ysel0、Ysel1、Ysel2、Ysel3、…供应到对应选择电路34。选择信号线X0、X1、X2、X3、…分别将选择信号Xsel0、Xsel1、Xsel2、Xsel3、…供应到对应选择电路34。选择电路12激活选择信号Ysel0、Ysel1、Ysel2、Ysel3、…中的任一者且撤销激活所有其余信号。选择电路14激活选择信号Xsel0、Xsel1、Xsel2、Xsel3、…中的任一者且撤销激活所有其余信号。以此方式，激活选择电路34中的任一者，使得选择与其对应的TSV 30中的一者。
包含于存储器芯片20到27中的每一者中的每一选择电路34包含P沟道MOS晶体管41及控制晶体管41的NAND门电路42，如图3中所展示。NAND门电路42接收选择信号Xsel0、Xsel1、Xsel2、Xsel3、…中的对应一者、选择信号Ysel0、Ysel1、Ysel2、Ysel3、…中的对应一者以及选择信号SliceEn(其选择存储器核心芯片20到27中的其中包含NAND门电路42的一个存储器核心芯片)，且在所有所接收信号处于有效电平(高电平)时将选择信号XYselF激活到低电平。在存储器核心芯片20到27中的每一者中，P沟道MOS晶体管43及P沟道MOS晶体管41串联连接于电力供应器VDD与TSV 30之间。将测试信号TESTF供应到晶体管43的栅极电极。因此，当将测试信号TESTF及选择信号XYselF两者激活到低电平时，TSV 30连接到电力供应器VDD。举例来说，电力供应器VDD为高电位侧电力供应器。在此情形中，当激活测试信号TESTF及选择信号XYselF两者时，经由TSV 30而对信号路径32进行充电。
包含于接口芯片10中的选择电路34具有与包含于存储器核心芯片20到27中的选择电路34相同的电路配置，如图4中所展示。在接口芯片10中，晶体管41及N沟道MOS晶体管47串联连接于TSV 30与电力供应器VSS之间。将测试时钟信号CLK供应到晶体管47的栅极电极。因此，当将测试时钟信号CLK激活到高电平且将选择信号XYselF激活到低电平时，TSV30连接到电力供应器VSS。举例来说，电力供应器VSS为低电位侧电力供应器。在此情形中，当激活测试时钟信号CLK及选择信号XYselF两者时，经由TSV 30而对信号路径32进行放电。
如图3及4中所展示，输出缓冲器45及输入接收器46并联连接于内部电路44与包含于接口芯片10及存储器核心芯片20到27中的每一者中的TSV 30之间。因此，经由输出缓冲器45及TSV 30而将从内部电路44输出的数据、命令等等供应到信号路径32。此外，经由TSV30及输入接收器46而将从信号路径32供应的数据、命令等等输入到内部电路44。
如图5中所展示，复数个信号路径32包含复制路径32R。复制路径32R在对其它信号路径32的检验中用作参考且具有与信号路径32相同的配置，只有使用用于接收启用信号EnF的晶体管48来取代晶体管41且串联***虚设电阻器Rd除外。在测试周期期间总是激活启用信号EnF。添加到每一信号路径32的寄生电容C1及添加到复制路径32R的寄生电容C2经设计以具有大体上彼此相同的值。每一信号路径32经由设置于接口芯片10上的晶体管41而连接到节点N1，且复制路径32R经由设置于接口芯片10上的晶体管48而连接到节点N2。接口芯片10包含比较器电路49，所述比较器电路响应于比较信号COMP而将节点N1处的电平与节点N2处的电平彼此进行比较。
参考图6及7来描述图5中所展示的电路的操作。图6展示其中在每一信号路径32中不具有故障的情形中的波形，且图7展示其中在信号路径32的一部分中存在故障的情形中的波形。首先，在其中将选择信号Xsel0、Xsel1、Xsel2、Xsel3、…中的任一者(在图6及7中所展示的实例中，选择信号Xsel0)激活到高电平的状态中，依序将选择信号Ysel0、Ysel1、Ysel2、Ysel3、…激活到高电平。因此，依序选择如图2中所展示的以矩阵形式进行布置的TSV 30，且经由选定TSV 30，对信号路径32中的对应一者进行充电。在存储器核心芯片20到27中的任一者中执行对信号路径32的充电为足够的，且不需要在其它存储器核心芯片中的充电。优选地在最上部层中的存储器核心芯片27中执行对每一信号路径32的充电。通过在最上部层中的存储器核心芯片27中对每一信号路径32进行充电，可对包含于所述信号路径32中的所有TSV 30进行测试。同时，在其中于信号路径32中存在故障的情形中，通过在并非位于最上部层中的存储器核心芯片20到26中的任一者中对每一信号路径32进行充电，可能指定存储器核心芯片20到26中的哪一者包含有缺陷TSV30。在于最上部层中的存储器核心芯片27中对每一信号路径32进行充电的情形中，将与最上部层中的存储器核心芯片27对应的选择信号SliceEn激活到高电平且将与其它存储器核心芯片20到26对应的选择信号SliceEn撤销激活到低电平为足够的。同样针对接口芯片10，将对应选择信号SliceEn激活到高电平。还通过针对最上部层中的存储器核心芯片27以及接口芯片10激活启用信号EnF而对复制路径32R进行充电。
如图6及7中所展示，测试时钟信号CLK的一个循环与选择信号Ysel0、Ysel1、Ysel2、Ysel3、…的激活周期重合。因此，在周期的前一半(在其期间选择信号路径32中的一者)期间，晶体管47接通，且因此对选定信号路径32及复制路径32R进行放电且将节点N1及N2置于VSS电平下。同时，在周期的后一半(在其期间选择信号路径32中的一者)期间，晶体管47关断，且因此选定信号路径32及复制路径32R的放电停止。当选定信号路径32及复制路径32R的放电停止时，分别经由晶体管41及48而对选定信号路径32及复制路径32R进行充电，使得节点N1及N2处的电平上升。此时，节点N1处的电平的上升速率由信号路径32的电阻值及寄生电容C1确定。此外，节点N2处的电平的上升速率由复制路径32R的电阻值及寄生电容C2确定。虽然如上文所描述复制路径32R的寄生电容C2与信号路径32的寄生电容C1大体上相同，但除非信号路径32具有故障，否则复制路径32R的充电速率低于信号路径32的充电速率，这是因为将虚设电阻器Rd串联***到复制路径32R。图6展示在其中每一信号路径32不具有故障的情形中的波形，且节点N1处的电平比节点N2处的电平上升得快。在将测试时钟信号CLK从高电平改变为低电平之后且在将测试时钟信号CLK再次改变为高电平之前的时序处激活比较信号COMP。当激活比较信号COMP时，比较器电路49执行将节点N1处的电平与节点N2处的电平彼此进行比较的操作，且当节点N1处的电平较高时，将所述比较器电路的输出信号OUT置于高电平下。这意味着信号路径32不具有故障，且故障信号FAIL保持为非现用的。
同时，图7展示在其中对应于选择信号Xsel0及Ysel2的信号路径32具有故障的情形中的波形。当在信号路径32中存在故障时，所述信号路径的电阻值为高的且信号路径32的充电速率降低。由于信号路径32中的故障，因此可考虑如下情形：由于经由TSV凸块31B的连接部分中的故障，因此TSV 30自身的电阻变为高的且信号路径32的电阻变为高的。如果信号路径32的电阻值比复制路径32R的电阻值高，那么节点N1处的电平比节点N2处的电平上升地慢。在此情形中，当激活比较信号COMP时，比较器电路49将其输出信号OUT置于低电平下。这意味着信号路径32具有故障，且激活故障信号FAIL。当激活故障信号FAIL时，对应信号路径32被停用且用备用信号路径来替换。
作为检验信号路径32的方法，还可考虑其中并非将复制路径32R用作参考而是使用恒定参考电压的方法。也就是说，考虑将比较器电路49的输入端子中的一者连接到节点N1且将恒定参考电压施加到比较器电路49的其它输入端子的方法。然而，在此方法中，对通过或故障的确定结果可由测试时钟信号CLK的频率改变。举例来说，在其中测试时钟信号CLK的实际频率高于经设计值的情形中，信号路径32的充电时间比预期的短，且因此可将无缺陷的信号路径32确定为有缺陷的。相反，在其中测试时钟信号CLK的实际频率低于经设计值的情形中，信号路径32的充电时间比预期的长，且因此将有缺陷的信号路径32确定为无缺陷的。此外，来自输出缓冲器45的关断泄漏(off-leak)电流还流动到信号路径32中。因此，当信号路径32的充电时间变为比预期的长时，将有缺陷信号路径32确定为无缺陷的风险增加，且甚至可将完全断开连接的信号路径32确定为无缺陷的。相反，根据本发明实施例的半导体装置使用复制路径32R作为参考。因此，即使测试时钟信号CLK的实际频率不同于经设计值的实际频率，此差异仍均匀地影响信号路径32及复制路径32R。此外，来自输出缓冲器45的关断泄漏电流也均匀地影响信号路径32及复制路径32R。因此，可针对每一信号路径32执行正确检验。此外，由于即使在测试时钟信号CLK的频率被设计为较高的情况下仍可执行正确检验，因此在接通电力之后的初始化周期内以充分裕量完成对若干个信号路径32的检验是可能的(甚至在其中于初始化周期中执行检验的情形中)。
此外，可将并联连接的多个虚设电阻器Rd0到Rd2***到复制路径32R中，如图8中所展示。通过进一步将晶体管50到52串联***到相应虚设电阻器Rd0到Rd2且通过使用选择信号S0到S2中的一者或两者或多于两者来接通晶体管50到52中的一者或者所述晶体管中的两者或多于两者，改变复制路径32R的电阻值是可能的。因此，通过选择信号S0到S2而切换其中信号路径32被确定为有缺陷的电阻值是可能的。在此情形中，优选地虚设电阻器Rd0到Rd2的电阻值彼此不同。
此外，如图9中所展示，在存储器核心芯片20到26及接口芯片10中的每一者中，可使用两个TSV 30来配置复制路径32R，同时所述两个TSV 30并联连接。利用此配置，即使在其中配置复制路径32R的TSV 30的一部分中存在故障的情形中，仍可正确地执行对信号路径32的检验。在此情形中，复制路径32R的电阻值由于两个TSV 30的并联连接而稍微降低。然而，包含于复制路径32R中的八个TSV 30的总电阻值为约1Ω且与晶体管48的导通电阻相比为充分低的。因此，复制路径32R的电阻值的降低几乎对检验不具有影响。此外，TSV 30中的三者或多于三者可并联连接。
此外，可将虚设电容Cd连接到复制路径32R而非将虚设电阻器Rd***到复制路径32R中，如图10中所展示。而且在此情形中，可执行与图5中所展示的电路的操作基本上相同的操作，这是因为复制路径32R的时间常数大于信号路径32的时间常数。
虽然已在特定优选实施例及实例的上下文中揭示本发明，但所属领域的技术人员将理解，本发明超出具体揭示的实施例而扩展到其它替代实施例及/或对本发明及其明显修改及等效内容的使用。另外，所属领域的技术人员将基于本发明而容易地明了在本发明的范围内的其它修改。还预期，可做出对实施例的特定特征及方面的各种组合或子组合且其仍属于本发明的范围内。应理解，所揭示实施例的各种特征及方面可彼此组合或替代以便形成所揭示本发明的不同模式。因此，打算本文中所揭示的本发明中的至少一些的范围不应由上文所描述的特定所揭示实施例限制。

Claims (20)

1.一种设备，其包括：
第一半导体芯片；
第一TSV及第二TSV，其穿透所述第一半导体芯片；
第一路径，其包含所述第一TSV；
第二路径，其包含所述第二TSV；
第一充电电路，其经配置以对所述第一路径进行充电；
第二充电电路，其经配置以对所述第二路径进行充电；
第一放电电路，其经配置以对所述第一路径进行放电；
第二放电电路，其经配置以对所述第二路径进行放电；及
比较器电路，其经配置以将所述第一路径的电位与所述第二路径的电位进行比较。
2.根据权利要求1所述的设备，其中所述第一充电电路及所述第二充电电路经配置以同时对所述第一路径及所述第二路径进行充电。
3.根据权利要求1所述的设备，其中所述第一放电电路及所述第二放电电路经配置以同时对所述第一路径及所述第二路径进行放电。
4.根据权利要求1所述的设备，其进一步包括第二半导体芯片，所述第一半导体芯片堆叠于所述第二半导体芯片上，
其中所述第一放电电路及所述第二放电电路形成于所述第二半导体芯片上。
5.根据权利要求4所述的设备，
其中所述第一半导体芯片为存储器核心芯片，且
其中所述第二半导体芯片为接口芯片。
6.根据权利要求5所述的设备，其进一步包括堆叠于所述第一半导体芯片及所述第二半导体芯片上的第三半导体芯片，
其中所述第一充电电路及所述第二充电电路形成于所述第三半导体芯片上。
7.根据权利要求6所述的设备，其中所述第三半导体芯片为另一存储器核心芯片。
8.根据权利要求1所述的设备，其中所述第二路径包含串联连接到所述第二TSV的虚设电阻器电路。
9.根据权利要求8所述的设备，其中所述虚设电阻器电路包含并联连接的多个电阻器元件。
10.根据权利要求1所述的设备，其进一步包括穿透所述第一半导体芯片的第三TSV，
其中所述第二路径包含并联连接的所述第二TSV及所述第三TSV。
11.一种设备，其包括
多个第一半导体芯片，其彼此上下地堆叠，所述多个第一半导体芯片包含各自通过所述多个第一半导体芯片的第一路径及第二路径；及
接口芯片，其堆叠于所述多个第一半导体芯片上，使得所述接口芯片耦合到所述第一路径及所述第二路径的第一端中的每一者，所述接口芯片经配置以控制：
用第一电压来对所述第一路径及所述第二路径的第二端中的每一者进行充电；及
在用所述第一电压来对所述第一路径及所述第二路径的第二端中的每一者进行充电之后，将所述第一路径与所述第二路径的所述第一端的电位进行比较。
12.根据权利要求11所述的设备，其中所述接口芯片经配置以控制对所述第一路径及所述第二路径的所述第一端中的每一者进行放电。
13.根据权利要求12所述的设备，其中所述接口芯片经配置以在第一周期期间控制对所述第一路径及所述第二路径的所述第一端中的每一者进行放电且在所述第一周期之后的第二周期期间控制对所述第一路径及所述第二路径的所述第二端中的每一者进行充电。
14.根据权利要求13所述的设备，其中所述接口芯片经配置以在所述第二周期期间控制将所述第一路径与所述第二路径的所述第一端的电位进行比较。
15.根据权利要求14所述的设备，其中所述接口芯片经配置以在所述第二周期期间停止对所述第一路径及所述第二路径的所述第一端中的每一者进行放电。
16.根据权利要求11所述的设备，其中在无不良连接的情况下，所述第二路径具有比所述第一路径高的电阻或电容。
17.根据权利要求16所述的设备，其中在具有不良连接的情况下，所述第二路径具有比所述第一路径低的电阻或电容。
18.根据权利要求11所述的设备，其进一步包括第二半导体芯片，所述第二半导体芯片堆叠于所述多个第一半导体芯片上，使得所述多个第一半导体芯片夹在所述接口芯片与所述第二半导体芯片之间，
其中所述第一路径及所述第二路径的所述第二端中的每一者位于所述第二半导体芯片处。
19.一种设备，其包括：
半导体芯片；
多个第一TSV，其穿透所述半导体芯片；
第二TSV，其穿透所述半导体芯片；
第一电路，其经配置以选择所述多个第一TSV中的一者；
第二电路，其经配置以响应于第一时序信号而将第一电位施加到所述第一TSV中的所述选定一者及所述第二TSV；
第三电路，其经配置以响应于第二时序信号而将不同于所述第一电位的第二电位施加到所述第一TSV中的所述选定一者及所述第二TSV；及
第四电路，其经配置以将所述第一TSV中的所述选定一者的电位与所述第二TSV的电位进行比较。
20.根据权利要求19所述的设备，
其中所述多个第一TSV以矩阵形式进行布置，且
其中所述第一电路包含：
多个行选择线，其中的每一者被共同地指派给在行方向上进行布置的所述第一TSV中的两者或多于两者；
多个列选择线，其中的每一者被共同地指派给在列方向上进行布置的所述第一TSV中的两者或多于两者；
行选择电路，其经配置以激活所述行选择线中的一者；及
列选择电路，其经配置以激活所述列选择线中的一者。
CN202010952553.2A 2019-09-19 2020-09-11 具有复制路径的穿硅通孔检查电路 Pending CN112530502A (zh)

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