CN112510975A - Method and system for improving PWM precision of accelerator power supply - Google Patents
Method and system for improving PWM precision of accelerator power supply Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/081—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters wherein the phase of the control voltage is adjustable with reference to the AC source
- H02M1/082—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters wherein the phase of the control voltage is adjustable with reference to the AC source with digital control
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Abstract
The invention relates to a method and a system for improving the PWM precision of an accelerator power supply, which are characterized by comprising the following steps: 1) dividing the PWM wave adjustment of the accelerator power supply into a digital regulator comparison value integer part adjustment and a digital regulator comparison value decimal part adjustment; 2) under the condition that the period of a PWM wave is not changed, the duration time of high and low levels is changed by comparing a sawtooth wave generated by a counter with a comparison value output by a digital regulator, and the PWM wave is generated; 3) the dynamic phase shift of the voltage control oscillator in the FPGA phase-locked loop is used for phase shifting the generated counting clock of the PWM wave, adjusting the decimal part of a comparison value output by the digital regulator, further adjusting the duty ratio of the PWM wave and completing the adjustment of the PWM wave of the accelerator power supply.
Description
Technical Field
The invention relates to a method and a system for improving the precision of a power supply PWM (pulse width modulation) of an accelerator, belonging to the field of pulse width modulation.
Background
Currently, the generation method of digital power supply PWM wave in the prior art is generally adjusted by comparing the sawtooth wave generated by the counter with the comparison value generated by the digital regulator, as shown in fig. 1, for the principle of PWM wave generation, in the figure, "SW _ num _ in" represents the period of the PWM wave, i.e. the maximum output of the comparison counter, and is determined by the switching frequency of the power supply, and "PWM _ num _ in" represents the low level holding time of the PWM wave, i.e. the comparison value generated by the digital regulator, and determines the duty ratio of the PWM wave. When the output of the comparison counter is smaller than the comparison value generated by the digital regulator, the PWM wave is in a low state, when the output of the comparison counter is greater than the comparison value generated by the digital regulator, the PWM wave is in a high state, and when the next period of the sawtooth wave starts, the PWM wave returns to the low state, as can be seen from fig. 1, the period of the PWM wave is determined by the maximum output of the comparison counter, and the duty ratio of the PWM wave is determined by the difference between the maximum output of the comparison counter and the comparison value output by the digital regulator. In the currently adopted method, the comparison value output by the digital regulator is a single floating point number, the comparison value output by the comparison counter is an integer, the decimal part of the comparison value output by the digital regulator is abandoned at present, only the integer part is taken to be compared with the integer value output by the comparison counter, so that the loss of the PWM precision is caused, and the precision of the adjustment of the PWM duty ratio mainly depends on the frequency of a clock used by the counter.
At present, in the prior art, two methods are mainly used to improve the precision of PWM waves, the first method is a dual PWM modulation method, as shown in fig. 2, and the second method is an interpolation method, as shown in fig. 3. In the dual PWM modulation method, the modulation accuracy is affected by the low frequency PWM accuracy, i.e. the low frequency PWM accuracy is the minimum accuracy of the method; interpolation involves the use of digital programmable delay devices, which greatly increases the difficulty of hardware implementation.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a method and system for improving the PWM accuracy of an accelerator power supply without requiring any additional hardware on the premise of meeting the accuracy.
In order to achieve the purpose, the invention adopts the following technical scheme: a method for improving the PWM accuracy of an accelerator power supply, comprising:
1) dividing the PWM wave adjustment of the accelerator power supply into a digital regulator comparison value integer part adjustment and a digital regulator comparison value decimal part adjustment;
2) under the condition that the period of a PWM wave is not changed, the duration time of high and low levels is changed by comparing a sawtooth wave generated by a counter with a comparison value output by a digital regulator, and the PWM wave is generated;
3) the dynamic phase shift of the voltage control oscillator in the FPGA phase-locked loop is used for performing phase shift on the generated counting clock of the PWM wave, adjusting the decimal part of a comparison value output by the digital regulator, further adjusting the duty ratio of the PWM wave and completing the adjustment of the PWM wave of the accelerator power supply.
Further, the specific process of step 3) is as follows:
3.1) determining whether the duty ratio of the generated PWM wave is more than 50%, if so, entering a step 3.2); otherwise, entering step 3.7);
3.2) determining whether the decimal part of the comparison value output by the digital regulator is less than 0.5 minimum count value, if so, entering the step 3.3); otherwise, go to step 3.12);
3.3) dividing the decimal part of the comparison value of the digital regulator into n steps of m picoseconds according to the counting clock frequency of the PWM wave, wherein each m picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.4);
3.4) enabling the dynamic phase shift of the phase-locked loop in the forward direction, recording the number of the phase shift plus 1, and entering the step 3.5);
3.5) when one phase shift of the phase-locked loop is finished, entering step 3.4) until the recorded phase shift times reach n, entering step 3.6);
3.6) when the falling edge of the PWM wave comes, resetting the phase-locked loop to complete the adjustment of the fractional part of the comparison value of the digital regulator;
3.7) determining whether the decimal part of the comparison value output by the digital regulator is less than 0.5 minimum count value, if so, entering a step 3.8); otherwise, go to step 3.16);
3.8) dividing the decimal part of the comparison value of the digital regulator into n steps of m picoseconds according to the counting clock frequency of the PWM wave, wherein each m picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.9);
3.9) reversely enabling the dynamic phase shift of the phase-locked loop, recording the number of the phase shift plus 1, and entering the step 3.10);
3.10) when one phase shift of the phase-locked loop is finished, entering step 3.9) until the recorded phase shift times reach n, entering step 3.11);
3.11) when the rising edge of the PWM wave comes, resetting the phase-locked loop to complete the adjustment of the fractional part of the comparison value of the digital regulator;
3.12) rounding off the decimal part of the comparison value of the digital regulator according to the counting clock frequency of the PWM wave, dividing the rounded decimal part into n steps of m picoseconds, wherein each m picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.13);
3.13) reversely enabling the dynamic phase shift of the phase-locked loop, recording the number of the phase shifts plus 1, and entering the step 3.14);
3.14) when one phase shift of the phase-locked loop is finished, entering step 3.13) until the recorded phase shift times reach n, entering step 3.15);
3.15) when the falling edge of the PWM wave comes, resetting the phase-locked loop to complete the adjustment of the fractional part of the comparison value of the digital regulator;
3.16) rounding off the decimal part of the comparison value of the digital regulator according to the counting clock frequency of the PWM wave, dividing the rounded decimal part into n steps of m picoseconds, wherein each m picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.17);
3.17) enabling the dynamic phase shift of the phase-locked loop in the forward direction, recording the number of the phase shifts and adding 1, and entering the step 3.18);
3.18) when one phase shift of the phase-locked loop is finished, entering step 3.17) until the recorded phase shift times reach n, entering step 3.19);
3.19) when the rising edge of the PWM wave comes, resetting the phase-locked loop to complete the adjustment of the fractional part of the comparison value of the digital regulator.
Further, m in the step 3) is 18.
Further, the rounding in steps 3.12) and 3.16) is to add 1 to the integer part of the digital modifier comparison value and divide the value of 1 minus the fractional part of the digital modifier comparison value into n steps of 18 picoseconds.
A system for improving accuracy of PWM of an accelerator power supply, comprising:
the dividing module is used for dividing the PWM wave adjustment of the accelerator power supply into digital regulator comparison value integer part adjustment and digital regulator comparison value decimal part adjustment;
the PWM wave generation module is used for generating PWM waves by changing the duration time of high and low levels through comparing a sawtooth wave generated by the counter with a comparison value output by the digital regulator under the condition that one PWM wave period is not changed;
and the PWM wave adjusting module is used for phase shifting the generated counting clock of the PWM wave through the dynamic phase shift of the voltage control oscillator in the FPGA phase-locked loop, adjusting the decimal part of the comparison value output by the digital regulator, further adjusting the duty ratio of the PWM wave and finishing the adjustment of the PWM wave of the accelerator power supply.
A processor comprising computer program instructions, wherein the computer program instructions, when executed by the processor, are adapted to implement the steps corresponding to the above-described method for improving the accuracy of PWM of an accelerator power supply.
A computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, are for implementing the corresponding steps of the above-described method for improving the accuracy of PWM of an accelerator power supply.
Due to the adoption of the technical scheme, the invention has the following advantages: the invention utilizes the dynamic phase-shifting function of the phase-locked loop to adjust the decimal part of the comparison value output by the digital regulator, can improve the precision of the PWM wave duty ratio, and the minimum precision can reach about 18 picoseconds, so that the output of the accelerator power supply is easier to approach the given current value, the time required by dynamic adjustment is reduced, and the invention can be widely applied to the field of pulse width modulation.
Drawings
FIG. 1 is a schematic diagram illustrating the generation principle of PWM wave in the prior art, wherein "SW _ num _ in" represents the period of PWM wave; "PWM _ num _ in" represents a PWM wave low level holding time, the abscissa is time, and the ordinate is a comparison value;
FIG. 2 is a schematic diagram of a dual PWM modulation method in the prior art;
FIG. 3 is a schematic diagram of a prior art interpolation method;
FIG. 4 is a flow chart of the method of the present invention;
FIG. 5 is a schematic diagram of a state machine of an FPGA performing multiple adjustments in an embodiment of the present invention.
Detailed Description
The present invention is described in detail below with reference to the attached drawings. It is to be understood, however, that the drawings are provided solely for the purposes of promoting an understanding of the invention and that they are not to be construed as limiting the invention.
The invention provides a method for improving the PWM precision of an accelerator power supply, which comprises the following steps:
1) the PWM wave adjustment of the accelerator power supply is divided into digital regulator comparison value integer part adjustment and digital regulator comparison value decimal part adjustment.
2) Under the condition that one PWM wave period is not changed, the duration time of high and low levels is changed by comparing a sawtooth wave generated by a counter with a comparison value output by a digital regulator, and the PWM wave is generated.
3) As shown in fig. 4, the dynamic phase shift of the voltage controlled oscillator in the FPGA (field programmable gate array) phase-locked loop is used to shift the phase of the generated PWM wave counting clock, and adjust the fractional part of the comparison value output by the digital regulator, so as to adjust the duty ratio of the PWM wave, thereby completing the adjustment of the accelerator power supply PWM wave, specifically:
3.1) determining whether the duty ratio of the generated PWM wave is more than 50%, if so, entering a step 3.2); otherwise, step 3.7) is entered.
3.2) determining whether the decimal part of the comparison value output by the digital regulator is less than 0.5 minimum count value, if so, entering the step 3.3); otherwise, step 3.12) is entered.
3.3) dividing the fractional part of the comparison value of the digital regulator into n steps of 18 picoseconds according to the counting clock frequency of the PWM wave, wherein each 18 picoseconds corresponds to one phase shift of the phase-locked loop, and entering the step 3.4).
Because the minimum step size of the dynamic phase shift of the phase-locked loop is determined by the voltage-controlled oscillator, the minimum step size of each step of the dynamic phase shift is one fiftieth of the period of the voltage-controlled oscillator, the frequency of the voltage-controlled oscillator adopted in the invention is 1000MHZ, so the minimum adjustment step size is about 18 picoseconds, namely the adjustment of the fractional part of the PWM wave is divided into n 18 picoseconds.
3.4) enabling the dynamic phase shift of the phase-locked loop in the forward direction, recording the number of phase shifts plus 1, and entering the step 3.5).
3.5) when one phase shift of the phase-locked loop is finished, step 3.4) is entered, and step 3.6) is entered until the number of recorded phase shifts reaches n.
3.6) when the falling edge of the PWM wave comes, resetting the phase-locked loop, completing the adjustment of the fractional part of the comparison value of the digital regulator, and entering the step 3.20).
3.7) determining whether the decimal part of the comparison value output by the digital regulator is less than 0.5 minimum count value, if so, entering a step 3.8); otherwise, step 3.16) is entered.
3.8) dividing the fractional part of the comparison value of the digital regulator into n steps of 18 picoseconds according to the counting clock frequency of the PWM wave, wherein each 18 picoseconds corresponds to one phase shift of the phase-locked loop, and entering the step 3.9).
3.9) reverse enabling the dynamic phase shift of the phase-locked loop and recording the number of phase shifts plus 1, go to step 3.10).
3.10) when one phase shift of the phase locked loop is completed, step 3.9) is entered, and step 3.11) is entered until the number of phase shifts recorded reaches n).
3.11) when the rising edge of the PWM wave comes, resetting the phase-locked loop, completing the adjustment of the fractional part of the comparison value of the digital regulator, and entering the step 3.20).
3.12) rounding off the decimal part of the comparison value of the digital regulator according to the counting clock frequency of the PWM wave, dividing the rounded decimal part into n steps of 18 picoseconds, wherein each 18 picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.13).
3.13) reverse enabling the dynamic phase shift of the phase locked loop and recording the number of phase shifts plus 1, go to step 3.14).
3.14) when one phase shift of the phase locked loop is completed, step 3.13) is entered, and step 3.15) is entered until the number of phase shifts recorded reaches n).
3.15) when the falling edge of the PWM wave comes, resetting the phase-locked loop, completing the adjustment of the fractional part of the comparison value of the digital regulator, and entering the step 3.20).
3.16) rounding off the decimal part of the comparison value of the digital regulator according to the counting clock frequency of the PWM wave, dividing the rounded decimal part into n steps of 18 picoseconds, wherein each 18 picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.17).
3.17) forward enable dynamic phase shift of the phase locked loop and record the number of phase shifts plus 1, go to step 3.18).
3.18) when one phase shift of the phase locked loop is completed, step 3.17) is entered, until the number of phase shifts recorded reaches n, step 3.19) is entered.
3.19) when the rising edge of the PWM wave comes, resetting the phase-locked loop, completing the adjustment of the fractional part of the comparison value of the digital regulator, and entering the step 3.20).
3.20) is finished.
In the step 3), the FPGA may adopt a core chip XILINX kit-7 series FPGA based on a power digital controller.
As shown in fig. 5, a schematic diagram of a state machine of an FPGA is shown, for example: a PWM wave with a count clock frequency of 100MHZ and a period of 100 microseconds needs to be increased by 4.001% in duty cycle, which means that the time for the PWM wave to go high is increased by 4001 nanoseconds. Since the minimum count value corresponds to 10 ns, it is necessary to increase the comparison value by 400 ns and then adjust the fractional part of the PWM wave by 1 ns through the dynamic phase shift of the phase-locked loop, i.e., adjust the fractional part of the PWM wave by 1 ns in the positive direction (right shift), and it takes about 55 times to complete the phase adjustment according to the method mentioned in the background art.
By the dynamic phase shift of the phase locked loop, which requires a certain time to complete when adjusting the clock phase of the PWM wave, according to the method of the present invention, when adjusting the fractional part of the digital regulator comparison value for the duration of the high level, the adjustment will be completed before the falling edge, and in some cases, the adjustment will not be completed before the falling edge, resulting in some deviation of the result from what is expected. In order to avoid the situation, the invention adopts a mode of rounding the fractional part of the comparison value of the digital regulator, namely when the fractional part of the comparison value of the digital regulator is adjusted to be more than 0.5 minimum count value, adding 1 to the integer part of the PWM wave, changing the adjustment direction of the fractional part into the original opposite direction, and changing the adjustment value into 1 to subtract the fractional part of the original comparison value; and the adjustment of the fractional part of the comparator value of the digital regulator to be less than 0.5 minimum count value will not change. For example, the above-mentioned PWM wave having a count clock frequency of 100MHZ and a period of 100 microseconds, the value of the fractional part is 0.1, and therefore, it is not necessary to round it. If the duty cycle is simply desired to be increased by 3.999%, the high time of the PWM wave will be increased by 3999 ns, if the fractional part of the adjustment is 9 ns by the method disclosed in the prior art, which is too large, and the adjustment cannot be completed before the falling edge of the PWM comes, whereas by the method of the present invention, the comparison value generated by the digital regulator in fig. 1 will be increased by 400, the dynamic phase shift will be used to compensate for the extra 1 ns, and since the original direction of adjustment of the PWM wave is forward (to the right), the fractional part of the adjustment will be adjusted in the opposite direction, i.e., to the left by 1 ns.
There is also a case where the high level duration of the PWM wave is not sufficient to complete the adjustment, which means that another way is needed to adjust a PWM wave of a low duty ratio. In order to solve the problem, the invention adopts the technical scheme that when the duty ratio of the PWM wave is less than 50%, the dynamic phase shift adjustment is placed at the low level part of the PWM wave, and the duty ratio of the PWM wave is changed by changing the position of the rising edge of the PWM wave. Similar to the previous method, the high level duration or the low level holding time is changed without adjusting the period to adjust the duty ratio of the PWM wave. There are differences, however, in that a positive adjustment of the falling edge results in an increase in the duration of the high level, while a negative adjustment of the rising edge also results in an increase in the duration of the high level. Therefore, when it is desired to reduce the duty cycle, more low-level hold time is required, and vice versa. For example: when the duty cycle of the PWM wave is less than 50%, the integer part of the adjustment is the same, and the fractional part of the adjustment is put in the low level holding time of the PWM wave, the direction will be the opposite direction of the original adjustment.
Based on the method for improving the precision of the PWM of the accelerator power supply, the present invention further provides a system for improving the precision of the PWM of the accelerator power supply, including:
the dividing module is used for dividing the PWM wave adjustment of the accelerator power supply into digital regulator comparison value integer part adjustment and digital regulator comparison value decimal part adjustment;
the PWM wave generation module is used for generating PWM waves by changing the duration time of high and low levels through comparing a sawtooth wave generated by the counter with a comparison value output by the digital regulator under the condition that one PWM wave period is not changed;
and the PWM wave adjusting module is used for phase shifting the generated counting clock of the PWM wave through the dynamic phase shift of the voltage control oscillator in the FPGA phase-locked loop, adjusting the decimal part of the comparison value output by the digital regulator, further adjusting the duty ratio of the PWM wave and finishing the adjustment of the PWM wave of the accelerator power supply.
The invention also provides a processor comprising computer program instructions, wherein the computer program instructions, when executed by the processor, are used for implementing the corresponding steps of the method for improving the precision of the PWM of the accelerator power supply.
The present invention also provides a computer readable storage medium, on which computer program instructions are stored, wherein the computer program instructions, when executed by a processor, are configured to implement the steps corresponding to the method for improving the accuracy of the PWM of the accelerator power supply.
The above embodiments are only used for illustrating the present invention, and the structure, connection mode, manufacturing process, etc. of the components may be changed, and all equivalent changes and modifications performed on the basis of the technical solution of the present invention should not be excluded from the protection scope of the present invention.
Claims (7)
1. A method for improving the PWM accuracy of an accelerator power supply, comprising:
1) dividing the PWM wave adjustment of the accelerator power supply into a digital regulator comparison value integer part adjustment and a digital regulator comparison value decimal part adjustment;
2) under the condition that the period of a PWM wave is not changed, the duration time of high and low levels is changed by comparing a sawtooth wave generated by a counter with a comparison value output by a digital regulator, and the PWM wave is generated;
3) the dynamic phase shift of the voltage control oscillator in the FPGA phase-locked loop is used for performing phase shift on the generated counting clock of the PWM wave, adjusting the decimal part of a comparison value output by the digital regulator, further adjusting the duty ratio of the PWM wave and completing the adjustment of the PWM wave of the accelerator power supply.
2. The method for improving the PWM accuracy of the accelerator power supply according to claim 1, wherein the specific process of step 3) is:
3.1) determining whether the duty ratio of the generated PWM wave is more than 50%, if so, entering a step 3.2); otherwise, entering step 3.7);
3.2) determining whether the decimal part of the comparison value output by the digital regulator is less than 0.5 minimum count value, if so, entering the step 3.3); otherwise, go to step 3.12);
3.3) dividing the decimal part of the comparison value of the digital regulator into n steps of m picoseconds according to the counting clock frequency of the PWM wave, wherein each m picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.4);
3.4) enabling the dynamic phase shift of the phase-locked loop in the forward direction, recording the number of the phase shift plus 1, and entering the step 3.5);
3.5) when one phase shift of the phase-locked loop is finished, entering step 3.4) until the recorded phase shift times reach n, entering step 3.6);
3.6) when the falling edge of the PWM wave comes, resetting the phase-locked loop to complete the adjustment of the fractional part of the comparison value of the digital regulator;
3.7) determining whether the decimal part of the comparison value output by the digital regulator is less than 0.5 minimum count value, if so, entering a step 3.8); otherwise, go to step 3.16);
3.8) dividing the decimal part of the comparison value of the digital regulator into n steps of m picoseconds according to the counting clock frequency of the PWM wave, wherein each m picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.9);
3.9) reversely enabling the dynamic phase shift of the phase-locked loop, recording the number of the phase shift plus 1, and entering the step 3.10);
3.10) when one phase shift of the phase-locked loop is finished, entering step 3.9) until the recorded phase shift times reach n, entering step 3.11);
3.11) when the rising edge of the PWM wave comes, resetting the phase-locked loop to complete the adjustment of the fractional part of the comparison value of the digital regulator;
3.12) rounding off the decimal part of the comparison value of the digital regulator according to the counting clock frequency of the PWM wave, dividing the rounded decimal part into n steps of m picoseconds, wherein each m picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.13);
3.13) reversely enabling the dynamic phase shift of the phase-locked loop, recording the number of the phase shifts plus 1, and entering the step 3.14);
3.14) when one phase shift of the phase-locked loop is finished, entering step 3.13) until the recorded phase shift times reach n, entering step 3.15);
3.15) when the falling edge of the PWM wave comes, resetting the phase-locked loop to complete the adjustment of the fractional part of the comparison value of the digital regulator;
3.16) rounding off the decimal part of the comparison value of the digital regulator according to the counting clock frequency of the PWM wave, dividing the rounded decimal part into n steps of m picoseconds, wherein each m picoseconds corresponds to one phase shift of a phase-locked loop, and entering the step 3.17);
3.17) enabling the dynamic phase shift of the phase-locked loop in the forward direction, recording the number of the phase shifts and adding 1, and entering the step 3.18);
3.18) when one phase shift of the phase-locked loop is finished, entering step 3.17) until the recorded phase shift times reach n, entering step 3.19);
3.19) when the rising edge of the PWM wave comes, resetting the phase-locked loop to complete the adjustment of the fractional part of the comparison value of the digital regulator.
3. The method for improving the PWM accuracy of an accelerator power supply according to claim 2, wherein m in said step 3) is 18.
4. A method for improving the accuracy of the PWM of the accelerator power supply as claimed in claim 2, wherein said rounding in steps 3.12) and 3.16) is performed by adding 1 to the integer part of the digital regulator comparison value and dividing the value of 1 minus the fractional part of the digital regulator comparison value into n steps of 18 picoseconds.
5. A system for improving accuracy of PWM of an accelerator power supply, comprising:
the dividing module is used for dividing the PWM wave adjustment of the accelerator power supply into digital regulator comparison value integer part adjustment and digital regulator comparison value decimal part adjustment;
the PWM wave generation module is used for generating PWM waves by changing the duration time of high and low levels through comparing a sawtooth wave generated by the counter with a comparison value output by the digital regulator under the condition that one PWM wave period is not changed;
and the PWM wave adjusting module is used for phase shifting the generated counting clock of the PWM wave through the dynamic phase shift of the voltage control oscillator in the FPGA phase-locked loop, adjusting the decimal part of the comparison value output by the digital regulator, further adjusting the duty ratio of the PWM wave and finishing the adjustment of the PWM wave of the accelerator power supply.
6. A processor characterized by comprising computer program instructions, wherein the computer program instructions, when executed by the processor, are adapted to implement the steps corresponding to the method for improving the accuracy of PWM of an accelerator power supply of any of claims 1 to 4.
7. A computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, are configured to implement the corresponding steps of the method for improving the PWM accuracy of an accelerator power supply according to any one of claims 1 to 4.
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| CN114221642A (en) * | 2022-02-22 | 2022-03-22 | 浙江地芯引力科技有限公司 | PWM wave generation and duty ratio control method, device, timer and equipment |
| CN114724501A (en) * | 2022-03-23 | 2022-07-08 | 厦门凌阳华芯科技有限公司 | LED display and pulse width modulation system thereof |
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