CN112416832A - Communication system based on MIPS framework processor - Google Patents

Communication system based on MIPS framework processor Download PDF

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Publication number
CN112416832A
CN112416832A CN202011231577.5A CN202011231577A CN112416832A CN 112416832 A CN112416832 A CN 112416832A CN 202011231577 A CN202011231577 A CN 202011231577A CN 112416832 A CN112416832 A CN 112416832A
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China
Prior art keywords
interface module
spi interface
data
microsystem
module
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刘振
叶菲
周华
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Guanghua Lingang Engineering Application Technology Research and Development Shanghai Co Ltd
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Guanghua Lingang Engineering Application Technology Research and Development Shanghai Co Ltd
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Priority to CN202011231577.5A priority Critical patent/CN112416832A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention discloses a communication system based on an MIPS framework processor. The system comprises: the first micro system comprises a first UART0 interface module and a first SPI interface module, and the first UART0 interface module is used for interacting with first peripheral terminal equipment; and the second micro system comprises a second SPI interface module, and the second SPI interface module is connected with the first SPI interface module and used for receiving the data sent by the first SPI interface module so as to realize data transmission between the first micro system and the second micro system. According to the invention, communication and data storage between two independent microsystems can be realized, and the terminal equipment transmits data to the second microsystem through the connected first microsystem to realize the functions of the microsystem (such as data acquisition or data storage), thereby improving the efficiency of the whole system.

Description

Communication system based on MIPS framework processor
Technical Field
The invention relates to the technical field of communication, in particular to a communication system based on an MIPS framework processor.
Background
With the progress of the integrated circuit manufacturing process, the integration level on the same chip is greatly improved. The development of the embedded flash memory process enables the memory system to be completely realized on the same chip without the PCB-level memory support. These conditions allow a 32-bit microprocessor system to run on a single chip, forming a separate microcomputer system, plus the necessary peripheral modules, forming a micro-control system.
At present, most of domestic microprocessors with ARM architectures are adopted, a PC end controls a CPU to execute some commands, such as data acquisition or data storage, and then the CPU controls corresponding functional modules (such as sensors) through corresponding programs to realize the functions of the commands.
In order to solve the problems in the prior art, the invention provides a communication system based on an MIPS architecture processor.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to solve the problems in the prior art, the invention provides a communication system based on an MIPS architecture processor, which comprises:
the first micro system comprises a first UART0 interface module and a first SPI interface module, and the first UART0 interface module is used for interacting with first peripheral terminal equipment;
and the second micro system comprises a second SPI interface module, and the second SPI interface module is connected with the first SPI interface module and used for receiving the data sent by the first SPI interface module so as to realize data transmission between the first micro system and the second micro system.
Illustratively, at least two of the second microsystems are included, wherein the second SPI interface modules of at least two of the at least two microsystems are connected with the first SPI interface module of the same first microsystem.
Illustratively, the first microsystem further comprises a first processor module, the first processor module being configured to detect an operating status of the first UART0 interface module and to control data transmission between the first UART0 interface module and the first peripheral terminal device according to the operating status, the operating status including a data transmission status and an idle status;
when the first UART0 interface module is in the data transmission state, controlling the first UART0 interface module to suspend receiving data of the first peripheral terminal device;
when the first UART0 interface module is in the idle state, the first UART0 interface module is controlled to receive data of the first peripheral terminal device.
Illustratively, the first processor module further detects a working state of the first SPI interface module, and controls the first SPI interface module to send data to the second SPI interface module according to the working state, where the working state includes a data transmission state and an idle state;
when the first SPI interface module is in the data transmission state, controlling the first SPI interface module to suspend sending data;
and when the first SPI interface module is in an idle state, controlling the first SPI interface module to send data.
Exemplarily, the second microsystem further comprises a second processor module, the second processor module is configured to detect a working state of the second SPI interface module and control the second SPI interface module to receive data sent by the first SPI interface module according to the working state, and the working state includes a data transmission state and an idle state;
when the second SPI interface module is in the data transmission state, controlling the second SPI interface module to suspend receiving data;
and when the second SPI interface module is in an idle state, controlling the second SPI interface module to receive data.
Illustratively, the second microsystem further comprises a storage module to store the data.
Illustratively, the memory module is a flash memory module.
Illustratively, the second processor module also controls read and write operations of the flash memory module.
Illustratively, the second microsystem further comprises a second UART0 interface module, the second UART0 interface module being configured to interact with a second peripheral terminal device.
Illustratively, the ISA architecture of the first and second microsystems employs 32-bit MIPS-I.
According to the communication system based on the MIPS framework processor, communication and data storage between two independent microsystems can be realized, the terminal equipment transmits data to the second microsystem through the connected first microsystem, and functions of the microsystem (such as data collection or data storage) are realized, so that the efficiency of the whole system is improved. Meanwhile, one micro system can transmit data to more than one micro system at the same time through the SPI interface module, so that more complex functions can be realized while the system efficiency is improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 is a schematic structural diagram of a MIPS architecture processor-based communication system according to an embodiment of the present invention;
fig. 2 shows a schematic flow diagram of a data transfer process of a MIPS architecture processor based communication system according to one embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
In order to provide a thorough understanding of the present invention, a detailed description will be provided in the following description to illustrate the MIPS architecture processor-based communication system of the present invention. It is apparent that the implementation of the present invention is not limited to the specific details familiar to a person skilled in the art of communication technology. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same elements are denoted by the same reference numerals, and thus the description thereof will be omitted.
In order to solve the problems in the prior art, the invention provides a communication system based on an MIPS architecture processor, which comprises:
the first micro system comprises a first UART0 interface module and a first SPI interface module, and the first UART0 interface module is used for interacting with first peripheral terminal equipment;
and the second micro system comprises a second SPI interface module, and the second SPI interface module is connected with the first SPI interface module and is used for transmitting data between the first micro system and the second micro system.
A MIPS architecture processor-based communication system according to the present invention is exemplarily illustrated with reference to fig. 1 and 2. Fig. 1 is a schematic structural diagram of a communication system based on a MIPS architecture processor according to an embodiment of the present invention, and fig. 2 is a schematic flow chart illustrating a data transmission process of the communication system based on the MIPS architecture processor according to an embodiment of the present invention.
As shown in fig. 1, a MIPS architecture processor-based communication system according to the present invention includes a first microsystem 1 and a second microsystem 2.
The first microsystem 1 and the second microsystem 2 may be circuit boards (development boards) for embedded system development, on which various devices may be disposed, including a series of hardware components such as a central processing unit, a memory, an input device, a data path/bus, and an external resource interface.
With continued reference to fig. 1, the first microsystem 1 comprises a first UART0 interface module and a first SPI interface module, said first UART0 interface module being adapted to interact with the first peripheral terminal device 3.
Illustratively, the terminal includes a data acquisition terminal and/or a data processing terminal.
Illustratively, the data acquisition terminal comprises a meter, a controller and the like for acquiring data, such as an electric energy metering and acquiring device and a gas consumption acquiring device.
Illustratively, data processing terminals include terminals for processing data, such as data processors, including but not limited to computers and the like.
The UART interface module is a universal serial bus and is used for asynchronous communication, bidirectional communication and full duplex transmission and reception. The UART converts parallel data into serial data to be sent out, and converts received serial data into parallel data.
The UART interface module generally adopts a UART0 interface module to communicate with a terminal device, and can communicate with a terminal device such as a computer by setting an interface level.
In one embodiment of the invention, the first peripheral terminal device 3 is a data output means, a memory storing executable instructions and a processor which, when executing the executable program instructions, causes the data output means to output data. The data output device may be a personal computing device such as a computer, tablet computer, or the like.
With continued reference to FIG. 1, the second microsystem 2 includes a second SPI interface module.
The first SPI interface module of the first microsystem 1 is connected to the second SPI interface module of the second microsystem, and is used for data transmission between the first microsystem 1 and the second microsystem 2.
SPI is an abbreviation for Serial Peripheral Interface (Serial Peripheral Interface), a high-speed, full-duplex, synchronous communication bus. Unlike the UART interface module, the SPI serial peripheral interface may also connect to and communicate with a plurality of peripheral devices simultaneously.
In this embodiment, the first microsystem and the second microsystem are configured as a circuit board (development board) developed by an embedded system, and data output and input pins are provided thereon, as shown in fig. 1, a data output pin 11(SO) and a data input pin 12(SI) are provided on the first SPI interface module of the first microsystem 1, and a data output pin 21(SO) and a data input pin 22(SI) are provided on the second SPI interface module of the second microsystem 2, and in this embodiment, data transmission between the first microsystem and the second microsystem is realized by communicating the data output pin 11(SO) on the first SPI interface module of the first microsystem 1 with the data input pin 22(SI) on the second SPI interface module of the second microsystem 2.
According to the communication system based on the MIPS framework processor, communication and data storage between two independent microsystems can be realized, the terminal equipment transmits data to the second microsystem through the connected first microsystem, and functions of the microsystem (such as data collection or data storage) are realized, so that the efficiency of the whole system is improved.
For example, when the first UART0 interface module connects the first peripheral terminal device 3 as a computer, a control command is input by the computer and sent to the first UART0 interface module, the first UART0 interface module receives the control command, the processor in the first microsystem reads the control command through the bus and loads the read data into the first SPI interface module of the first microsystem, and the data output pin 11 sent by the first SPI interface module sends the control command to the data receiving hard glue 22 of the second SPI interface module of the second microsystem, so that the control command can be transmitted and communicated between the first microsystem and the second microsystem. For example, when the second microsystem is a sensor device, data acquisition may be performed according to a control command, and when the second microsystem has a data storage function, the data storage function may be implemented, or the like.
In one example according to the present invention, at least two of the second microsystems are included, wherein the second SPI interface module of at least two of the at least two microsystems is connected to the first SPI interface module of the same first microsystem.
In the invention, a plurality of second microsystems are arranged, each second microsystem comprises a second SPI interface module, and the second SPI interface modules in the plurality of second microsystems are connected with the first SPI interface module of the same first microsystem, so that data can be transmitted to the plurality of second microsystems through the same first microsystem, the system efficiency is improved, and more complex functions can be realized when the plurality of second microsystems have different functions.
With continued reference to fig. 1, the first microsystem 1 further comprises a first processor module 13, the first processor module 13 being configured to detect an operating status of the first UART0 interface module and to control data transmission between the first UART0 interface module and the first peripheral terminal device 3 according to the operating status, the operating status including a data transmission status and an idle status;
when the first UART0 interface module is in the data transmission state, controlling the first UART0 interface module to suspend receiving data of the first peripheral terminal device 3;
when the first UART0 interface module is in the idle state, controlling the first UART0 interface module to receive data of the first peripheral terminal apparatus 3.
The first processor module 13 may be configured as a processor core, and is connected to the UART0 interface module through a data bus, and during the data transmission of the first microsystem 1, the processor core reads data from the first UART0 interface module through the bus and places the read data into a register of the processor core.
Further, for example, the first processor module 13 further detects a working state of the first SPI interface module, and controls the first SPI interface module to send data to the second SPI interface module according to the working state, where the working state includes a data transmission state and an idle state;
when the first SPI interface module is in the data transmission state, controlling the first SPI interface module to suspend sending data;
and when the first SPI interface module is in an idle state, controlling the first SPI interface module to send data.
With continued reference to fig. 1, the processor core is connected to the UART0 interface module through the data bus, and during the data transmission process of the first microsystem 1, the processor core reads data from the first UART0 interface module through the data bus and puts the read data into the register of the processor core; meanwhile, the processor core loads data to the first SPI interface module of the first microsystem 1 through the data bus, and prepares to send to the second microsystem.
Also exemplarily, the second microsystem 2 further includes a second processor module 23, where the second processor module 23 is configured to detect a working state of the second SPI interface module and control the second SPI interface module to receive data sent by the first SPI interface module according to the working state, where the working state includes a data transmission state and an idle state;
when the second SPI interface module is in the data transmission state, controlling the second SPI interface module to suspend receiving data;
and when the second SPI interface module is in an idle state, controlling the second SPI interface module to receive data.
The second processor module 23 may be configured as a processor core, and is connected to the second SPI interface module through a data bus, and in the process of receiving the data transmitted by the first microsystem 1, the processor core controls the second SPI interface module to receive the data through the bus.
In one example according to the present invention, the ISA architecture of the first and second microsystems employs 32-bit MIPS-I. By adopting 32-bit MIPS-I as an ISA framework, a user can add own instructions in a developed kernel, and modification is facilitated. In the invention, after the second SPI interface module of the second microsystem is physically connected with the second SPI interface module of the first microsystem, the functions of data transmission, data storage and the like between the first microsystem and the second microsystem are realized by editing and modifying instructions on an ISA framework of 32-bit MIPS-I.
In one example according to the present invention, as shown in fig. 1, a storage module 24 is provided in the second microsystem 2, and when the second SPI interface module of the second microsystem 2 receives data from the first microsystem 1, the data is stored in the storage module 24.
It is to be understood that the arrangement of the memory module 24 in the second microsystem 2 for implementing the memory function is merely exemplary, and it will be understood by those skilled in the art that the second microsystem 2 is arranged as any system unit having a logic function for implementing the present invention. For example, the second microsystem 2 includes a sensor for collecting data, a processing unit having an arithmetic function, and the like, and is not limited thereto.
In one example according to the present invention, the memory module 24 is configured as a flash memory module so that the second microsystem can implement multiple read and write operations.
Illustratively, the second processor module 24 also controls read and write operations of the flash memory module.
In one embodiment of the invention, the flash module write operation is maintained at a system clock frequency of 6MHz, i.e., maintaining a baud rate of 19200, so that 0x1000 needs to be written to SYS _ CTL2_ REG (1f800702) to set the baud rate before the write operation.
Flash module erasure is accomplished by calling special system functions. In a C language implementation, the erasing of the flash memory module can be implemented by jumping to the address through a function pointer. The contents of 1K byte are erased by writing arbitrary data into 0x1010- [ addr ]. The address of the system function OS _ EfErease for erasing the flash memory module is: 0x2f 8.
The writing operation of the Flash memory module is completed by calling a special system function, and in the C language implementation, the writing operation can be executed by jumping to the system function address 0x2C4 through a function pointer to realize the writing of Flash. It should be noted that a word has four bytes, the address of a word must match the address of one of the 4 bytes it contains, and the addresses of successive words differ by 4. Therefore, the address should be increased by 4 when the next character is stored.
The read operation of the flash memory module maintains 9600 baud rate, so it is necessary to write 0x00 to SYS _ CTL2_ REG (1f800702) to set the baud rate before the write operation.
The read operation of the flash memory module is similar to other memories, and the read operation of data can be completed by using a MemoryRead32 function.
The above is an exemplary description of a MIPS architecture processor based communication system according to the present invention with reference to fig. 1. It should be understood that in the above description, only the operation process of the first microsystem 1 receiving data from the first peripheral terminal device 3 and then transferring the data to the second microsystem 2 to be stored in the storage module 24 is described, the illustrated one-way transmission process of data is only an example, and those skilled in the art should understand that the data can also be transmitted in the reverse direction.
Illustratively, as shown in fig. 1, a second UART0 interface module is further disposed in the second microsystem 2 for connecting to the second peripheral terminal device 4.
As with the interaction of the first microsystem 1 with the first peripheral terminal 3, the second microsystem 2 likewise performs data transmission with the second peripheral terminal 4 via the second UART0 interface module. Likewise, the second SPI interface module in the second microsystem 2 is provided with a data output pin 21(SO pin) and a data reception pin 22(SI pin), wherein the data output pin 21 is connected to the data reception pin 12 of the first microsystem 1 to transmit data received from the second peripheral terminal device 4 through the second UART0 interface module to the first microsystem.
Similarly, as in the case of the second microsystem 2, a memory module may be provided in the first microsystem 1 for storing data received from the second microsystem 2.
In one example according to the invention, the second peripheral terminal device 4 is a display device, which may be sent to the second peripheral terminal device 4 for display by the second URAT0 after the processing module 23 of the second microsystem reads the data from the memory module 24.
A data transfer process of a MIPS architecture processor-based communication system according to one embodiment of the present invention is schematically described with reference to fig. 1 and 2. Wherein the data transmission process of the MIPS architecture processor-based communication system shown in fig. 2 is performed on the MIPS architecture processor-based communication system in fig. 1.
Referring to fig. 2, firstly, it is determined that the master device is a microsystem (a first microsystem 1 or a second microsystem 2) for sending data, in this step, the step may be performed by a peripheral terminal device (a first peripheral terminal device 3 or a second peripheral terminal device 4, such as a computer) connected to the first microsystem and the second microsystem, and when data needs to be sent through the microsystem (the first microsystem 1 or the second microsystem 2), a command is set on the peripheral terminal device connected to the microsystem to send data, for example, a command is sent through a PC connected to the first microsystem 1, and at this time, the first microsystem 1 is the master device and the second microsystem 2 is the slave device. While confirming that the master device (the first microsystem is the master device), the master device (the first microsystem 1) receives a command from the PC through the urat0, thereby turning off the urat0 interface module function and setting the SPI interface module (the first SPI interface module) of the master device (the first microsystem 1) ready for data transmission, and the corresponding slave device (the second microsystem is the slave device) turns off the urat0 function and sets the SPI interface module (the second SPI interface module) of the slave device (the second microsystem 2) ready for data reception.
As shown in fig. 2, the CS in the master device is turned on, the master device (the first processor module 13 in the first microsystem 1) performs control operation on the SPI (the first SPI interface module), controls the SPI (the first SPI interface module) to send data, calls a urat _ read function return value, acquires characters, controls the SPI (the first SPI interface module) to send data, waits for completion of the SPI (the first SPI interface module) sending task, and turns off the CS (the first processor module 13 in the first microsystem 1).
Likewise, the slave device (the second processor module 23 in the second microsystem 2) also controls the second SPI interface module to perform receiving operation; when the second SPI interface module is in the data transmission state, controlling the second SPI interface module to suspend receiving data from a first microsystem; and when the second SPI interface module finishes current data transmission, controlling the second SPI interface module to receive data from the first microsystem 1. After the data reception from the first microsystem 1 is completed, the storage and display operations are performed, which specifically include: setting the write baud rate of the flash memory module (memory module 24), erasing the flash memory module, storing data into the flash memory module space, setting the read baud rate after delaying for 10ms, and reading and printing the data from the flash memory module space.
The above is an exemplary description of the communication system based on the MIPS architecture processor according to the present invention, communication and data storage between two independent microsystems can be realized, and the terminal device transmits data to the second microsystem through the connected first microsystem, and realizes the functions of the microsystem (such as data collection or data storage), thereby improving the efficiency of the whole system. Meanwhile, one micro system can transmit data to more than one micro system at the same time through the SPI interface module, so that more complex functions can be realized while the system efficiency is improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present invention should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
The above description is only for the specific embodiment of the present invention or the description thereof, and the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A MIPS architecture processor-based communication system, comprising:
the first micro system comprises a first UART0 interface module and a first SPI interface module, and the first UART0 interface module is used for interacting with first peripheral terminal equipment;
and the second micro system comprises a second SPI interface module, and the second SPI interface module is connected with the first SPI interface module and used for receiving the data sent by the first SPI interface module so as to realize data transmission between the first micro system and the second micro system.
2. The MIPS architecture processor-based communication system of claim 1, comprising at least two of the second microsystems, wherein the second SPI interface modules of at least two of the at least two microsystems are connected with the first SPI interface module of the same first microsystem.
3. The MIPS architecture processor-based communication system of claim 1, wherein the first microsystem further comprises a first processor module, the first processor module to detect an operating state of the first UART0 interface module and to control data transmission between the first UART0 interface module and the first peripheral end device according to the operating state, the operating state including a data transmission state and an idle state;
when the first UART0 interface module is in the data transmission state, controlling the first UART0 interface module to suspend receiving data of the first peripheral terminal device;
when the first UART0 interface module is in the idle state, the first UART0 interface module is controlled to receive data of the first peripheral terminal device.
4. The MIPS architecture processor-based communication system of claim 3, wherein the first processor module further detects an operating state of the first SPI interface module, and controls the first SPI interface module to send data to the second SPI interface module according to the operating state, the operating state including a data transmission state and an idle state;
when the first SPI interface module is in the data transmission state, controlling the first SPI interface module to suspend sending data;
and when the first SPI interface module is in an idle state, controlling the first SPI interface module to send data.
5. The MIPS architecture processor-based communication system of claim 1, wherein the second microsystem further comprises a second processor module, the second processor module is configured to detect an operating status of the second SPI interface module and control the second SPI interface module to receive the data sent by the first SPI interface module according to the operating status, the operating status includes a data transmission status and an idle status;
when the second SPI interface module is in the data transmission state, controlling the second SPI interface module to suspend receiving data;
and when the second SPI interface module is in an idle state, controlling the second SPI interface module to receive data.
6. The MIPS architecture processor-based communication system of claim 4, wherein the second microsystem further comprises a memory module to store the data.
7. The MIPS architecture processor-based communication system of claim 3, wherein the memory module is a flash memory module.
8. The MIPS architecture processor-based communication system of claim 6, wherein the second processor module further controls read and write operations of the flash memory module.
9. The MIPS architecture processor-based communication system of claim 4, wherein the second microsystem further comprises a second UART0 interface module, the second UART0 interface module to interact with a second peripheral terminal device.
10. The MIPS architecture processor-based communication system of claim 9, wherein ISA architectures of the first and second microsystems employ 32-bit MIPS-I.
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