CN112187229A - High-precision pulse width modulation system and method - Google Patents

High-precision pulse width modulation system and method Download PDF

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Publication number
CN112187229A
CN112187229A CN202011166022.7A CN202011166022A CN112187229A CN 112187229 A CN112187229 A CN 112187229A CN 202011166022 A CN202011166022 A CN 202011166022A CN 112187229 A CN112187229 A CN 112187229A
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signal
phase
time delay
signals
delay
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冯珅
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Sino Wealth Microelectronics Co ltd
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Sino Wealth Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0998—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention provides a high-precision pulse width modulation system and a high-precision pulse width modulation method. Multi-phase time delay locked loop system generates M main phase signals Q based on input reference frequency signals0～QM－1And generating N time delay signals P according to the M main phase signals1～PNWherein N ═ M × S, M, N, S is an integer greater than or equal to 1; selecting N time delay signals P1～PNCompares the phase of the particular time delayed signal with the phase of the particular main phase signal of the M main phase signals, and compares the phase of the particular time delayed signal with the phase of the particular main phase signalThe comparison result is converted into a digital error signal to calibrate the output phase error of the delay signal. The PWM signal post processor selects a time delay signal P from the N time delay signals after calibration according to the modulation precision requirementnModulating to modulation frequency F of PWM signal by rising edge or falling edge modulation modePWMAnd obtaining a high-precision modulated PWM signal, wherein N is an integer from 1 to N.

Description

High-precision pulse width modulation system and method
Technical Field
The present invention relates to pulse width modulation systems, and more particularly to high resolution pulse width modulation systems with multi-phase time delays.
Background
Pulse Width Modulation (PWM) is a very efficient technique for controlling analog circuits using the digital output of a microprocessor, and is widely used in many fields from measurement, communication to power control and conversion. How to generate a PWM signal with high precision and finely adjust the pulse width of the PWM signal is a significant challenge in the art.
In some existing pulse width modulation systems, a Delay Locked Loop (DLL-Delay Locked Loop) is used to control a PWM signal, as shown in fig. 1. The delay locked loop does not provide a multi-phase delayed output signal and thus cannot be used in system applications requiring fine delay resolution.
Furthermore, it is proposed in the prior art to implement the formation of 40 multiphase delay signal outputs using 5 × 8 delay cells in a delay locked loop. However, the generation of the multiphase signals at its input terminals employs an analog circuit interpolation technique, which is prone to cause phase errors in the multiphase input signals, and also does not provide a high-precision implementation of pulse width modulation.
Disclosure of Invention
In order to realize high-precision modulation of a pulse width signal, the invention provides a high-precision pulse width modulation system and a high-precision pulse width modulation method.
The high-precision pulse width modulation system comprises a multiphase time delay locking loop system and a PWM signal post processor.
The multiphase delay locked loop system is configured to generate M main phase signals Q based on an input reference frequency signal0～QM－1And generating N time delay signals P according to the M main phase signals1～PNWherein N ═ M × S, M, N, S is an integer greater than or equal to 1; selecting N time delay signals P1～PNCompares the phase with a particular one of the M master phase signals and converts the comparison result into a digital error signal to calibrate the output phase error of the delay signal.
The PWM signal post processor selects a time delay signal P from the N time delay signals after calibration according to the modulation precision requirementnBy modulation of rising or falling edgesModulated to the modulation frequency F of the PWM signalPWMAnd obtaining a high-precision modulated PWM signal, wherein N is an integer from 1 to N.
In one embodiment, the multi-phase delay locked loop system comprises a main phase signal generator configured to generate the M main phase signals Q based on the input reference frequency signal0～QM－1The M master phase signals have a frequency Fout, and the M master phase signals in turn have a phase difference of 360/M degrees.
In one embodiment, the multi-phase delay locked loop system further comprises a phase locked loop. The phase locked loop comprises a time delay module, a charge pump type phase discriminator, a loop filter and an analog-to-digital converter.
The delay module comprises M delay lines, each delay line correspondingly receives one main phase signal in the M main phase signals, and each delay line comprises S numerical control delay units which are sequentially connected in series; under the condition that the time delay module has no error, each time delay line delays the corresponding main phase signal and then outputs S time delay signals with the same phase difference in sequence, so that the time delay delta T between the time delay signals is 1/(Fout M S), and the phase shift difference is 360/(M S).
The charge pump type phase discriminator is configured to compare the time delay signal P output by the last time delay unit in the jth time delay linekAnd a main phase signal Q of the next delay linejIs the same, a comparison result in the form of an analog current is obtained, wherein PkFor said particular time-delayed signal, QjJ is an integer from 1 to M for the specific master phase signal, k is j S, QMViewed as Q0。
The loop filter converts the comparison result into an analog voltage value.
The analog-to-digital converter converts the analog voltage value into the digital error signal, and the digital error signal has PkAnd QjThe digital error signal is fed back to the time delay module; when the digital error signal is presentShow PkAnd QjIs the same, then PkThe corresponding delay line has no error; when the digital error signal represents PkAnd QjIn the presence of a phase error, then PkThe corresponding delay line needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, and adjusts the phase of the phase-adjusted PkOutput to the charge pump type phase discriminator and Q is connected againjComparing until the digital error signal represents PkAnd QjIf the phases of the delay lines are the same, the error correction of the delay line of the delay module is finished.
In an embodiment, the multiphase time delay locked loop system further includes a first gate, a second gate, and a digital state machine.
The first gate is configured to select P from the output of the delay module under control of the digital state machine0、PnAnd PkIn which P is0Representing non-delayed signals, P0Is input to the PWM signal post-processor, PnFor the calibrated modulation frequency F used for modulating the PWM signalPWMTime-delayed signal of, PnIs input to the PWM signal post-processor, PkFor time-delayed signals for correcting phase errors, PkIs input to the charge pump phase detector.
The second gate is configured to slave M digital master phase signals Q via control of the digital state machine0～QM－1To select out Qj，QjIs sent to the charge pump phase detector.
The digital state machine is configured to perform signal gating control and system control of the first and second gates according to a state control signal from a master control unit and the digital error signal.
In one embodiment, the digital state machine selects, according to the state control signal, to perform phase error calibration only on the delay signal output by the delay line corresponding to one of the M digital master phase signals, or to perform phase error calibration on the delay signals output by the delay lines corresponding to all the M digital master phase signals.
In one embodiment, the digital state machine further selects the rising edge or the falling edge modulation mode according to the state control signal.
In one embodiment, the digital state machine selects the total N time-delayed signals P1～PNWhen the digital error signal represents P in the case of calibration of the output phase error of (b), the digital error signal represents PkAnd QjWhen there is no phase error, the digital state machine controls the first gating device and the second gating device to gate the next group of PkAnd QjFor the phase locked loop to perform a phase comparison, wherein the next group PkAnd QjRefers to P obtained after j +1kAnd Qj。
In one embodiment, when the time delay signal PnModulation frequency F modulated to PWM signal by rising edge modulationPWMThe time delay of the rising edge is (N/N) × Δ T, Δ T is 1/(Fout × N), and N is an integer from 1 to N/2.
In one embodiment, when the time delay signal PnModulation frequency F modulated to PWM signal by falling edge modulationPWMThe falling edge time delay is- (N-N/N) × Δ T, Δ T ═ 1/(Fout × N), and N is an integer from N/2+1 to N.
In one embodiment, the PWM signal post-processor comprises a first D-type flip-flop, a second D-type flip-flop and an OR gate;
the D end of the first D-type flip-flop is input with the modulation frequency F of the PWM signalPWMThe input at the C terminal is P0；
The D end of the second D-type flip-flop is input with the modulation frequency F of the PWM signalPWMThe input at the C terminal is Pn；
The outputs of the first and second D-type flip-flops are used as the inputs of an OR gate, and the output of the OR gate is the PWM modulation signal after high-precision modulation.
In one embodiment, the master phase signal generator is a current-mode logic digital divider.
In one embodiment, the master phase signal generator is implemented by a multi-phase ring oscillator and a phase-locked loop coupled to the multi-phase ring oscillator.
The invention relates to a high-precision pulse width modulation method, which comprises the following steps:
providing a reference signal frequency and a modulation frequency Fpwm of the PWM signal;
generating M digital master phase signals having a frequency Fout based on the reference signal frequency, the M master phase signals having a phase difference of 360/M degrees in sequence;
providing a time delay module with M time delay lines to delay M digital main phase signals to obtain N time delay signals P1～PNWherein N ═ M × S, M, N, S is an integer greater than or equal to 1;
selecting N time delay signals P1～PNComparing the phase of the specific time delay signal with a specific main phase signal in the M main phase signals, and converting the comparison result into a digital error signal to calibrate the output phase error of the time delay signal; and
selecting a time delay signal P from the N calibrated time delay signals according to the modulation precision requirementnModulating to modulation frequency F of PWM signal by rising edge or falling edge modulation modePWMAnd obtaining a high-precision modulated PWM signal, wherein N is an integer from 1 to N.
In one embodiment, the time delay module with M delay lines is provided to delay M digital main phase signals to obtain N delay signals P1～PNComprises the following steps:
each delay line correspondingly receives one main phase signal of the M main phase signals, wherein each delay line comprises S numerical control delay units which are sequentially connected in series;
under the condition that the delay module has no error, each delay line delays the corresponding main phase signal and then outputs S delay signals with a phase difference in sequence, so that delay delta T between the delay signals is 1/(Fout M S), and the phase shift difference is 360/(M S).
In one embodiment, the selecting N time-delayed signals P1～PNCompares the phase of the particular time delayed signal with a particular main phase signal of the M main phase signals, and converts the comparison result into a digital error signal to calibrate an output phase error of the time delayed signal, comprising:
only the phase error calibration is carried out on the time delay signal output by the time delay line corresponding to one main phase signal in the M digital main phase signals; or
And performing phase error calibration on the delay signals output by the delay lines corresponding to all the M digital main phase signals.
In one embodiment, the selecting N time-delayed signals P1～PNCompares the phase of a particular one of the M main phase signals with a particular one of the M main phase signals, and converts the comparison result into a digital error signal to calibrate the output phase error of the delay signal, comprising:
selecting the time delay signal P output by the last time delay unit in the jth time delay linekAnd a main phase signal Q of the next delay linejComparing the phases with each other, wherein PkFor said particular time-delayed signal, QjJ is an integer from 1 to M for the specific master phase signal, k is j S, QMViewed as Q0；
Converting the comparison result into an analog voltage value;
converting the analog voltage value to the digital error signal with PkAnd QjThe digital error signal is fed back to the time delay module; when the digital error signal represents PkAnd QjIs the same, then PkThe corresponding delay line has no error, and the next group P is selectedkAnd QjFor phase comparison, wherein the next group PkAnd QjRefers to P obtained after j +1kAnd Qj(ii) a When the digital error signal represents PkAnd QjIn the presence of a phase error, then PkThe corresponding delay line needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, and adjusts the phase of the phase-adjusted PkAgain with QjComparing until the digital error signal represents PkAnd QjIf the phases of the delay lines are the same, the error correction of the delay line of the delay module is finished.
In one embodiment, when said time-delayed signal PnModulation frequency F modulated to PWM signal by rising edge modulationPWMThe time delay of the rising edge is (N/N) × Δ T, Δ T is 1/(Fout × N), and N is an integer from 1 to N/2.
In one embodiment, when said time-delayed signal PnModulation frequency F modulated to PWM signal by rising edge modulationPWMThe falling edge time delay is- (N-N/N) × Δ T, Δ T ═ 1/(Fout × N), and N is an integer from N/2+1 to N.
The high-precision pulse width modulation system and the method are extremely good in application in a multiphase time delay locked loop, and can realize high-precision modulation of pulse width signals.
Drawings
The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. It is to be noted that the appended drawings are intended as examples of the claimed invention. In the drawings, like reference characters designate the same or similar elements.
FIG. 1 illustrates a prior art delay locked loop;
FIG. 2 illustrates a high resolution pulse width modulation system based on multi-phase time delays according to an embodiment of the present invention;
FIG. 3 illustrates a logic circuit of a PWM post-processor according to an embodiment of the present invention;
FIG. 4 illustrates a diagram of input and output signal timing for a PWM post-processor according to an embodiment of the present invention;
FIG. 5 shows a system operation and control flow diagram according to an embodiment of the invention.
Detailed Description
The detailed features and advantages of the present invention are described in detail in the detailed description which follows, and will be sufficient for anyone skilled in the art to understand the technical content of the present invention and to implement the present invention, and the related objects and advantages of the present invention will be easily understood by those skilled in the art from the description, claims and drawings disclosed in the present specification.
The pulse width modulation system of the invention is a high-resolution pulse width modulation (HR PWM) system based on multi-phase time delay (MP DLL). As shown in fig. 2, the system includes a multiphase delay locked loop system and a PWM signal post processor 210.
The multiphase delay locked loop system includes a main phase signal generator 201, a first gate 202, a second gate 203, a phase locked loop 204, and a digital state machine 205. Phase locked loop 204 includes a delay module 206, a charge pump phase detector 207, a loop filter 208, and an analog-to-digital converter (ADC) 209.
Master phase signal generator 201 generates M digital master phase signals Q based on an input reference frequency signal Fref0～QM－1(having a frequency Fout) where M is an integer greater than or equal to 1. The M main phase signals have a phase difference of 360/M degrees in sequence. For example, when M is 8, 8 main phase signals Q0-Q7The phase difference between the sequences is 45 degrees, and is respectively 0, 45, 90, 135, 180, 225, 270 and 315 degrees.
In one embodiment, the main phase signal generator 201 may be implemented by a Current Mode Logic digital Divider (CML Divider). In one embodiment, the current-mode logic digital divider converts a single-ended input reference frequency signal Fref from a current-mode logic circuit into a fully differential signal, and generates 8 main phase signals Q by a divide-by-4 divider0-Q7Where Fout is Fref/4. For example, the frequency of the input reference frequency signal Fref may be 400M, and the frequency of the output signal Fout of the master phase signal generator is 100M at this time.
At one isIn one embodiment, the main phase signal generator 201 may be implemented by a multi-phase Ring Oscillator (RO) and a Phase Locked Loop (PLL). For example, the multi-phase ring oscillator may be an 8-phase ring oscillator, generating 8 main phase signals Q0-Q7. In one embodiment, the input reference frequency signal Fref may be a lower frequency, such as 24MHz or 40 MHz. A Phase Locked Loop (PLL) multiplies the input reference frequency signal Fref to a high frequency, e.g., in the 100MHz range, and 8 master phase signals with a phase difference of 45 degrees are generated by an 8-phase output ring oscillator (8-phase RO). The ring oscillator is generally composed of a CMOS inverter, and its oscillation frequency and phase are controlled by current or voltage, and then the final output frequency and phase are locked by a phase-locked loop.
Delay module 206 includes M Delay lines Delay M-1, …,0, each of which includes S identical digitally controlled Delay elements, i.e., each Delay line can provide S phase shifted or delayed signal outputs. Each delay line correspondingly receives a main phase signal, and under the condition that no error exists in the delay line (or under the condition that the error is calibrated), the delay line outputs S phase shift or delay signals with the same phase difference in sequence, wherein the phase difference is 360/(M S), so that the phase shift or delay signal output by the last delay unit in each delay line is the same as the phase of the main phase signal input to the next delay line.
The M delay lines provide M S phase-shifted or delayed output signals, i.e. P1，P2，...，PM*SAdded to the original phase signal P which has not undergone phase shift0The delay module 202 outputs a total of (M S) +1 phase shifted or delayed signals, where P is0And PM*S(corresponding to a phase shift of 360 degrees) and Q0Are identical. The phase difference between the phase shifted signals is 360/(M × S), and the time delay Δ T, when converted to a time delay, is 1/(Fout × M × S). P thnA time delay signal (n epsilon [1, M S ]]) The delay time of (d) is n/(Fout M S).
It is noted that the term "phase shift" is understood by those skilled in the art to have substantially the same meaning as the term "time delay", and thus, reference herein to "phase shifted signal" and "time delayed signal" refers to the same signal, and reference herein to "phase error" and "time delayed error" has substantially the same meaning.
In one embodiment, it is assumed that M is 8 and S is 8, i.e. the master phase signal generator generates 8 master phase signals Q0～Q7Their phase difference in sequence is 45 degrees, respectively Q0Phase shift of 0 degree, Q1Phase shift of 45 degrees, Q2Phase shift 90 degree, Q3Phase shift of 135 degree, Q4Phase shift of 180 degrees, Q5Phase shift 225 degrees, Q6Phase shift 270 degree, Q7The phase shift is 315 degrees. Q0After being input into the first delay line, the delay line outputs 8 phase shift or delay signal outputs P1～P8The phase difference between the 8 phase shifted or delayed signals is 45/8 degrees, the 8 th phase shifted or delayed signal P8Is 45 degrees, exactly with the next main phase signal Q1The phase difference (45 degrees) of (d) is the same. By analogy, Q7(with a phase difference of 315 degrees) to an eighth delay line that outputs 8 phase shifted or delayed signal outputs P57～P64The phase difference between the 8 phase shifted or delayed signals is 45/8 degrees, when the 8 th phase shifted or delayed signal P of the delay line64Is exactly 360 degrees out of phase with Q0The phase difference (0 degrees) of (d) is the same.
Ideally, i.e. if no error occurs in the delay module itself, the phase shift or delay signal output P from the last delay cell in each delay line iskShould be matched with the main phase signal Q input to the next delay linejJ represents the j-th delay line, j is an integer from 1 to M, k is j × S, QMViewed as Q0. That is, when M is 8 and S is 8, P is 18Should be in phase with Q1The same is true. When j is 2, P16Should be in phase with Q2Same … … analogize in turn, when j is 8, P64Should be in phase with Q0The same is true. In practical application, however, the delay module or delay line has error, so that 65-path phase shift orThe phase difference between the time-delayed signals is not uniform, i.e. P8Phase of (2) and Q1Will have an error, P16Phase of (2) and Q2There will be an error … … in the phase of P64Phase of (2) and Q0There will be an error in the phase of (a). If the 65-way phase shift or delay output signal with phase error is used to adjust the pulse width of the PWM signal, the accuracy of the adjustment is greatly reduced. Therefore, to solve this problem, the present invention compares the phase shifted or delayed signal output P from the last delay element in each delay linekAnd a main phase signal Q of the next delay linejWhether the phases are the same or not, to control and adjust the output delay error or the output phase error generated by the delay module.
The first gate 202 receives the outputs from the delay module and selects, from these output signals, via the control of the digital state machine 205, three signals:
--P0and outputs to a Post Processor (Post Processor)210 for phase synchronization processing function in the Post Processor;
--Pnthe delay time of the selected time delay signal, which is output to the post-processor 210, can be calculated by (n/(M × S)) × (1/Fout); wherein n is 1, 2.., M is S;
--Pkis selected as one input reference signal of a charge pump type phase discriminator (PD/CP)207 in the phase-locked loop, wherein k is j is S, j is E [1, M ∈]。
The second gate 203 receives M main phase signals and selects one signal Q from the main phase signals through the control of the digital state machine 205jAnd output to the charge pump phase detector 207.
Charge pump phase detector 207 compares PkAnd QjIs the same, wherein PkAnd QjIs not optional, and k ═ j × S, Q need to be satisfiedMViewed as Q0. That is, if M is 8 and S is 8, P needs to be selected8And Q1Comparison, P16And Q2Comparison, P24And Q3Comparison, P32And Q4Comparison, P40And Q5Comparison, P48And Q6Comparison, P56And Q7Comparison, P64And Q0And (6) comparing.
The charge pump type phase detector 207 outputs the comparison result to the Loop Filter (LF)208 in the form of an analog current to obtain an analog voltage value, and then outputs a digital quantity (i.e., a digital error signal) as a control signal after being converted by the analog-to-digital converter (ADC)209, one path of the digital quantity is fed back to the delay module 206 to adjust the phase shift or delay error of the delay module, and the other path of the digital quantity is output to the digital state machine 205 to control the state switching of the state machine, i.e., the gating of the first gate and the second gate. The control signal has PkAnd QjThe phase error information of (1).
Ideally, PkAnd QjAre the same, so if the phase of the charge pump phase detector 207 is compared to find that the phases of the two are the same, then P is representedkAnd QjWithout phase error between, PkThe corresponding delay line does not need to be adjusted by an error, and the digital state machine 205 selects whether the phase of the next set of comparison objects is the same, where the next set of comparison objects refers to P obtained after j is j +1kAnd Qj。
If the charge pump phase detector 207 finds P by comparisonkAnd QjIs in error, the comparison result is fed back to the delay module 206 after being analog-to-digital converted into a digital quantity (digital error signal) by the analog-to-digital converter. The digital quantity represents the magnitude of the error. The delay module 206 adjusts the error according to the digital quantity, and the adjusted output PkThen passes through a charge pump type phase discriminator and QjCompares and feeds back the digital value to the delay module 206, and so on until the comparison result indicates PkAnd QjThe phase is the same, indicating that P is nowkWhen the corresponding delay line is calibrated, the digital state machine 205 controls the charge pump phase detector 207 to jump to the next set of comparison objects, i.e. let j ═ j +1 (i.e. start the calibration of the next delay line), and continue to compare PkAnd QjWhether the phase isAnd repeating the steps until the whole time delay module is calibrated.
In one embodiment, the analog-to-digital converter (ADC)209 of the present invention requires a low resolution, typically 4 bits.
In one embodiment, a Digital State Machine (DSM)205 is used for system control, calibration control, and post-processor latency selection. Digital State Machine (DSM)205 receives two signal inputs, one is the digital error signal with phase error information output by analog-to-digital converter (ADC)209 in phase locked loop 204; the other is a state control signal from a master control unit (SOC), such as a microprocessor in a chip (MCU), e.g., a power-on, calibration end, calibration start, etc. The digital state machine 205 outputs a digital control signal for signal selection control of the first and second gates and control of the entire system based on the two input signals.
In one embodiment, the digital state machine 205 may select to perform phase error calibration only on the delay signal output by the delay line corresponding to one of the M digital main phase signals according to the state control signal, or may select to perform phase error calibration on the delay signals output by the delay lines corresponding to all the M digital main phase signals. The control may be performed by controlling signal selection of the first and second gates.
In one embodiment, the digital state machine 205 further selects the rising edge or the falling edge modulation scheme according to the state control signal.
In one embodiment, the digital state machine 205 selects the total N number of time delayed signals P1～PNWhen the digital error signal represents P in the case of calibration of the output phase error of (1)kAnd QjWhen there is no phase error, the digital state machine 205 controls the first and second gates to gate the next group of PkAnd QjFor phase-locked loop phase comparison, wherein the next group PkAnd QjRefers to P obtained after j +1kAnd Qj。
The input signal to the PWM post-processor 210 is P0And PnAnd FPWMIn which F isPWMThe output signal is a PWM modulation signal after high-precision modulation, which is the modulation frequency of the PWM signal. PWM post-processor 210 can be either FPWMModulation of the rising edge of the frequency signal, also for FPWMThe falling edge of the frequency signal is modulated. The PWM post-processor 210 selects a time delay signal P from the calibrated N time delay signals according to the modulation precision requirementnModulating to modulation frequency F of PWM signal by rising edge or falling edge modulation modePWMObtaining a high-precision modulated PWM signal, where N is an integer from 1 to N, and different PnRepresenting different modulation accuracies.
The PWM post-processor 210 in the present invention can be implemented by a simple logic circuit. FIG. 3 illustrates a logic circuit implementation of a PWM post-processor according to an embodiment of the present invention. As shown in fig. 3, the PWM signal post-processor includes a first D-type flip-flop, a second D-type flip-flop, and an or gate. The D end of the first D-type flip-flop is input with the modulation frequency F of the PWM signalPWMThe input at the C terminal is P0. The D end of the second D-type flip-flop is input with the modulation frequency F of the PWM signalPWMThe input at the C terminal is Pn. The outputs of the first and second D-type flip-flops are used as the inputs of an OR gate, and the output of the OR gate is the PWM modulation signal after high-precision modulation, and is represented by PWMn in the figure.
In one embodiment, the time delay signal PnModulation frequency F modulated to PWM signal by rising edge modulationPWMThe rising edge delay is (N/N) × Δ T, Δ T is 1/(Fout × N), and N is an integer from 1 to N/2.
In one embodiment, the time delay signal PnModulation frequency F modulated to PWM signal by falling edge modulationPWMThe falling edge time delay is- (N-N/N) × Δ T, Δ T is 1/(Fout × N), and N is an integer from N/2+1 to N.
The timing relationship of the input and output signals of the post-processor 210 is given by fig. 4. For simplicity and clarity, the timing relationship in fig. 4 is given only for the delay modules with 8-phase outputs, i.e., the delay modules output P in total1～P8。
The system of the present invention may modulate the falling edge of the pulse with a time delay such as n-1/2/3, or modulate the rising edge of the pulse with a time delay such as n-4/5/6/7.
It should be noted that the PWM post-processor 210 of the present invention is not limited to be implemented by the logic circuit shown in fig. 3. Those skilled in the art will appreciate that the PWM post-processor 210 may also be implemented using other modules or circuits.
In addition, the values of M and S in the present invention are not limited to the values mentioned in the above embodiments, and may be selected according to actual requirements (e.g. precision requirements). In addition, the high-precision pulse width modulation system can also select the output phase of the delay signal corresponding to one main phase signal from the M main phase signals for calibration, and at the moment, the multi-phase delay locked loop system is changed into a single phase locked loop.
The invention also discloses a high-precision pulse width modulation method, which comprises the following steps:
providing a reference signal frequency and a modulation frequency Fpwm of the PWM signal;
generating M digital master phase signals having a frequency Fout based on the reference signal frequency, the M master phase signals having a phase difference of 360/M degrees in sequence;
providing a time delay module with M time delay lines, and carrying out time delay on M digital main phase signals to obtain N time delay signals P1～PNWherein N ═ M × S, M, N, S is an integer greater than or equal to 1;
selecting N time delay signals P1～PNComparing the phase of the specific time delay signal with a specific main phase signal in the M main phase signals, and converting the comparison result into a digital error signal to calibrate the output phase error of the time delay signal; and
selecting a time delay signal P from the N calibrated time delay signals according to the modulation precision requirementnModulating to modulation frequency F of PWM signal by rising edge or falling edge modulation modePWMTo obtain a high-precision modulated PWM modulation signalWherein N is an integer from 1 to N.
In one embodiment, the time delay module with M delay lines is provided to delay M digital main phase signals to obtain N delay signals P1～PNComprises the following steps:
each delay line correspondingly receives one main phase signal of the M main phase signals, wherein each delay line comprises S numerical control delay units which are sequentially connected in series;
under the condition that the delay module has no error, each delay line delays the corresponding main phase signal and then outputs S delay signals with a phase difference in sequence, so that delay delta T between the delay signals is 1/(Fout M S), and the phase shift difference is 360/(M S).
In one embodiment, the selecting N time-delayed signals P1～PNCompares the phase of the particular time delayed signal with a particular main phase signal of the M main phase signals, and converts the comparison result into a digital error signal to calibrate an output phase error of the time delayed signal, comprising:
only the phase error calibration is carried out on the time delay signal output by the time delay line corresponding to one main phase signal in the M digital main phase signals; or
And performing phase error calibration on the delay signals output by the delay lines corresponding to all the M digital main phase signals.
In one embodiment, the selecting N time-delayed signals P1～PNCompares the phase of the particular time delayed signal with a particular main phase signal of the M main phase signals, and converts the comparison result into a digital error signal to calibrate an output phase error of the time delayed signal, comprising:
selecting the time delay signal P output by the last time delay unit in the jth time delay linekAnd a main phase signal Q of the next delay linejComparing the phases with each other, wherein PkFor said particular time-delayed signal, QjJ is an integer from 1 to M for the specific master phase signal, k is j S, QMViewed as Q0；
Converting the comparison result into an analog voltage value;
converting the analog voltage value to the digital error signal with PkAnd QjThe digital error signal is fed back to the time delay module; when the digital error signal represents PkAnd QjIs the same, then PkThe corresponding delay line has no error, and the next group P is selectedkAnd QjFor phase comparison, wherein the next group PkAnd QjRefers to P obtained after j +1kAnd Qj(ii) a When the digital error signal represents PkAnd QjIn the presence of a phase error, then PkThe corresponding delay line needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, and adjusts the phase of the phase-adjusted PkAgain with QjComparing until the digital error signal represents PkAnd QjIf the phases of the delay lines are the same, the error correction of the delay line of the delay module is finished.
In one embodiment, when said time-delayed signal PnModulation frequency F modulated to PWM signal by rising edge modulationPWMThe time delay of the rising edge is (N/N) × Δ T, Δ T is 1/(Fout × N), and N is an integer from 1 to N/2.
In one embodiment, when said time-delayed signal PnModulation frequency F modulated to PWM signal by rising edge modulationPWMThe falling edge time delay is- (N-N/N) × Δ T, Δ T ═ 1/(Fout × N), and N is an integer from N/2+1 to N.
FIG. 5 shows a system operation and control flow diagram according to an embodiment of the invention. Reference signal frequency Fref and PWM modulation signal frequency F after Power-On (Power On) and Reset (Reset)PWMAfter preparation (step 501), the master phase generator generates M master phase signals Q0～QM-1(step 502). According to the requirement of system precision, the invention can use a digital state machine to process multiple phasesExtended lines, e.g. Delay [ M-1:0]A Calibration flow Control (Calibration Control) is performed for a Single-Phase (Single-Phase) or a plurality of master phases (Multi-Phase) and gate Control is performed for the first gate and the second gate (step 503). The phase-locked loop is used for comparing the output phase of the delay line with the main phase, and the error signal is converted into a digital signal for controlling and adjusting the delay of the delay line, so that the phase is locked to eliminate the phase error, and a high-precision multi-phase delay line system is realized. After the calibration process is completed (Cal End)
(step 504), the digital state machine and the gate (e.g., Mux 65-to-3 and Mux 8-to-1) select a phase shifted signal or a delay signal P of a fixed delay linekAnd corresponding master phase signal QjWhere k is j × S, j is an integer from 1 to M, and the two phase signals are locked by the phase-locked loop (steps 505 and 506). At this time, the multiphase delay line will output a phase shifted or delayed signal after calibration and phase locking. The PWM signal post processor is switched on, the digital state machine controls the post processor according to the system requirement, selects and generates a rising Edge Delay (Rise Edge Delay) or a Falling Edge Delay (Falling Edge Delay), and modulates to the modulation frequency F of the PWMPWMThe above. Finally, the high-precision time-delayed PWM modulation signal is Output (PWM Output) by an Output Driver circuit (Driver). The calculation of the rising edge time delay can be calculated by the following formula: (N/N) × Δ T ═ 1/Fout, such as N ═ 64, N ═ 0,1, …,31, and the time delay of the trailing edge can also be estimated from the formula: - (N-N) × Δ T ═ 1/Fout, such as N ═ 64, N ═ 32,33, …,63, Δ T ═ 1/Fout)/64 (step 507).
For convenience of illustration, the above-mentioned work flow diagram adopts a delay line and PWM system having 8 main phases and 64 delay units, but the present invention is applicable to various corresponding systems with multiple main phases and multiple delay units.
The terms and expressions which have been employed herein are used as terms of description and not of limitation. The use of such terms and expressions is not intended to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications may be made within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be looked to in order to cover all such equivalents.
Also, it should be noted that although the present invention has been described with reference to the current specific embodiments, it should be understood by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes or substitutions may be made without departing from the spirit of the present invention, and therefore, it is intended that all changes and modifications to the above embodiments be included within the scope of the claims of the present application.

Claims (16)

1. A high precision pulse width modulation system, comprising:
a multi-phase delay locked loop system configured to generate M main phase signals Q based on an input reference frequency signal0～QM－1And generating N time delay signals P according to the M main phase signals1～PNWherein N ═ M × S, M, N, S is an integer greater than or equal to 1; selecting N time delay signals P1～PNComparing the phase of the specific time delay signal with a specific main phase signal in the M main phase signals, and converting the comparison result into a digital error signal to calibrate the output phase error of the time delay signal; and
the PWM signal post processor selects a time delay signal P from the N time delay signals after calibration according to the modulation precision requirementnModulating to modulation frequency F of PWM signal by rising edge or falling edge modulation modePWMAnd obtaining a high-precision modulated PWM signal, wherein N is an integer from 1 to N.
2. The high accuracy pulse width modulation system of claim 1 wherein the multiphase time delay locked loop system comprises:
a master phase signal generator configured to generate the M master phase signals Q based on the input reference frequency signal0～QM－1The M main phase signals have a frequency Fout, and the M main phase signals have phase differences in sequence360/M degree.
3. The high accuracy pulse width modulation system of claim 2 wherein the multi-phase delay locked loop system further comprises:
a phase locked loop comprising:
the delay module comprises M delay lines, each delay line correspondingly receives one main phase signal in the M main phase signals, and each delay line comprises S numerical control delay units which are sequentially connected in series; under the condition that no error exists in the time delay module, each time delay line delays the corresponding main phase signal and then outputs S time delay signals with the same phase difference in sequence, so that the time delay delta T between the time delay signals is 1/(Fout M S), and the phase shift difference is 360/(M S);
a charge pump type phase discriminator configured to compare the delay signal P output by the last delay unit in the jth delay linekAnd a main phase signal Q of the next delay linejIs the same, a comparison result in the form of an analog current is obtained, wherein PkFor said particular time-delayed signal, QjJ is an integer from 1 to M for the specific master phase signal, k is j S, QMViewed as Q0；
A loop filter converting the comparison result into an analog voltage value;
an analog-to-digital converter for converting the analog voltage value into the digital error signal with PkAnd QjThe digital error signal is fed back to the time delay module; when the digital error signal represents PkAnd QjIs the same, then PkThe corresponding delay line has no error; when the digital error signal represents PkAnd QjIn the presence of a phase error, then PkThe corresponding delay line needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, and adjusts the phase of the phase-adjusted PkOutput to the charge pump type phase discriminator andQjcomparing until the digital error signal represents PkAnd QjIs the same, then PkAnd finishing the error correction of the corresponding delay line.
4. The high accuracy pulse width modulation system of claim 3 wherein the multi-phase delay locked loop system further comprises:
a first gate, a second gate and a digital state machine;
the first gate is configured to select P from the output of the delay module under the control of the digital state machine0、PnAnd PkIn which P is0Representing non-delayed signals, P0Is input to the PWM signal post-processor, PnFor the calibrated modulation frequency F used for modulating the PWM signalPWMTime-delayed signal of, PnIs input to the PWM signal post-processor, PkFor time-delayed signals for correcting phase errors, PkIs input to the charge pump phase discriminator;
the second gate is configured to slave M digital master phase signals Q via control of the digital state machine0～QM－1To select out Qj，QjIs sent to the charge pump phase discriminator;
the digital state machine is configured to perform signal gating control and system control of the first and second gates according to a state control signal from a master control unit and the digital error signal, wherein:
and the digital state machine selects to carry out phase error calibration only on the time delay signal output by the time delay line corresponding to one main phase signal in the M digital main phase signals or to carry out phase error calibration on the time delay signal output by the time delay line corresponding to all the M digital main phase signals according to the state control signal, and selects the modulation mode of the rising edge or the falling edge according to the state control signal.
5. The high accuracy pulse width modulation system of claim 4 wherein the digital state machine selects P for all N delayed signals1～PNWhen the digital error signal represents P in the case of calibration of the output phase error of (b), the digital error signal represents PkAnd QjWhen there is no phase error, the digital state machine controls the first gating device and the second gating device to gate the next group of PkAnd QjFor the phase locked loop to perform a phase comparison, wherein the next group PkAnd QjRefers to P obtained after j +1kAnd Qj。
6. The high accuracy pulse width modulation system of claim 1 wherein when said time delay signal P is asserted, said time delay signal P is assertednModulation frequency F modulated to PWM signal by rising edge modulationPWMThe time delay of the rising edge is (N/N) × Δ T, Δ T is 1/(Fout × N), and N is an integer from 1 to N/2.
7. The high accuracy pulse width modulation system of claim 1 wherein when said time delay signal P is asserted, said time delay signal P is assertednModulation frequency F modulated to PWM signal by falling edge modulationPWMThe falling edge time delay is- (N-N/N) × Δ T, Δ T ═ 1/(Fout × N), and N is an integer from N/2+1 to N.
8. The high accuracy pulse width modulation system of claim 1 wherein said PWM signal post processor comprises a first D-type flip-flop, a second D-type flip-flop, and an or gate;
the D end of the first D-type flip-flop is input with the modulation frequency F of the PWM signalPWMThe input at the C terminal is P0；
The D end of the second D-type flip-flop is input with the modulation frequency F of the PWM signalPWMThe input at the C terminal is Pn；
The outputs of the first and second D-type flip-flops are used as the inputs of an OR gate, and the output of the OR gate is the PWM modulation signal after high-precision modulation.
9. The high accuracy pulse width modulation system of claim 2 wherein the master phase signal generator is a current-mode logic digital divider.
10. The high accuracy pulse width modulation system of claim 2, wherein the master phase signal generator is implemented by a multi-phase ring oscillator and a phase locked loop coupled to the multi-phase ring oscillator.
11. A high precision pulse width modulation method, the method comprising:
providing a reference signal frequency and a modulation frequency Fpwm of the PWM signal;
generating M digital master phase signals having a frequency Fout based on the reference signal frequency, the M master phase signals having a phase difference of 360/M degrees in sequence;
providing a time delay module with M time delay lines, and carrying out time delay on M digital main phase signals to obtain N time delay signals P1～PNWherein N ═ M × S, M, N, S is an integer greater than or equal to 1;
selecting N time delay signals P1～PNComparing the phase of the specific time delay signal with a specific main phase signal in the M main phase signals, and converting the comparison result into a digital error signal to calibrate the output phase error of the time delay signal; and
selecting a time delay signal P from the N calibrated time delay signals according to the modulation precision requirementnModulating to modulation frequency F of PWM signal by rising edge or falling edge modulation modePWMAnd obtaining a high-precision modulated PWM signal, wherein N is an integer from 1 to N.
12. The method of claim 11, wherein delaying the M digital main phase signals by a delay module having M delay lines provides N delay signals P1～PNThe method comprises the following steps:
each delay line correspondingly receives one main phase signal of the M main phase signals, wherein each delay line comprises S numerical control delay units which are sequentially connected in series;
under the condition that the time delay module has no error, each time delay line delays the corresponding main phase signal and then outputs S time delay signals with the same phase difference in sequence, so that the time delay delta T between the time delay signals is 1/(Fout M S), and the phase shift difference is 360/(M S).
13. The method of claim 12, wherein the selecting N time delayed signals P1～PNComparing the phase of the particular delayed signal with a particular one of the M main phase signals, and converting the comparison result into a digital error signal to calibrate an output phase error of the delayed signal comprises:
only the phase error calibration is carried out on the time delay signal output by the time delay line corresponding to one main phase signal in the M digital main phase signals; or
And performing phase error calibration on the delay signals output by the delay lines corresponding to all the M digital main phase signals.
14. The method of claim 12, wherein the selecting N time delayed signals P1～PNComparing the phase of the particular delayed signal with a particular one of the M main phase signals, and converting the comparison result into a digital error signal to calibrate an output phase error of the delayed signal comprises:
selecting the time delay signal P output by the last time delay unit in the jth time delay linekAnd a main phase signal Q of the next delay linejComparing the phases with each other, wherein PkFor said particular time-delayed signal, QjJ is an integer from 1 to M for the specific master phase signal, k is j S, QMViewed as Q0；
Converting the comparison result into an analog voltage value;
converting the analog voltage value to the digital error signal with PkAnd QjThe digital error signal is fed back to the time delay module; when the digital error signal represents PkAnd QjIs the same, then PkThe corresponding delay line has no error, and the next group P is selectedkAnd QjFor phase comparison, wherein the next group PkAnd QjRefers to P obtained after j +1kAnd Qj(ii) a When the digital error signal represents PkAnd QjIn the presence of a phase error, then PkThe corresponding delay line needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, and adjusts the phase of the phase-adjusted PkAgain with QjComparing until the digital error signal represents PkAnd QjIf the phases of the delay lines are the same, the error correction of the delay line of the delay module is finished.
15. The method of claim 11, wherein the time delay signal P is a time delay signalnModulation frequency F modulated to PWM signal by rising edge modulationPWMThe time delay of the rising edge is (N/N) × Δ T, Δ T is 1/(Fout × N), and N is an integer from 1 to N/2.
16. The method of claim 11, wherein the time delay signal P is a time delay signalnModulation frequency F modulated to PWM signal by rising edge modulationPWMThe falling edge time delay is- (N-N/N) × Δ T, Δ T ═ 1/(Fout × N), and N is an integer from N/2+1 to N.
CN202011166022.7A 2020-10-27 2020-10-27 High-precision pulse width modulation system and method Pending CN112187229A (en)

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CN114724501A (en) * 2022-03-23 2022-07-08 厦门凌阳华芯科技有限公司 LED display and pulse width modulation system thereof
CN115243357A (en) * 2022-07-15 2022-10-25 中国人民解放军国防科技大学 RF-PWM signal delay error correction method and system
CN116015253A (en) * 2022-12-13 2023-04-25 上海极海盈芯科技有限公司 Self-correcting delay circuit, micro-processing chip and motor control system

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CN114724501A (en) * 2022-03-23 2022-07-08 厦门凌阳华芯科技有限公司 LED display and pulse width modulation system thereof
CN114724501B (en) * 2022-03-23 2024-06-04 厦门凌阳华芯科技股份有限公司 LED display and pulse width modulation system thereof
CN115243357A (en) * 2022-07-15 2022-10-25 中国人民解放军国防科技大学 RF-PWM signal delay error correction method and system
CN115243357B (en) * 2022-07-15 2023-08-18 中国人民解放军国防科技大学 RF-PWM signal delay error correction method and system
CN116015253A (en) * 2022-12-13 2023-04-25 上海极海盈芯科技有限公司 Self-correcting delay circuit, micro-processing chip and motor control system
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