CN112104489B - High-speed real-time data capturing method without interference to communication - Google Patents
High-speed real-time data capturing method without interference to communication Download PDFInfo
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- CN112104489B CN112104489B CN202010912593.4A CN202010912593A CN112104489B CN 112104489 B CN112104489 B CN 112104489B CN 202010912593 A CN202010912593 A CN 202010912593A CN 112104489 B CN112104489 B CN 112104489B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/14—Network analysis or design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
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Abstract
The invention belongs to the field of computer network communication, and particularly relates to a high-speed real-time data capturing method without interference to communication. The invention realizes the loopback and redundancy of high-speed serial data by utilizing a CML or LVDS level one-to-two chip, utilizes the real-time data analysis of redundant data, supports the functions of fault injection and bit error rate test, and supports the data rate of 500 Mbps-6.25 Gbps, thereby ensuring the normal interference-free transmission of data and realizing the capture of data.
Description
Technical Field
The invention belongs to the field of computer network communication, and particularly relates to a high-speed real-time data capturing method without interference to communication.
Background
At present, an aircraft control system carries out data communication through various buses, the real-time reliable operation of the buses is of great importance to the safety of the aircraft, the data transmission rate and the high-reliability design of the buses are continuously improved along with the development of bus technology, and higher requirements are also put forward for bus testing. In the process of testing the bus, various types of data frames running in the network need to be captured and analyzed, and information such as sending time, arrival time, accuracy of transmission data and the like of the data frames is determined, so that performance tests such as packet capture analysis, communication test, pressure test, fault injection, accurate positioning of faults, error rate test and the like are performed. The Bit Error Rate (BER) is the ratio of the number of bits that have been erroneous within a certain observation time to the total number of bits transmitted within that time period. The bit error rate is defined as:
BER＝N e /N t 。
wherein N is e 、N t The number of erroneous bits in the time interval t, the total number of bits transmitted, respectively. By using the bit error rate test data, the reliability of the transmission of the communication system can be efficiently evaluated, the faults of the tested object can be effectively checked, and the method has good practical application significance. The fault injection function can provide good help for testing fault tolerance and recurrent faults of the bus network equipment.
The existing data capturing method comprises a kernel-mode Packet filter and two dynamic link libraries, wherein an NPF (network Packet Filter) network Packet filter is responsible for collecting data packets from a network, completing the filtration of the data packets, copying the data packets to a kernel layer buffer area, calling an application layer dynamic link library file to transmit the data to the application layer buffer area, and finally handing the data to a program for processing. In addition, the research of the data capture analysis instrument with the fault injection function mainly takes JDSU company and Finisar as main instruments, but the price is high, the cost is high, and no relevant research exists at present in China.
Disclosure of Invention
The purpose of the invention is as follows: the method is used for solving the problems of low real-time performance and low reliability of the existing capturing method, supports the functions of error rate testing and fault injection and has important significance for high-speed bus testing.
The technical scheme of the invention is as follows: a high-speed real-time data capturing method without interference to communication is provided, the method comprises the following steps:
actual data on a bus network is captured, two paths of data are generated through a level one-to-two chip and are respectively a first path of data and a second path of data, the first path of data is transmitted back to the bus network, and the second path of data enters a data packet analysis module;
the data packet analysis module comprises an FPGA module and a processor module; the data packet analysis module analyzes the second path of data, the acquired second path of data is written into a shared Buffer area of the FPGA, the FPGA performs configuration operation on the FPGA, the FPGA sends the written second path of data to the DDR3 for storage, the processor module reads the data through a PCIe switching chip, the data frame type is identified through identifying a data frame header, different data frame formats of the second path of data are analyzed according to different protocol stacks, and the analyzed data blocks are stored;
the upper computer software reads the analyzed data block in the processor module; the upper computer inputs theoretical data through a network port and generates a test sequence; the control communication module of the upper computer starts to receive the test sequence and sends the test sequence to the processor module; controlling the communication module to detect the FIFO state of the upper computer receiver in the receiving process, when the FIFO is half full, the upper computer starts to read the test sequence received by the processor module, compares the test sequence with the analyzed data block, counts the error code number and calculates the error code rate; when the FIFO is full, the communication module is controlled to finish receiving the test sequence, and the upper computer displays the counted error code number and the calculated error code rate;
when the control communication module of the upper computer starts to receive the test sequence, the control communication module of the upper computer judges whether the sending code of the theoretical data is enough; and when the sending code of the theoretical data is enough, the control communication module of the upper computer stops sending the test sequence to the processor module and stops receiving the test sequence.
Further, the method comprises: the data packet analysis module further comprises a PCIe exchange chip, and the PCIe exchange chip is in data connection with the FPGA channel and the processor module respectively so as to improve the data transmission rate between the FPGA channel and the processor module.
Further, the method comprises: the data packet analysis module analyzes the second path of data; the processor module acquires the first 4 bytes of the MAC address field of the data frame in the second path of data, and judges the format of the data frame according to the first 4 bytes; the processor module allocates the data address of the second path of data to the corresponding protocol stack according to the data frame format; the processor module recovers the data processed by each protocol stack and returns the address space to the second path of data; and the thread of each protocol stack is respectively distributed with two data queues which are respectively used for storing the data block to be analyzed and the analyzed data block in the second path of data.
Further, the method further comprises: a fault injection process; the upper computer identifies the lead code of the second path of data and identifies the position of the fault code injected into the bus network according to the requirement; programming fault codes through a JTAG port of the FPGA channel; and injecting the fault code into the bus network by the FPGA channel.
Furthermore, the level-to-two chip is a CML or LVDS level-to-two chip. The LVDS is a low-power and low-cost signal transmission technology, and is widely applied to parallel and relatively low-speed serial communication systems, and the application of the LVDS is limited in the case that the rate exceeds 1 Gbit/s. CML is the simplest of all high speed data interfaces, with matched input and output circuitry, and supports higher data transfer rates.
Further, the actual data on the bus network is input into the level one-to-two chip through a pluggable module; the first path of data is output to the bus network through the pluggable module.
Furthermore, the pluggable module is a small-sized hot-pluggable transceiver module.
Furthermore, the FPGA channel, the PCIe exchange chip and the processor module are connected through a PCIeX4 bus interface.
The invention has the technical effects that:
the invention realizes the loopback and redundancy of high-speed serial data by utilizing a CML or LVDS level one-to-two chip, utilizes the real-time data analysis of redundant data, supports the functions of fault injection and bit error rate test, and supports the data rate of 500 Mbps-6.25 Gbps, thereby ensuring the normal interference-free transmission of data and realizing the capture of data. And test guarantee is provided for the design and development of the bus. The bottleneck problem of the host computer on the capture and real-time processing capacity of the bus data packet in the high-speed network environment is solved.
Drawings
FIG. 1 is a functional block diagram of data capture;
FIG. 2 is a data capture flow diagram;
FIG. 3 is a schematic block diagram of packet parsing;
FIG. 4 error rate test principle;
FIG. 5 is a schematic diagram of a bit error rate test flow;
fig. 6 is a schematic diagram of a fault injection process.
Detailed Description
Example 1
In this embodiment, fig. 1 is a functional block diagram of data capture, and in combination with fig. 1, a method for capturing real-time data at high speed without interference to communication is provided, where the method includes:
capturing actual data on the bus network, generating first data and second data through a level-one-to-two chip, transmitting the first data back to the bus network, and enabling the second data to enter a data packet analysis module;
the data packet analysis module comprises an FPGA channel and a processor module which are sequentially connected in a data mode; the data packet analysis module analyzes the second data and writes the acquired second data into a shared Buffer of the FPGA channel; the processor module analyzes different data frame formats of the second data according to different protocol stacks and stores the analyzed data blocks;
the upper computer reads the analyzed data block in the processor module; the upper computer inputs theoretical data through a network port and generates a test sequence; the control communication module of the upper computer starts to receive the test sequence and sends the test sequence to the processor module; detecting the FIFO state of the upper computer receiver in the receiving process of the control communication module, and when the FIFO is half full, the upper computer starts to read the test sequence received by the processor module and compares the test sequence with the analyzed data block, and counts the number of error codes and calculates the error code rate; when the FIFO is full, the upper computer displays the counted error code number and the calculated error code rate after receiving the test sequence;
when the control communication module of the upper computer starts to receive the test sequence, the control communication module of the upper computer judges whether the sending code of the theoretical data is enough; and when the sending code of the theoretical data is enough, the control communication module of the upper computer stops sending the test sequence to the processor module and stops receiving the test sequence.
Specifically, in this embodiment, the data capturing flowchart in fig. 2 is combined with the data capturing flowchart in fig. 2, and the method for capturing high-speed real-time data without interference to communication includes the following steps:
step 1: the receiving port RX0 of the pluggable module 1 is connected with a bus network;
step 2: the pluggable module 1 transmits data to a CML level or LVDS level one-to-two chip through a high-speed interface;
and step 3: one-to-two chip generates two paths of data, one path of data is transmitted back to a TX1 transmitting port of the pluggable module 2 by the level one-to-two chip and returns to a bus network, and the other path of data enters the data packet analysis module.
And 4, step 4: fig. 3 is a schematic block diagram of packet parsing, and referring to fig. 3, the packet parsing process includes the following steps:
1) Writing the obtained second path of data flow into a shared Buffer area of the FPGA;
2) The FLASH controls the writing of data into the DDR3 for storage by configuring the FPGA;
3) The processor reads the data written into the DDR3 from the FPGA through the PCIeX4 chip;
4) The processor acquires the first 4 bytes of the MAC address field of the data frame and judges the frame type according to the first 4 bytes;
5) The processor data distribution module is responsible for continuously distributing the captured second path of data address to a protocol stack corresponding to the frame type;
6) The processor data recovery module is responsible for continuously recovering the data processed by each protocol stack and returning the address space to the bottom layer data
7) Two data queues are distributed for each protocol stack thread and are respectively used for storing a data block to be analyzed and an analyzed data block;
and 5: and outputting the analyzed data packet through upper computer software.
Step 6: the bit error rate testing process is shown in fig. 4 and 5, and the bit error rate testing principle in fig. 4 and the bit error rate testing flow in fig. 5 specifically include the following steps:
1) The upper computer inputs theoretical data through a network port to generate a test sequence;
2) The control communication module of the upper computer starts to receive the test sequence and sends the test sequence to the processor module;
3) Controlling the communication module to detect the FIFO state of the upper computer receiver in the receiving process, and when the FIFO is half full, the upper computer starts to read the test sequence received by the processor module;
4) Comparing with the analyzed data block, counting the number of error codes and calculating the error rate;
5) When the control communication module of the upper computer starts to receive the test sequence, the control communication module of the upper computer judges whether the sending code of the theoretical data is enough; and when the sending code of the theoretical data is enough, the control communication module of the upper computer stops sending the test sequence to the processor module and stops receiving the test sequence.
6) When the FIFO is full, the communication module is controlled to finish receiving the test sequence, and the upper computer displays the counted error code number and the calculated error code rate;
and 7: for fault injection in a bus network, fig. 6 is a schematic diagram of a fault injection process, which is shown in fig. 6 and includes the following steps:
1) The upper computer identifies the lead code of the second path of data and identifies the position of the fault code injected into the bus network according to the requirement;
2) Programming fault codes through a JTAG port of the FPGA;
3) The fault code is output to the pluggable module 2 after passing through the level one-to-two chip;
4) The pluggable module 2 injects a fault code into the bus network through the transmission port TX 1.
Claims (8)
1. A method for high speed real time data capture without interference to communications, the method comprising:
capturing actual data on the bus network, generating first data and second data through a level-one-to-two chip, transmitting the first data back to the bus network, and enabling the second data to enter a data packet analysis module;
the data packet analysis module comprises an FPGA channel and a processor module which are connected in sequence; the data packet analysis module analyzes the second data and writes the acquired second data into a shared Buffer of the FPGA channel; the processor module analyzes different data frame formats of the second data according to different protocol stacks and stores the analyzed data blocks;
the upper computer reads the analyzed data block in the processor module; the upper computer inputs theoretical data through a network port and generates a test sequence; the control communication module of the upper computer starts to receive the test sequence and sends the test sequence to the processor module; controlling the communication module to detect the FIFO state of the upper computer receiver in the receiving process, when the FIFO is half full, the upper computer starts to read the test sequence received by the processor module, compares the test sequence with the analyzed data block, counts the error code number and calculates the error code rate; when the FIFO is full, the upper computer displays the counted error code number and the calculated error code after receiving the test sequence;
when the control communication module of the upper computer starts to receive the test sequence, the control communication module of the upper computer judges whether the sending code of the theoretical data is enough; and when the sending code of the theoretical data is enough, the control communication module of the upper computer stops sending the test sequence to the processor module and stops receiving the test sequence.
2. The real-time data capture method of claim 1, wherein the method comprises: the data packet analysis module further comprises a PCIe exchange chip, and the PCIe exchange chip is in data connection with the FPGA channel and the processor module respectively so as to improve data transmission between the FPGA channel and the processor module.
3. The real-time data capture method of claim 1, wherein the method comprises:
the process of the data packet analysis module for analyzing the second data comprises the following steps: the processor module acquires the first 4 bytes of the MAC address field of the data frame in the second data and judges the format of the data frame according to the first 4 bytes; the processor module allocates the data address of the second data to the corresponding protocol stack according to the data frame format; the processor module recovers the data processed by each protocol stack and returns the address space to the second data; and the thread of each protocol stack is respectively distributed with two data queues which are respectively used for storing the data block to be analyzed and the analyzed data block in the second data.
4. The real-time data capture method of claim 1, further comprising: the upper computer identifies the lead code of the second data and identifies the position of the fault code injected into the FPGA channel according to the requirement; programming fault codes through a JTAG port of the FPGA channel; and injecting the fault code into the bus network by the FPGA channel.
5. The real-time data capturing method of claim 1, wherein the level-one-two chip is a CML or LVDS level-one-two chip.
6. The real-time data capturing method of claim 1, wherein the actual data on the bus network is inputted into the level-one-to-two chip through a pluggable module; the first data is output to the bus network through the pluggable module.
7. The method of real-time data capture of claim 6, wherein the pluggable module is a small hot-pluggable transceiver module.
8. The real-time data capture method of claim 2, wherein the FPGA channel, PCIe switch chip, and processor module are connected through a PCIe x4 bus interface.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4048481A (en) * | 1974-12-17 | 1977-09-13 | Honeywell Information Systems Inc. | Diagnostic testing apparatus and method |
| CN203014988U (en) * | 2012-12-28 | 2013-06-19 | 中国航空工业集团公司第六三一研究所 | High-speed video shunt circuit |
| CN104471880A (en) * | 2012-05-02 | 2015-03-25 | 莱特普茵特公司 | Method for efficient parallel testing of time division duplex (TDD) communications systems |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110650066B (en) * | 2019-09-27 | 2023-04-25 | 南京工程学院 | Bus communication detection system based on embedded type and reliability detection method thereof |
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- 2020-09-02 CN CN202010912593.4A patent/CN112104489B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4048481A (en) * | 1974-12-17 | 1977-09-13 | Honeywell Information Systems Inc. | Diagnostic testing apparatus and method |
| CN104471880A (en) * | 2012-05-02 | 2015-03-25 | 莱特普茵特公司 | Method for efficient parallel testing of time division duplex (TDD) communications systems |
| CN203014988U (en) * | 2012-12-28 | 2013-06-19 | 中国航空工业集团公司第六三一研究所 | High-speed video shunt circuit |
Non-Patent Citations (3)
| Title |
|---|
| 王文等.基于FPGA的TCP/IP网络通信***的设计与实现.《现代电子技术》.2018,(第08期), * |
| 王荣阳等.紫外光通信误码率测试***设计.《半导体光电》.2012,(第05期), * |
| 陈旭等.电力***中无线监控***通信方法研究.《测控技术》.2010,(第03期), * |
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