CN112036113A - ESD protection method and system - Google Patents
ESD protection method and system Download PDFInfo
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- CN112036113A CN112036113A CN202010785616.XA CN202010785616A CN112036113A CN 112036113 A CN112036113 A CN 112036113A CN 202010785616 A CN202010785616 A CN 202010785616A CN 112036113 A CN112036113 A CN 112036113A
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000010586 diagram Methods 0.000 claims abstract description 52
- 238000009826 distribution Methods 0.000 claims abstract description 13
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000004590 computer program Methods 0.000 claims description 3
- 238000005259 measurement Methods 0.000 claims description 3
- 238000003860 storage Methods 0.000 claims description 3
- 238000002372 labelling Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 abstract description 2
- 239000000306 component Substances 0.000 description 99
- 239000004020 conductor Substances 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0067—Devices for protecting against damage from electrostatic discharge
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Abstract
The invention relates to the technical field of electronic equipment detection, in particular to an ESD protection method and system, wherein the ESD protection method comprises the following steps: acquiring a circuit layout and a circuit diagram; learning the circuit diagram; identifying the electronic components in the circuit layout according to the learning result; acquiring the position distribution of the core electronic components according to the identification result; marking the position of the core electronic component; and placing the ESD device according to the marking result and the ESD rule. By the ESD protection method and system, the ESD device can be automatically arranged on the circuit layout according to the position relation of the electronic components.
Description
Technical Field
The invention relates to the technical field of electronic equipment detection, in particular to an ESD protection method and system.
Background
ESD (Electro-Static discharge) is a discipline developed since the middle of the 20 th century to study generation and damage of Static electricity and electrostatic protection. Therefore, it is customary internationally to refer to the equipment for electrostatic protection collectively as ESD, herein termed electrostatic impeders.
ESD can occur when a charged conductor approaches another conductor, first, a strong electric field is established between the two conductors, causing breakdown due to the electric field, and when the voltage between the two conductors exceeds the breakdown voltage of the air and insulating medium between them, an arc is created that is sustained until the two conductors are shorted together or the current is so low that it cannot sustain an arc. It follows that ESD protection is a very important process.
Many product design engineers usually take the problem of antistatic release into consideration when the product enters the production ring, if the electronic device passes the antistatic release test differently, the engineers generally will search for a solution that does not destroy the original design with overtime, however, the final solution usually adopts expensive components and parts, and also adopts manual assembly in the manufacturing process, even needs redesign, therefore, the progress of the product must be influenced.
In order to solve the above problems and find an anti-ESD scheme more simply, the present invention provides an ESD protection method and system.
Disclosure of Invention
The invention provides an ESD protection method and system. By the ESD protection method and system, the ESD device can be automatically arranged on the circuit layout according to the position relation of the electronic components.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
an ESD protection method comprising:
acquiring a circuit layout and a circuit diagram;
learning the circuit diagram;
identifying the electronic components in the circuit layout according to the learning result;
acquiring the position distribution of the core electronic components according to the identification result;
marking the position of the core electronic component;
and placing the ESD device according to the marking result and the ESD rule.
Preferably, the method for identifying the electronic component in the circuit layout according to the learning result comprises the following steps:
acquiring a circuit diagram;
the type, the model and the position relation of electronic components in the circuit diagram are learned for the first time;
after the first learning is finished, performing second learning on the connection relation between the electronic components in the circuit diagram;
and identifying the electronic components in the circuit layout according to the two learning results. The circuit diagram can show the types and the connection relations of the electronic components more clearly, but the circuit diagram can show the actual state of the product, the distance between each electronic component and the position more clearly. Therefore, it is very meaningful to analyze the ESD of the circuit layout by recognizing the electronic devices of the circuit layout after learning the circuit diagram. The circuit layout can be more accurately identified through the study of the circuit diagram.
Further preferably, the method for learning the connection relationship between the electronic components in the circuit diagram for the second time includes:
constructing a data set, wherein the data set is used for storing the types of the electronic components in the circuit diagram and the corresponding models of the electronic components;
and acquiring information of other electronic components connected with each pin of the electronic component, and storing the information in the constructed data set.
Further preferably, the method for obtaining the position distribution of the core electronic component according to the recognition result includes:
identifying electronic components in the circuit layout, and primarily determining a core electronic element device and characteristic electronic components;
and after the preliminary identification is finished, presuming the electronic components which cannot be identified according to the information of other electronic components connected with the pins of the characteristic electronic components.
Further preferably, the step of identifying the electronic components in the circuit layout to preliminarily determine the core electronic component and the characteristic electronic component specifically includes:
identifying a core electronic element device and a characteristic electronic component in the circuit layout;
and after the identification is finished, determining the positions of other peripheral electronic components according to the pin relation of the core electronic component. In the method, the core device and the electronic components with the characteristics are firstly identified, and the electronic components which cannot be identified can be objectively presumed according to the connection relation of pins of the electronic components in the circuit diagram, so that the identification result is more accurate.
Preferably, the method for marking the position of the core electronic component includes:
acquiring the position of a core electronic component in a circuit layout;
and measuring the distances between the pins of the core electronic component and the pins of other electronic components, and marking the measurement result.
Further preferably, the method for placing the ESD device according to the marking result and the ESD rule comprises:
obtaining a marking result;
and giving the optimal placement position of the ESD device through the ESD rules and the marking result.
An ESD protection system comprising:
an acquisition module: the acquisition module is used for acquiring a circuit layout and a circuit diagram;
a learning module: the learning module is used for learning the circuit diagram;
an identification module: the identification module is used for identifying the electronic components in the circuit layout according to the learning result;
a core device identification module: the core device identification module is used for acquiring the position distribution of the core electronic components according to the identification result;
a marking module: the marking module is used for marking the position of the core electronic component;
arranging a module: the arrangement module is used for arranging the ESD device according to the marking result and the ESD rule.
A computer readable storage medium having stored thereon computer program instructions adapted to be loaded by a processor and to execute a method of ESD protection.
A mobile terminal comprises a processor and a memory, wherein the processor is used for executing a program stored in the memory so as to realize an ESD protection method.
Compared with the prior art, the invention has the beneficial effects that: by the ESD protection method and system, the ESD device can be automatically arranged on the circuit layout according to the position relation of the electronic components. Specifically, after the circuit diagram is learned, the positions of the components in the circuit diagram are identified, the distances between the components are measured, and according to the distances and the ESD rules, after the circuit diagram is generated, the ESD devices can be reasonably arranged according to the position relations of all the electronic components in the circuit diagram and the ESD rules, so that labor is saved.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a schematic flow chart of a method for ESD protection according to the present invention;
fig. 2 is a block diagram of an ESD protection method system according to the present invention.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic drawings and illustrate only the basic flow diagram of the invention, and therefore they show only the flow associated with the invention.
Example 1
As shown in fig. 1, the present invention is an ESD protection method, specifically:
s1, obtaining a circuit layout and a circuit diagram;
s2, learning the circuit diagram;
s3, identifying the electronic components in the circuit layout according to the learning result;
s4, acquiring the position distribution of the core electronic components according to the recognition result;
s5, marking the position of the core electronic component;
and S6, placing the ESD device according to the marking result and the ESD rule.
Step S1: and acquiring a circuit layout and a circuit diagram. And inputting the circuit layout and the circuit diagram into an identification system for identification.
Step S2: the circuit diagram is learned. Since the type and model of the electronic components and the connection relationship between the electronic components are clearly shown in the circuit diagram, the circuit diagram is learned to acquire the above information.
Step S3: and identifying the electronic components in the circuit layout according to the learning result. The circuit layout is different from the circuit diagram in that the circuit diagram can clearly show what kind of electronic components are included and the connection relationship among a plurality of electronic components. In the circuit layout, the distance between the pins of the electronic component in the actual layout can be clearly reflected. Therefore, when the ESD device is added, the ESD device is placed at a more proper position according to the distance between the actual pins, and the design requirement is better met.
The method for identifying the electronic components in the circuit layout according to the learning result comprises the following steps: acquiring a circuit diagram; the type, the model and the position relation of electronic components in the circuit diagram are learned for the first time; after the first learning is finished, performing second learning on the connection relation between the electronic components in the circuit diagram; and identifying the electronic components in the circuit layout according to the two learning results. Here, if the electronic component in the circuit diagram cannot be identified, the electronic component may be manually selected, and the model and type of the device may be manually input.
The method for learning the connection relationship between the electronic components in the circuit diagram for the second time comprises the following steps: constructing a data set, wherein the data set is used for storing the types of the electronic components in the circuit diagram and the corresponding models of the electronic components; and acquiring information of other electronic components connected with each pin of the electronic component, and storing the information in the constructed data set.
Step S4: and acquiring the position distribution of the core electronic components according to the identification result.
The method for acquiring the position distribution of the core electronic component according to the identification result comprises the following steps: identifying electronic components in the circuit layout, and primarily determining a core electronic element device and characteristic electronic components; and after the preliminary identification is finished, presuming the electronic components which cannot be identified according to the information of other electronic components connected with the pins of the characteristic electronic components.
The method is characterized in that the electronic components in the circuit layout are identified, and the preliminary determination of the core electronic component and the characteristic electronic components is as follows: identifying a core electronic element device and a characteristic electronic component in the circuit layout; and after the identification is finished, determining the positions of other peripheral electronic components according to the pin relation of the core electronic component.
In this step, as the number of pins of some core electronic components in the circuit layout is large, the core electronic components are well recognized in the recognition process, and after the number of pins is recognized, the number of pins of the core electronic components in the data set is compared to determine which electronic component the core electronic component is. The preliminary identification can identify a plurality of core electronic components, and some devices with characteristics can be identified, such as a triode and an MOS tube. And judging other electronic components in the circuit layout according to the connection relation of peripheral circuits of pins of the core electronic components in the data set. After the preliminary matching is completed, the connection relation of the peripheral circuit of the core device is found. After the initial identification is completed, other circuits are not identified except peripheral circuits of the core electronic components, and at the moment, the final identification of the circuit layout is completed by carrying out conjecture according to the connection relations between the identified other electronic components and other electronic components.
Step S5: the positions of the core electronic components are marked.
The method for marking the position of the core electronic component comprises the following steps: acquiring the position of a core electronic component in a circuit layout; and measuring the distances between the pins of the core electronic component and the pins of other electronic components, and marking the measurement result.
Step S6: and placing the ESD device according to the marking result and the ESD rule.
The method for placing the ESD device according to the marking result and the ESD rule comprises the following steps: obtaining a marking result; and giving the optimal placement position of the ESD device through the ESD rules and the marking result. For example: ESD devices can be placed at multiple locations according to ESD rules, but placement of ESD devices according to the distance between pins, i.e., which actual location in the circuit layout is a relatively spacious location, can facilitate mounting of electronic components in subsequent production.
Example 2
As shown in fig. 2, the present invention provides an ESD protection method system:
the acquisition module 1: the acquisition module is used for acquiring a circuit layout and a circuit diagram;
the learning module 2: the learning module is used for learning the circuit diagram;
the identification module 3: the identification module is used for identifying the electronic components in the circuit layout according to the learning result;
core device identification module 4: the core device identification module is used for acquiring the position distribution of the core electronic components according to the identification result;
the marking module 5: the marking module is used for marking the position of the core electronic component;
the arrangement module 6: the arrangement module is used for arranging the ESD device according to the marking result and the ESD rule.
The acquisition module 1 is used for acquiring the circuit layout and the circuit diagram and transmitting the acquired circuit layout and circuit diagram to the learning module. The learning module 2 is used for learning the circuit diagram and transmitting the learning result and the circuit diagram to the identification module for identification. The identification module 3 is used for identifying the electronic components in the circuit layout according to the learning result and transmitting the identification result of the electronic components to the core component identification module. The core device identification module 4 is used for acquiring the position distribution of the core electronic components according to the identification result and transmitting the distribution condition to the marking module. The marking module 5 is used for marking the position of the core electronic component and transmitting the marking result to the arrangement module. The placement module 6 is used for placing the ESD device according to the marking result and the ESD rule.
A computer readable storage medium having stored thereon computer program instructions adapted to be loaded by a processor and to execute a method of ESD protection.
A mobile terminal comprises a processor and a memory, wherein the processor is used for executing a program stored in the memory so as to realize an ESD protection method.
The above detailed description is specific to possible embodiments of the present invention, and the above embodiments are not intended to limit the scope of the present invention, and all equivalent implementations or modifications that do not depart from the scope of the present invention should be included in the present claims.
Claims (10)
1. An ESD protection method, comprising:
acquiring a circuit layout and a circuit diagram;
learning the circuit diagram;
identifying the electronic components in the circuit layout according to the learning result;
acquiring the position distribution of the core electronic components according to the identification result;
marking the position of the core electronic component;
and placing the ESD device according to the marking result and the ESD rule.
2. The ESD protection method according to claim 1, wherein the method for identifying the electronic device in the circuit layout according to the learning result comprises:
acquiring a circuit diagram;
the type, the model and the position relation of electronic components in the circuit diagram are learned for the first time;
after the first learning is finished, performing second learning on the connection relation between the electronic components in the circuit diagram;
and identifying the electronic components in the circuit layout according to the two learning results.
3. The ESD protection method according to claim 2, wherein the second learning method for the connection relationship between the electronic components in the circuit diagram comprises:
constructing a data set, wherein the data set is used for storing the types of the electronic components in the circuit diagram and the corresponding models of the electronic components;
and acquiring information of other electronic components connected with each pin of the electronic component, and storing the information in the constructed data set.
4. The ESD protection method according to claim 3, wherein the method for obtaining the location distribution of the core electronic component according to the recognition result comprises:
identifying electronic components in the circuit layout, and primarily determining a core electronic element device and characteristic electronic components;
and after the preliminary identification is finished, presuming the electronic components which cannot be identified according to the information of other electronic components connected with the pins of the characteristic electronic components.
5. The ESD protection method according to claim 4, wherein the first step of identifying the electronic components in the circuit layout and the preliminary determination of the core electronic component and the characteristic electronic component are specifically:
identifying a core electronic element device and a characteristic electronic component in the circuit layout;
and after the identification is finished, determining the positions of other peripheral electronic components according to the pin relation of the core electronic component.
6. The ESD protection method of claim 1, wherein the method of marking the location of the core electronic component comprises:
acquiring the position of a core electronic component in a circuit layout;
and measuring the distances between the pins of the core electronic component and the pins of other electronic components, and marking the measurement result.
7. The ESD protection method of claim 6, wherein the ESD device placement method according to the labeling result and the ESD rule comprises:
obtaining a marking result;
and giving the optimal placement position of the ESD device through the ESD rules and the marking result.
8. An ESD protection system, comprising:
an acquisition module: the acquisition module is used for acquiring a circuit layout and a circuit diagram;
a learning module: the learning module is used for learning the circuit diagram;
an identification module: the identification module is used for identifying the electronic components in the circuit layout according to the learning result;
a core device identification module: the core device identification module is used for acquiring the position distribution of the core electronic components according to the identification result;
a marking module: the marking module is used for marking the position of the core electronic component;
arranging a module: the arrangement module is used for arranging the ESD device according to the marking result and the ESD rule.
9. A computer-readable storage medium, characterized in that it stores computer program instructions adapted to be loaded by a processor and to execute the method of any of claims 1 to 7.
10. A mobile terminal comprising a processor and a memory, the processor being configured to execute a program stored in the memory to implement the method of any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010785616.XA CN112036113A (en) | 2020-08-06 | 2020-08-06 | ESD protection method and system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010785616.XA CN112036113A (en) | 2020-08-06 | 2020-08-06 | ESD protection method and system |
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| CN112036113A true CN112036113A (en) | 2020-12-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115935890A (en) * | 2022-12-19 | 2023-04-07 | 海光集成电路设计(北京)有限公司 | Circuit identification method and device, electronic equipment and computer readable storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105092994A (en) * | 2014-04-30 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | ESD detection method and device and ESD debugging method and device |
| CN107977477A (en) * | 2016-10-21 | 2018-05-01 | 上海复旦微电子集团股份有限公司 | The domain generation method and device of fpga chip |
-
2020
- 2020-08-06 CN CN202010785616.XA patent/CN112036113A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105092994A (en) * | 2014-04-30 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | ESD detection method and device and ESD debugging method and device |
| CN107977477A (en) * | 2016-10-21 | 2018-05-01 | 上海复旦微电子集团股份有限公司 | The domain generation method and device of fpga chip |
Non-Patent Citations (2)
| Title |
|---|
| 董培培等: "CMOS集成电路ESD保护技术研究", 《微处理机》, no. 5, 31 October 2016 (2016-10-31), pages 9 - 12 * |
| 黄昀荃等: "ESD保护结构中的SCR设计", 《电子与封装》, vol. 11, no. 7, 31 July 2011 (2011-07-31), pages 29 - 34 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115935890A (en) * | 2022-12-19 | 2023-04-07 | 海光集成电路设计(北京)有限公司 | Circuit identification method and device, electronic equipment and computer readable storage medium |
| CN115935890B (en) * | 2022-12-19 | 2024-05-31 | 海光集成电路设计(北京)有限公司 | Circuit identification method, circuit identification device, electronic equipment and computer readable storage medium |
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