CN111832734B - Design method of quantum image multiplication operation and simulation implementation method thereof - Google Patents
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Abstract
The invention relates to a design method of quantum image multiplication operation and a simulation implementation method thereof, belonging to the technical field of image processing. The quantum image multiplication design implementation steps are as follows: (1) designing a quantum multiplier; (2) Preparing two superimposed quantum images using a quantum image representation (NEQR) model; (3) Based on the two overlapped quantum images and the quantum multiplier, the multiplication of the two quantum images is realized; (4) simulation implementation of quantum image multiplication. The invention simultaneously provides a quantum circuit diagram of each step, and realizes the design of quantum image multiplication. The invention builds an experiment platform and performs simulation by using an open source quantum cloud simulator provided by a classical computer and an IBM laboratory. The quantum image multiplication operation is simulated and realized by using Python language by utilizing the open source quantum computing toolkit QISKIT provided by IBM company and the package management and environment management functions provided by Anaconda.
Description
Technical Field
The invention belongs to the technical field of image processing, and relates to a design method for quantum image multiplication operation and a simulation implementation method thereof.
Background
The concept of quantum images was first proposed by scientists such as Venagas-Andraca in 2003, and quantum algorithm Grover search algorithm was first applied to the field of image processing in Beach et al in the same year. In 2011, le et al proposed a quantum image Flexible Representation (FRQI) model, which represents image information in an overlapped state, and based on the model, realizes geometric transformation and image transformation of images; in 2013, zhang et al proposed an enhanced quantum image representation (netr) model, which extended the gray information of the FRQI model stored in the single-qubit probability frame to the multi-qubit basis vector, and maintained its operational flexibility while allowing accurate control of gray information, and allowed accurate recovery and reading of images in limited number of quantum measurements. The quantum algorithm has the capability of exponentially accelerating the corresponding classical algorithm, and is considered as one of effective means for solving the bottleneck of the computing capacity of the current physical system.
The quantum image multiplication operation is based on a quantum multiplier, can be applied to the fields of image enhancement, target extraction and the like in quantum image processing, and is a widely applied quantum algorithm. At present, according to literature investigation, theoretical researches related to a quantum multiplier exist, but the designed quantum multiplier is not simulated in a quantum simulator, but the invention focuses on realizing quantum image multiplication operation design and simulation realization thereof, and improves and optimizes the existing quantum multiplier. There are few studies on the design of algorithms and simulation implementations of quantum image multiplication. Therefore, the searching of the design and simulation realization of the quantum image multiplication operation has important significance.
Disclosure of Invention
In view of the above, the present invention is directed to a design method for quantum image multiplication and a simulation implementation method thereof.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a design method of quantum image multiplication operation and a simulation implementation method thereof, the method comprises the following steps:
step 1: designing a quantum multiplier by utilizing a quantum full adder and a right shift operation to realize the product of two n-bit binary numbers;
step 2: preparing two quantum images which share position information and are in an overlapped state based on a quantum image NEQR representation model;
step 3: the quantum multiplier acts on the two prepared quantum images to realize multiplication of the two quantum images;
step 4: an experiment platform is built by adopting a classical computer and an open source quantum cloud simulator provided by an IBM laboratory, and simulation is carried out; the quantum image multiplication operation is simulated and realized by using Python language by utilizing the open source quantum computing toolkit QISKIT provided by IBM company and the package management and environment management functions provided by Anaconda.
Optionally, the quantum full adder is improved, a zero-setting operation is used for multiplexing two-bit quantum bits representing carry information and one-bit quantum bit representing control bit information, so that auxiliary quantum bits are kept to be three bits all the time, the number of quantum bits used by the quantum adder is reduced, improvement and optimization of the quantum adder are realized, and an improved quantum multiplier is designed by combining an implementation mode of a right shift operation function.
Optionally, the step 2 specifically includes:
the two images share the position information, and a foundation is laid for the parallelism of the multiplication operation of the two subsequent quantum images;
in the preparation process of the image gray information, the auxiliary bits are utilized to transmit the position information, the position information and the gray information are in one-to-one correspondence, and the auxiliary bits are multiplexed by utilizing the zero setting operation, so that only two constant auxiliary bits are needed in the whole preparation process of the image, the two constant auxiliary bits are not increased along with the increase of the image size, and the two auxiliary bits representing the carry information in the quantum multiplier can be used after multiplexing, thereby realizing the improvement and the optimization of the preparation process of the quantum image.
Optionally, the zeroing operation is to place the state of the qubit into the |0> state.
The invention has the beneficial effects that:
1. the method successfully fills the blank of quantum image multiplication operation in design and IBM Q cloud platform simulation, and designs the highly parallel quantum image multiplication operation.
2. The auxiliary bits are multiplexed by using the zero setting operation, so that the quantum bit quantity required by the quantum multiplier and the quantum image preparation is greatly reduced, and the simulation realization of the algorithm is smoothly realized.
3. The invention realizes the highly parallel quantum image multiplication operation, improves the simulation efficiency, and also compacts the foundation for the theoretical experiments of other subsequent quantum image processing algorithms.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the specification.
Drawings
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in the following preferred detail with reference to the accompanying drawings, in which:
FIG. 1 is a technical roadmap of the method of the invention;
FIG. 2 is a block diagram illustrating the steps of a binary multiplication operation according to the present invention;
FIG. 3 is a generic quantum gate of the present invention; (a) is NOT Gate; (b) is Hadamard Gate; (c) is CNOT Gate; (d) is Toffoli Gate;
FIG. 4 is a quantum circuit diagram of a one-bit quantum full adder of the present invention; (a) is a one-bit quantum full adder specific circuit; (b) is a simplified diagram of a one-bit quantum full adder;
FIG. 5 is a diagram of a quantum full adder circuit of the present invention; (a) is an n-bit quantum full adder specific circuit diagram; (b) is a simplified diagram of an n-bit quantum full adder;
FIG. 6 is a circuit diagram of a quantum multiplier according to the present invention; (a) is a circuit diagram of a quantum multiplier; (b) simplifying the circuit diagram for the quantum multiplier;
FIG. 7 is a quantum circuit diagram of gray value preparation of a quantum image of the present invention at location 1010;
FIG. 8 is a quantum circuit diagram of the present invention by quantum image multiplication;
FIG. 9 is a 4×4 sized quantum image squaring simulation diagram of the present invention; (a) A probability histogram after the 4 multiplied by 4 quantum image is multiplied; (b) a 4 x 4 quantum image involved in the squaring operation; (c) is a visual view of the quantum image after squaring;
FIG. 10 is a simulation of the multiplication of two quantum images of size 4 x 4 of the present invention with an extraction target; (a) A probability histogram obtained by multiplying two 4×4 quantum images; (b) one of the quantum images participating in the multiplication operation; (c) another quantum image participating in the multiplication operation; (d) Is a visual view of the quantum image after multiplication of the two quantum images.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the illustrations provided in the following embodiments merely illustrate the basic idea of the present invention by way of illustration, and the following embodiments and features in the embodiments may be combined with each other without conflict.
Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to limit the invention; for the purpose of better illustrating embodiments of the invention, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numbers in the drawings of embodiments of the invention correspond to the same or similar components; in the description of the present invention, it should be understood that, if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc., that indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but not for indicating or suggesting that the referred device or element must have a specific azimuth, be constructed and operated in a specific azimuth, so that the terms describing the positional relationship in the drawings are merely for exemplary illustration and should not be construed as limiting the present invention, and that the specific meaning of the above terms may be understood by those of ordinary skill in the art according to the specific circumstances.
FIG. 1 is a technical roadmap of the method of the invention; FIG. 2 is a block diagram illustrating the steps of a binary multiplication operation according to the present invention; FIG. 3 is a generic quantum gate of the present invention; (a) is NOT Gate; (b) is Hadamard Gate; (c) is CNOT Gate; (d) is Toffoli Gate; FIG. 4 is a quantum circuit diagram of a one-bit quantum full adder of the present invention; (a) is a one-bit quantum full adder specific circuit; (b) is a simplified diagram of a one-bit quantum full adder; FIG. 5 is a diagram of a quantum full adder circuit of the present invention; (a) is an n-bit quantum full adder specific circuit diagram; (b) is a simplified diagram of an n-bit quantum full adder; FIG. 6 is a circuit diagram of a quantum multiplier according to the present invention; (a) is a circuit diagram of a quantum multiplier; (b) simplifying the circuit diagram for the quantum multiplier; FIG. 7 is a quantum circuit diagram of gray value preparation of a quantum image of the present invention at location 1010; where the two images share position information, the gray values of the two images are 7 (binary 111) and 1 (binary 001) at position 1010, respectively. FIG. 8 is a quantum circuit diagram of the present invention by quantum image multiplication; FIG. 9 is a 4×4 sized quantum image squaring simulation diagram of the present invention; (a) A probability histogram after the 4 multiplied by 4 quantum image is multiplied; (b) a 4 x 4 quantum image involved in the squaring operation; (c) is a visual view of the quantum image after squaring; FIG. 10 is a simulation of the multiplication of two quantum images of size 4 x 4 of the present invention with an extraction target; (a) A probability histogram obtained by multiplying two 4×4 quantum images; (b) one of the quantum images participating in the multiplication operation; (c) another quantum image participating in the multiplication operation; (d) Is a visual view of the quantum image after multiplication of the two quantum images.
1. Improvements and optimizations for quantum multipliers
(1) Binary multiplication step
The following describes the binary multiplication step employed, taking fig. 2 as an example only, and this multiplication step is applicable to multiplication of any two binary numbers. In fig. 2, 1011 is a multiplicand and 1101 is a multiplier, taking 1011×1101 as an example. After the partial product is set to zero, the operation steps are as follows: in the first step, the lowest order bit of the multiplier is set as the control bit, and if the control bit is 1, the multiplicand is added, and if the control bit is 0, 0 is added. And secondly, shifting the summation result by one bit to the right. The two steps are then cycled, but the second control bit is the next highest order of the multiplier. And when the loop is recycled, the control bit is the last higher one. For an n-bit binary multiplied number by an m-bit binary multiplier, m additions and m-1 right shift operations are required.
(2) Design quantum adder
According to the binary multiplication step, it is necessary to control whether the adder performs addition or not with each bit of the multiplier from the lower bit to the upper bit in sequence, so each bit of the multiplier will be used as a control bit, and addition is performed when the control bit is 1, otherwise, no addition is performed. FIG. 4 (a) is a detailed circuit diagram of a bit-controlled one-bit quantum full adder, in which |con i >A control bit representing a control quantum adder; i a i >And |b i >Qubit representing input summand and summand, |s i >Representing |a i +b i >Outputting a result bit; c i-1 >、|C i >And |ass>Is three-bit constant auxiliary quantum bit, |ass>For storing control bit information, the other two bits |C i-1 >And |C i ＝0>Is an auxiliary representing carry informationAuxiliary quantum bit, after passing through a one-bit quantum adder, |C i ＝0>Output is |C i >Prepare for the next addition. The one-bit quantum full adder of FIG. 4 (a) uses a control NOT gate, six Toffoli gates are shown in FIG. 3 (d), FIG. 4 (b) is a simplified diagram of the one-bit quantum full adder, to highlight the summand |a involved in the addition i >And the addend |b i >And input carry information |C i -1>Sum |S in operation result i >And output carry information |C i >Here, only the qubits corresponding to the addition are added with black dots.
The n one-bit quantum adders are overlapped together, and auxiliary bits are multiplexed through zero setting operation, so that the number of required auxiliary quantum bits cannot be increased along with the increase of digital bits participating in addition operation, and therefore, the n-bit quantum full adder with three constant auxiliary quantum bits is realized, and the addition of two n bits can be realized. Fig. 5 (a) is a circuit diagram of an n-bit quantum full adder, and fig. 5 (b) is a simplified diagram of an n-bit quantum full adder, in which auxiliary qubits are omitted. The following is a process for implementing two-digit addition for an n-bit quantum full adder.
Let |a>＝|a n a n-1 …a 2 a 1 >And |b>＝|b n b n-1 …b 2 b 1 >The input quantum state of FIG. 5 is two binary numbers to be processed, the control bit |con of the quantum adder i >Initial state of |0>Three-bit auxiliary qubit of (i) input quantum state isWherein represents |a>＝|a n a n-1 …a 2 a 1 >The qubit is used to store the sum of the two numbers after addition. The output quantum state is +.>Assuming that the quantum full adder operation is denoted by the symbol QADD, the process of adding the two numbers can be expressed as:
(3) Implementation mode of right shift operation function
Assuming that the multiplicand has an n-bit qubit number and the multiplier has an m-bit qubit number, the two numbers multiply by the maximum required m+n-bit qubit. The main idea of multiplication calculation is to reserve first a constant number of qubits in m+n bits initialized to the state |0> for storing the multiplication result, i.e., |00..0 >, where m+n zeros are included, from right to left in order from lower to higher. According to the above steps of binary multiplication, in the first addition, the addend is aligned with the lowest bit (rightmost bit) of the m+n bit, and the result is stored in the m+n bit, and when the next addition is performed, the addend is aligned with the next lower bit of the m+n bit, and this alignment can be achieved by selecting the corresponding qubit participation operation in the quantum circuit, such as the adder used in fig. 5, wherein the qubit marked with the black dot on the left side of the adder is the qubit representing the added number, the addend and the carry information participating in the addition, which corresponds to shifting the addition result by one bit to the right, and so on, each time the addition is performed, the corresponding right shift operation is performed.
(4) Completing a quantum multiplier design
According to the implementation steps of binary multiplication, the design of the multiplier can be realized by using the n-bit quantum full adder and right shift operation. As shown in fig. 6, the multiplier requires n-bit qubit numbers to represent an n-bit binary multiplicand; the m-bit qubit number represents a multiplier of an m-bit binary system; the result is stored in an m+n-bit qubit number; the three-bit quantum bit number is used as an auxiliary bit, wherein two auxiliary bits are used for representing carry information |C of the n-bit quantum full adder i >And |C i-1 >One bit is used to store control bit information. The quantum multiplier circuit mainly comprises a quantum full adder controlled by taking a multiplier as a control bit, a control NOT gate and a zero setting gate. The multiplication is implemented by using the multiplier from low order to high order to control whether the adder performs additionIf the control bit is 1, the addition is performed, and if the control bit is 0, the addition is not performed. And then using a control NOT gate to store the carry information output by the n-bit quantum full adder to the corresponding quantum bit, and combining the method for realizing the right shift operation function to realize multiplication of two numbers.
Let n-bit binary number a be stored in quantum state |a>＝|a n a n-1 …a 2 a 1 >In which an m-bit binary number b is stored in the quantum state |b>＝|b m b m-1 …b 2 b 1 >In FIG. 6, the input quantum state is two binary numbers to be processed, the quantum state storage result bit of n+m quantum bits with initial state of 0, and three constant auxiliary bits, namely the input quantum state isThe output quantum state is +.>Assuming that the quantum multiplier operation is represented by the symbol QMUL, the process of multiplying two numbers can be expressed as:
2. preparation of two parallel quantum images using a quantum image representation (NEQR) model
Taking the following two quantum images as an example, two superimposed quantum wires are prepared using the NEQR expression. Images for the remaining greyscale dimensions may be prepared with such a boost.
The matrix of these two 4 x 4 images is expressed as:
taking the preparation of pixels at two superimposed quantum image locations 0101 as an example. Fig. 7 is a quantum circuit for preparing this pixel. The pixel is represented in the NEQR expression in the form of a binary string 1110010101, wherein the four following bits represent position information, the first three bits represent the gray information of the first quantum image at that position, and the fourth through sixth bits represent the gray information of the second quantum image at that position.
Gray information: from top to bottom in fig. 7, the first 3 qubits (qr 0 -qr 2 ) Gradation information 111 representing the first quantum image, followed by 3 quantum bits (qr 3 -qr 5 ) Gray information 001 representing the second quantum image. Thus, the first 6 quantum wire outputs should result in 111001.
Position information: qr (qr) 6 →qr 9 For the corresponding position information, the position information in the y direction and the position information in the x direction are half of each other, wherein qr 6 And qr (q) 7 Represents the position information in the y-direction, qr 8 And qr (q) 9 Representing the position information in the x-direction.
Auxiliary bit information: qr (qr) 10 And qr (sum of qr) 11 Is a two-bit auxiliary qubit. Because the position bits are changed into the superposition state of all positions after passing through the H gate, the position information cannot be changed in the process of image preparation, and the position information needs to be transferred to the auxiliary quantum bits, so that the position information and the gray information are in one-to-one correspondence.
Next, the pixel 1110010101 is prepared by the quantum wire of fig. 7.
Step 1: a position information superposition state is generated. By quantum bits qr representing position information 6 And qr (sum of qr) 7 And adding an H gate to obtain the superposition state of the two position information.
Step 2: since the superimposed state representing the position information cannot be changed, preparation is made for one-to-one correspondence of the position information with the gradation information by transmitting the position information to the auxiliary qubit. For example, the position information qr 6 =1 and qr 7 Transfer of =0 to two constant auxiliary quantitiesOf the sub-bits, the sub-bit is made to control a sub-bit qr representing gradation information at the position of the two images 0101 0 -qr 2 ,qr 3 -qr 5 Let qr 0 -qr 2 ,qr 3 -qr 5 The outputs were 111, 001, respectively. The specific implementation is as follows:
through the first Toffoli gate, qr 6 The state of =0 is transferred to the auxiliary qubit qr 10 At this time qr 11 On-line application zeroing operation |0>Restoring the initial state to the value equal to qr 11 Is a multiplexing of (a); through the second Toffoli gate, qr 6 =0 and qr 7 The state of =1 is transferred together to the auxiliary qubit qr 11 At this time qr 10 On-line application zeroing operation |0>Restoring the initial state; through the third Toffoli gate, qr 6 ＝0、qr 7 =1 and qr 8 The state of =0 is transferred together to the auxiliary qubit qr 10 At this time qr 11 On-line application zeroing operation |0>Restoring the initial state; finally, the fourth Toffoli gate is used again, and at qr 10 Setting zero operation. Only qr 11 When 1, qr 6 ＝0、qr 7 ＝1、qr 8 =0 and qr 9 Only 1.
Step 3: and obtaining gray values corresponding to the positions. Will qr 11 As a control bit, the binary string representing the gradation value is made 1 where it is required to be 1, i.e., the functions implemented by the four latter CNOTs in fig. 7, by using the CNOT gate.
This completes the preparation of one pixel, after which the bottom two auxiliary qubits are zeroed using a zeroing operation so that multiplexing can be performed in the preparation of the next pixel.
It should be noted that any operation performed on the positional information requires a restoration, such as for qr in FIG. 7 6 And qr (q) 8 Must be restored with another non-operation.
It is emphasized that the transfer of position information can always be achieved by means of these two auxiliary qubits, whatever the number of qubits representing the position information, to one of the auxiliary qubits by means of the above-described repeated multiplexing method. Therefore, the number of auxiliary qubits does not increase with an increase in image size.
3. Based on two parallel quantum images and quantum multiplier, realizing multiplication of two quantum images
On the basis of completing preparation of two quantum images, the gray value at the same position of the two images is used as a multiplier and a multiplicand, and multiplication operation is carried out by using the multiplier. As shown in fig. 8, the multiplication between two numbers is extended to the multiplication between all pixels of the entire image. In the figure |b n-1 b n-2 ...b 0 >And |a n-1 a n-2 ...a 0 >Representing the gray information of the two quantum images at the corresponding positions. P k p k-1 ...p 0 >Representing the position information of the x-axis, in p k ～p 0 And (3) representing. I f k f k-1 ...f 0 >Representing the position information of the y-axis, f k ～f 0 And (3) representing. The gray information and the position information of the whole image are in an overlapped state and are generated through the preparation process of the step 2. In designing the image multiplication, in order to reduce the complexity of the quantum image, as few qubits as possible should be used. The two-bit auxiliary qubits used for preparing the two images are multiplexed by zero operation after the preparation process is completed, and can be used in the quantum multiplier circuit to represent the carry information |C of the n-bit quantum full adder i >And |C i-1 >Multiplexing is then achieved again by a zeroing operation. After the gray scale multiplication of a specific pixel point is completed, the quantum bit used for storing the result is also required to be subjected to zero setting operation to realize multiplexing. And (3) traversing all the pixel points by using the same method, so that multiplication of the two quantum images can be realized.
Two sizes of 2 are completed k ×2 k The gray scale range is [0,2 n -1]Is required to multiply the quantum images of (4n+2k+3) qubit digits, (8k+8n) 2 +6n+1)×2 k ×2 k Number of basic logic gates.
4. Simulation implementation of quantum image multiplication
The simulation implementation adopts a classical computer and a programmable quantum computer provided by an IBM platform, a quantum circuit is written by using python language according to environment management provided by an open source quantum computer toolkit Qiakit provided by an IBM laboratory and Anaconda, operation is realized according to the written circuit, quantum measurement is carried out, and finally a corresponding simulation result is output.
According to the basic information of the image, a quantum register, a classical register and various quantum bit gates are defined by referring to the quantum circuit design method, after the quantum circuit is added with various quantum bit gates, the quantum circuit is visualized, each quantum bit is measured, and the quantum gray image is output after collapsing. Experiments show that in order to ensure that complete quantum image information is measured and the measurement time is shortened, the number of times of measurement is about four times of the size of the quantum image.
The design method of the invention realizes feasibility and universality of quantum image multiplication, and can be applied to the algorithm operation size of 2 k ×2 k Quantum gray scale range is [0,2 n -1]Is used for multiplying the low-qubit images. Two 4 x 4 gray scale ranges [0,7 are completed]Is multiplied by the quantum image of (c), requiring 19-bit qubits. Two 16×16 gray scale ranges [0,7]Requiring 23-bit qubits within the limits of local simulation of 24 bits. Using an IBM laboratory 32-bit qubit cloud simulator, two gray scale ranges of 64 x 64 [0, 15 ] can be realized]Is multiplied by two quantum images of (c).
Quantum image multiplication is widely used in the fields of image enhancement, target extraction, and the like in quantum image processing. At f 4×4 Quantum image squaring and f 4×4 ×g 4×4 Feature extraction is two illustrative applications for designing quantum image multiplication. FIG. 9 (a) shows f 4×4 For the sake of easier visual understanding, fig. 9 (b) is an original image participating in the squaring operation, the gray information of which is shown in formula (3), and fig. 9 (c) is a visual view of the result obtained after the squaring operation. The contrast of the quantum image after the squaring is greatly improved.
Another application of quantum image multiplication is feature extraction, for example, as shown in fig. 10, in which, in order to extract the pixel values of the 2 nd row and the 2 nd column in fig. 10 (a), it can be realized by multiplying fig. 10 (a) with fig. 10 (b), wherein fig. 10 (a) as the multiplicand has gray information as shown in formula (3), fig. 10 (b) as the multiplier has gray information as shown in formula (4), and fig. 10 (d) is a probability histogram obtained by multiplying two 4×4 quantum images.
Quantum states appearing in the specificationOther similar representations are by analogy.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the claims of the present invention.
Claims (2)
1. A design method of quantum image multiplication operation and a simulation implementation method thereof are characterized in that: the method comprises the following steps:
step 1: designing a quantum multiplier by utilizing a quantum full adder and a right shift operation to realize the product of two n-bit binary numbers;
step 2: preparing two quantum images which share position information and are in an overlapped state based on a quantum image NEQR representation model;
the step 2 specifically comprises the following steps:
the two images share the position information, and a foundation is laid for the parallelism of the multiplication operation of the two subsequent quantum images;
the quantum image sharing position information is as follows:
for the preparation of a pixel at a certain position of two superimposed quantum images, the representation form of the pixel in the NEQR expression is expressed as a binary string, wherein the four latter bits represent position information, the first three bits represent gray information of the first quantum image at the position, and the fourth to sixth bits represent gray information of the second quantum image at the position;
the superposition state of the quantum images is as follows:
generating a position information superposition state: by adding an H gate on the quantum bit representing the position information, the superposition state of the two position information is obtained;
transmitting the position information to the auxiliary qubit;
obtaining gray values corresponding to the positions;
in the preparation process of the image gray information, position information is transmitted by using auxiliary bits, so that the position information corresponds to the gray information one by one, and auxiliary bits are multiplexed by using zero setting operation, so that only two constant auxiliary bits are needed in the whole preparation process of the image, the two constant auxiliary bits are not increased along with the increase of the image size, and the multiplexed auxiliary bits can be used as two auxiliary bits for representing carry information in a quantum multiplier, thereby realizing the improvement and optimization of the preparation process of the quantum image;
step 3: the quantum multiplier acts on the two prepared quantum images to realize multiplication of the two quantum images;
step 4: an experiment platform is built by adopting a classical computer and an open source quantum cloud simulator provided by an IBM laboratory, and simulation is carried out; using the open source quantum computing toolkit QISKIT provided by IBM company and the package management and environment management functions provided by Anaconda, simulating and realizing quantum image multiplication operation by Python language;
the quantum full adder is improved, a zero setting operation is used for multiplexing two-bit quantum bits representing carry information and one-bit quantum bits representing control bit information, so that auxiliary quantum bits are kept to be three bits all the time, the number of quantum bits used by the quantum adder is reduced, the improvement and optimization of the quantum adder are realized, and an improved quantum multiplier is designed by combining an implementation mode of a right shift operation function.
2. The method for designing and simulating the multiplication of the quantum image according to claim 1, wherein the method is characterized by comprising the following steps: the zeroing operation is to place the state of the qubit into the |0> state.
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