CN111786678B - Analog-to-digital converter based on thin film transistor, chip and control method - Google Patents
Analog-to-digital converter based on thin film transistor, chip and control method Download PDFInfo
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- CN111786678B CN111786678B CN202010504215.2A CN202010504215A CN111786678B CN 111786678 B CN111786678 B CN 111786678B CN 202010504215 A CN202010504215 A CN 202010504215A CN 111786678 B CN111786678 B CN 111786678B
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- H—ELECTRICITY
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- H03M1/12—Analogue/digital converters
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Abstract
The invention discloses an analog-to-digital converter, a chip and a control method based on a thin film transistor.A reference level module provides a reference voltage for a comparator module, a comparison unit compares the reference voltage with an analog signal input quantity to output a first comparison quantity, then a pseudo CMOS inverter unit processes the first comparison quantity to obtain a second comparison quantity, and a decoder module performs decoding processing to obtain an output digital quantity; the pseudo CMOS inverter unit is arranged to process the first comparison quantity, the pseudo CMOS inverter unit has a shaping characteristic on a waveform, the output swing amplitude and the direct current gain of the circuit are increased, and the improvement of the direct current gain enables the obtained second comparison quantity to be a value obtained after the first comparison quantity is further amplified, so that the integral resolution of the comparator module can be improved, and the differential nonlinear error and the integral nonlinear error of the analog-to-digital converter are reduced. The invention can be widely applied to the technical field of integrated circuits.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an analog-to-digital converter based on a thin film transistor, a chip and a control method.
Background
Analog-to-digital converters are important components of integrated circuits, and are used to convert analog signals into digital signals, and are widely used. The metal oxide thin film transistor (MO-TFT) has the advantages of low manufacturing cost, good light transmittance, large-area manufacturing, capability of being manufactured on a flexible substrate and the like. The analog-to-digital converter based on the MO-TFT has potential application prospect in the fields of temperature measurement of electronic thermometers, digital cameras, detection of humidity, light, sound in air, biological medical electrical signals and other analog signals. The existing phase inverter based on the MO-TFT analog-to-digital converter is usually designed based on the traditional diode load structure, resulting in poor dc gain, narrow output swing, and finally low resolution, low accuracy and poor performance of the analog-to-digital converter due to the lack of the p-type TFT.
Disclosure of Invention
In view of the above, in order to solve the above technical problems, an object of the present invention is to provide a thin film transistor-based analog-to-digital converter with high resolution, a chip and a control method.
The technical scheme adopted by the invention is as follows: a thin film transistor based analog to digital converter comprising: the device comprises a reference level module, a comparator module and a decoder module;
the reference level module is connected with the comparator module and is used for providing a plurality of reference voltages for the comparator module;
the comparator module comprises a plurality of comparators, each comparator inputs a reference voltage and an analog signal input quantity, each comparator comprises a comparison unit and a pseudo CMOS inverter unit, the comparison unit is used for comparing the reference voltage with the analog signal input quantity to output a first comparison quantity, and the pseudo CMOS inverter unit is connected with one end of the comparison unit, which outputs the first comparison quantity, and is used for processing the first comparison quantity to obtain a second comparison quantity;
the decoder module is connected with the comparator module and is used for decoding the second comparison quantity output by each comparator to obtain an output digital quantity.
Further, the comparison unit includes a first thin film transistor, a second thin film transistor, a first capacitor and a second capacitor, the analog signal input quantity is input to a first end of the second thin film transistor, a second end of the second thin film transistor is connected to a second end of the first thin film transistor, a first end of the first capacitor and a first end of the second capacitor, the reference voltage is input to the first end of the first thin film transistor, the second end of the first capacitor is grounded, the second end of the second capacitor is an end of the comparison unit outputting the first comparison quantity, and a third end of the first thin film transistor and a third end of the second thin film transistor are gates.
Further, the pseudo CMOS inverter unit includes an odd number of cascaded pseudo CMOS inverters, wherein an output end of the last stage of the pseudo CMOS inverter is connected to an input end of the first stage of the pseudo CMOS inverter through a third thin film transistor, and an input end of the first stage of the pseudo CMOS inverter is connected to one end of the comparison unit that outputs the first comparison quantity.
Furthermore, each pseudo CMOS phase inverter comprises a first field effect transistor, a second field effect transistor, a third field effect transistor and a fourth field effect transistor;
the third end of the first field effect transistor and the third end of the second field effect transistor are connected with one end of the comparison unit, which outputs the comparison quantity, the second end of the first field effect transistor and the second end of the second field effect transistor are grounded, the first end of the first field effect transistor is connected with the second end of the third field effect transistor, the third end of the third field effect transistor and the third end of the fourth field effect transistor, the first end of the second field effect transistor is connected with the second end of the fourth field effect transistor, and the first end of the third field effect transistor and the first end of the fourth field effect transistor are connected with a power supply;
the third end of the first field effect transistor, the third end of the second field effect transistor, the third end of the third field effect transistor and the third end of the fourth field effect transistor are grids; the input end of the pseudo CMOS phase inverter is the third end of the first field effect transistor, and the output end of the pseudo CMOS phase inverter is the first end of the second field effect transistor;
the first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor are thin film transistors.
Further, the pseudo CMOS inverter unit further includes a D flip-flop, an input end of the D flip-flop is connected to an output end of the last stage of pseudo CMOS inverter, and an output end of the D flip-flop is configured to output the second comparison quantity.
Further, the decoder module comprises a first gate structure, and the first gate structure comprises a first input end, a second input end, a third input end, a fourth input end, a first output end, a second output end, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor;
the first end of the fifth field effect transistor, the first end of the sixth field effect transistor and the first end of the seventh field effect transistor are connected with a power supply, the second end of the fifth field effect transistor is connected with the second end of the sixth field effect transistor, the first end of the ninth field effect transistor and the third end of the tenth field effect transistor, the second end of the ninth field effect transistor and the second end of the tenth field effect transistor are grounded, the second end of the seventh field effect transistor is connected with the first end of the eighth field effect transistor, and the second end of the eighth field effect transistor is connected with the third end of the ninth field effect transistor and the first end of the tenth field effect transistor;
the third end of the fifth field effect transistor, the third end of the sixth field effect transistor, the third end of the seventh field effect transistor, the third end of the eighth field effect transistor, the third end of the ninth field effect transistor and the third end of the tenth field effect transistor are all grids; the second end of the fifth field effect transistor is the first output end, the first end of the tenth field effect transistor is the second output end,
a third end of the fifth field effect transistor is the first input end, a third end of the seventh field effect transistor is the second input end, a third end of the sixth field effect transistor is the third input end, and a third end of the eighth field effect transistor is the fourth input end;
wherein the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, and the tenth field effect transistor are thin film transistors.
Further, the second comparison quantity includes a first digital quantity and a second digital quantity, the first digital quantity is the same as a level state of an output end of the last stage of the pseudo CMOS inverter, and the second digital quantity is opposite to a level state of the first digital quantity, wherein the first digital quantity of the D flip-flop of one of the pseudo CMOS inverter units is input to the first input end and the second digital quantity is input to the second input end, and the first digital quantity of the D flip-flop of the other one of the pseudo CMOS inverter units is input to the third input end and the second digital quantity is input to the fourth input end.
Further, the comparator module includes seven comparators, each comparator includes one D flip-flop, which is a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, the decoder module further includes a first digital quantity output terminal, a second digital quantity output terminal, a third digital quantity output terminal, and a second gate structure, a third gate structure, a fourth gate structure, a fifth gate structure, a sixth gate structure, a seventh gate structure, and an eighth gate structure that are all the same as the first gate structure, wherein the first digital quantity output terminal, the second digital quantity output terminal, and the third digital quantity output terminal are used for outputting the output digital quantity;
the first input end of the first gate structure inputs the first digital quantity of the seventh D flip-flop, the second input end of the first gate structure inputs the second digital quantity of the seventh D flip-flop, the third input end of the first gate structure inputs the second digital quantity of the sixth D flip-flop, the fourth input end of the first gate structure inputs the first digital quantity of the sixth D flip-flop, the first output end of the first gate structure is connected with the second input end of the fifth gate structure, and the second output end of the first gate structure is connected with the first input end of the fifth gate structure;
the first input end of the second gate structure inputs the first digital quantity of the fifth D flip-flop, the second input end of the second gate structure inputs the second digital quantity of the fifth D flip-flop, the third input end of the second gate structure inputs the second digital quantity of the fourth D flip-flop, the fourth input end of the second gate structure inputs the first digital quantity of the fourth D flip-flop, the first output end of the second gate structure is connected with the fourth input end of the fifth gate structure, and the second output end of the second gate structure is connected with the third input end of the fifth gate structure;
the first input end of the third gate structure inputs the first digital quantity of the third D flip-flop, the second input end of the third gate structure inputs the second digital quantity of the third D flip-flop, the third input end of the third gate structure inputs the second digital quantity of the second D flip-flop, the fourth input end of the third gate structure inputs the first digital quantity of the second D flip-flop, the first output end of the third gate structure is connected with the second input end of the sixth gate structure, and the second output end of the third gate structure is connected with the first input end of the sixth gate structure;
a first input end of the fourth gate structure inputs the first digital quantity of the sixth D flip-flop, a second input end of the fourth gate structure inputs the second digital quantity of the sixth D flip-flop, a third input end of the fourth gate structure inputs the second digital quantity of the fourth D flip-flop, a fourth input end of the fourth gate structure inputs the first digital quantity of the fourth D flip-flop, a first output end of the fourth gate structure is connected with a second input end of the seventh gate structure, and a second output end of the fourth gate structure is connected with a first input end of the seventh gate structure;
a first output end of the fifth gate structure is connected with a first input end of the eighth gate structure, and a second output end of the fifth gate structure is connected with a second input end of the eighth gate structure;
a third input end of the sixth gate structure inputs the second digital quantity of the first D flip-flop, a fourth input end of the sixth gate structure inputs the first digital quantity of the first D flip-flop, a first output end of the sixth gate structure is connected to a third input end of the eighth gate structure, and a second output end of the sixth gate structure is connected to a fourth input end of the eighth gate structure;
a third input end of the seventh gate structure inputs the second digital quantity of the second D flip-flop, a fourth input end of the seventh gate structure inputs the first digital quantity of the second D flip-flop, and a first output end of the seventh gate structure is the second digital quantity output end; the first output end of the eighth gate structure is the first digital quantity output end;
and the third digital quantity output end outputs the second digital quantity of the fourth D trigger.
The invention also provides a chip comprising the analog-to-digital converter.
The invention also provides a control method, which is applied to the analog-to-digital converter, wherein the comparison unit comprises a first thin film transistor, a second thin film transistor, a first capacitor and a second capacitor, the first end of the second thin film transistor inputs the analog signal input quantity, the second end of the second thin film transistor is connected with the second end of the first thin film transistor, the first end of the first capacitor and the first end of the second capacitor, the first end of the first thin film transistor inputs the reference voltage, the second end of the first capacitor is grounded, the second end of the second capacitor is the end of the comparison unit outputting the first comparison quantity, and the third end of the first thin film transistor and the third end of the second thin film transistor are grids; the pseudo CMOS phase inverter unit comprises an odd number of cascaded pseudo CMOS phase inverters, wherein the output end of the last-stage pseudo CMOS phase inverter is connected with the input end of the first-stage pseudo CMOS phase inverter through a third thin film transistor, and the input end of the first-stage pseudo CMOS phase inverter is connected with one end of the comparison unit, which outputs the first comparison quantity;
the control method, in particular, comprises the following control steps for each of the comparators:
controlling the first thin film transistor and the third thin film transistor to be conducted, controlling the second thin film transistor to be turned off, and sampling the reference voltage;
controlling the first thin film transistor and the third thin film transistor to be turned off, controlling the second thin film transistor to be turned on so as to input the analog signal input quantity and the reference voltage for comparison processing, and obtaining the first comparison quantity through the second capacitor;
and processing the first comparison quantity through the pseudo CMOS inverter unit, and outputting the second comparison quantity so that the decoder module obtains the output digital quantity according to the second comparison quantity.
The invention has the beneficial effects that: the reference level module provides a plurality of reference voltages for the comparator module, the comparison unit compares the reference voltages with the analog signal input quantity to output a first comparison quantity, then the pseudo CMOS inverter unit processes the first comparison quantity to obtain a second comparison quantity, and the decoder module decodes the second comparison quantity output by each comparator to obtain an output digital quantity; the pseudo CMOS inverter unit is arranged to process the first comparison quantity, the pseudo CMOS inverter unit has a shaping characteristic on a waveform, the output swing amplitude and the direct current gain of the circuit are increased, the direct current gain is improved, the obtained second comparison quantity is a value obtained by further amplifying the first comparison quantity, the minimum voltage which can be identified by the comparator module is reduced, the integral resolution of the comparator module is improved, the differential non-linear error (DNL) and the integral non-linear error (INL) of the analog-to-digital converter are reduced, and the performance of the analog-to-digital converter is improved.
Drawings
FIG. 1 is a schematic diagram of an analog-to-digital converter according to the present invention;
FIG. 2 is a schematic diagram of a comparator module according to the present invention;
FIG. 3 is a schematic diagram of a pseudo CMOS inverter cell;
FIG. 4 is a schematic structural view of a door structure;
fig. 5 is a schematic structural diagram of a decoder module.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
As shown in fig. 1, the present embodiment provides an analog-to-digital converter, including: a reference level module 10, a comparator module 20 and a decoder module 30;
the reference level module 10 is connected to the comparator module 20, and is configured to provide a plurality of reference voltages for the comparator module 20;
the comparator module 20 includes a plurality of comparators, each of which inputs a reference voltage and an analog signal input quantity, each of which includes a comparison unit for comparing the reference voltage with the analog signal input quantity V and a pseudo CMOS inverter unitinThe pseudo CMOS inverter unit is connected with one end of the comparison unit for outputting the first comparison quantityProcessing to obtain a second comparison quantity;
the decoder module 30 is connected to the comparator module 20, and is configured to decode the second comparison quantity output by each comparator to obtain an output digital quantity.
Wherein the reference level module comprises 2nA series resistor R for providing a reference level V by dividing voltageREFZ(Z＝2n-1) the comparator module comprises 2n-1 comparators, one reference level corresponding to one input of one comparator, the other input of the comparator being for inputting the analog signal input quantity. The decoder module is used for outputting n-bit output digital quantity, wherein n is a freely selectable positive integer. For example, when n is 3, the decoder block outputs three bits of output digital values, OUT1, OUT2, and OUT3, respectively.
In the present embodiment, the dummy CMOS means that the output transistors are each controlled by its preceding stage transistor, enabling the two transistors of the output to reach a complementary cut-off structure similar to a Complementary Metal Oxide Semiconductor (CMOS).
As shown in fig. 2, in the present embodiment, the comparing unit includes a first thin film transistor T1, a second thin film transistor T2, a first capacitor C1 and a second capacitor C2, a first end of the second thin film transistor T2 inputs an analog signal input quantity, a second end (a) of the second thin film transistor T2 is connected to a second end of the first thin film transistor T1, a first end of the first capacitor C1 and a first end of the second capacitor C2, a first end of the first thin film transistor T1 inputs a reference voltage, a second end of the first capacitor C1 is grounded, a second end (B) of the second capacitor C2 is an end of the comparing unit outputting the first comparison quantity, and a third end of the first thin film transistor T1 and a third end of the second thin film transistor T2 are gates. In the present embodiment, the thin film transistors used are all n-type metal oxide thin film transistors (MO-TFTs), and the field effect transistors concerned are optionally all thin film transistors.
As shown in fig. 2 and fig. 3, in the present embodiment, the dummy CMOS inverter unit includes three cascaded dummy CMOS inverters, specifically, a first dummy CMOS inverter 21, a second dummy CMOS inverter 22, and a third dummy CMOS inverter 23, and in other embodiments, an odd number of cascaded dummy CMOS inverters other than three may be included, where an output terminal of the last dummy CMOS inverter is connected to an input terminal of the first dummy CMOS inverter through a third thin film transistor, and an input terminal of the first dummy CMOS inverter is connected to one terminal (B) of the comparison unit, which outputs the first comparison quantity.
As shown in fig. 3, wherein each pseudo CMOS inverter includes a first fet Q1, a second fet Q2, a third fet Q3, and a fourth fet Q4;
the third end of the first field effect transistor Q1 and the third end of the second field effect transistor Q2 are connected with one end of the comparison unit, which outputs the comparison quantity, the second end of the first field effect transistor Q1 and the second end of the second field effect transistor Q2 are grounded, the first end of the first field effect transistor Q1 is connected with the second end of the third field effect transistor Q3, the third end of the third field effect transistor Q3 and the third end of the fourth field effect transistor Q4, the first end of the second field effect transistor Q2 is connected with the second end of the fourth field effect transistor Q4, and the first end of the third field effect transistor Q3 and the first end of the fourth field effect transistor Q4 are connected with a power supply;
the third end of the first field effect transistor Q1, the third end of the second field effect transistor Q2, the third end of the third field effect transistor Q3 and the third end of the fourth field effect transistor Q4 are both gates; the input end of the pseudo CMOS inverter is the third end of the first field effect transistor Q1, and the output end of the pseudo CMOS inverter is the first end of the second field effect transistor Q2.
In the present embodiment, the cascade connection means that the first terminal of the second fet Q2 of the previous stage is connected to the third terminal of the first fet Q1 and the third terminal of the second fet Q2 of the dummy CMOS inverter of the next stage. The output end of the last stage of the pseudo CMOS inverter is connected to the input end of the first stage of the pseudo CMOS inverter through a third thin film transistor, which means that the third end of the first field effect transistor Q1 of the first stage and the first end of the second field effect transistor Q2 of the last stage are connected through a third thin film transistor.
In this embodiment, the pseudo CMOS inverters are cascaded, the output swing of the circuit can be increased by utilizing the characteristic that the inverters have a shaping effect on waveforms, and the overall dc gain of the cascaded pseudo CMOS inverter unit is equal to the product of the dc gains of the three inverters, so as to realize high dc gain and wide output swing of the pseudo CMOS inverter. The improvement of the DC gain of the pseudo CMOS inverter can further amplify the difference between the input voltage of the comparator and the reference voltage, namely, the minimum voltage which can be identified by the comparator is reduced, and the integral resolution of the comparator module is improved, so that the differential nonlinear error (DNL) and the integral nonlinear error (INL) of the analog-to-digital converter are reduced.
As shown in fig. 2, in the present embodiment, the dummy CMOS inverter units further include D flip-flops, that is, each dummy CMOS inverter unit includes a D flip-flop, so that the comparator module has D flip-flop Dx(x＝1，2，……2n-1), the input end of the D flip-flop is connected with the output end (C) of the pseudo CMOS inverter of the last stage, and the output end of the D flip-flop is used for outputting the second comparison quantity. In this embodiment, the second comparison quantity includes a first digital quantity Qx and a second digital quantity-Qx (x is 1, 2, … … 2)n-1), the first digital quantity is the same as the output end level state of the pseudo CMOS inverter of the last stage, and the second digital quantity is opposite to the level state of the first digital quantity, namely the output end level state of the pseudo CMOS inverter of the last stage is high level, then the first digital quantity is high level, and the second digital quantity is low level.
By setting D flip-flop DxThe output signal of the pseudo CMOS inverter unit can be well shaped, so that two output states that the high level approaches to 1 and the low level approaches to 0 can be obtained, the output waveform of the pseudo CMOS inverter unit is shaped, the output swing is increased, and the signal burr is eliminated.
As shown in fig. 4, in this embodiment, the decoder module includes a plurality of gate structures with the same structure, for example, a structure that may be a nor gate, where the gate structures include a first input terminal (Ey), a second input terminal (-Ey), a third input terminal (Fy), a fourth input terminal (-Fy), a first output terminal (Ey + Fy), a second output terminal- (Ey + Fy), a fifth field effect transistor Q5, a sixth field effect transistor Q6, a seventh field effect transistor Q7, an eighth field effect transistor Q8, a ninth field effect transistor Q9, and a tenth field effect transistor Q10, where y is a selectable positive integer, and in this embodiment, y has a value range of [1, 8 ].
A pair of inverted output signals can be obtained by providing a gate structure having a differential structure, so that the number of inverter circuits in the decoder block can be reduced, and the power consumption of the entire circuit can be reduced.
Specifically, the first end of the fifth fet Q5, the first end of the sixth fet Q6, and the first end of the seventh fet Q7 are connected to the power supply, the second end of the fifth fet Q5 is connected to the second end of the sixth fet Q6, the first end of the ninth fet Q9, and the third end of the tenth fet Q10, the second end of the ninth fet Q9 and the second end of the tenth fet Q10 are grounded, the second end of the seventh fet Q7 is connected to the first end of the eighth fet Q8, and the second end of the eighth fet Q8 is connected to the third end of the ninth fet Q9 and the first end of the tenth fet Q10;
the third end of the fifth field-effect transistor Q5, the third end of the sixth field-effect transistor Q6, the third end of the seventh field-effect transistor Q7, the third end of the eighth field-effect transistor Q8, the third end of the ninth field-effect transistor Q9 and the third end of the tenth field-effect transistor Q10 are both gates; the second terminal of the fifth fet Q5 is a first output terminal, the first terminal of the tenth fet Q10 is a second output terminal, the third terminal of the fifth fet Q5 is a first input terminal, the third terminal of the seventh fet Q7 is a second input terminal, the third terminal of the sixth fet Q6 is a third input terminal, and the third terminal of the eighth fet Q8 is a fourth input terminal.
In the following, n is equal to 3 for example, that is, the reference level module includes 8 resistors R connected in series to provide 7 reference levels, and the comparator module includes 7 comparators, one reference level is correspondingly input to an input terminal of one comparator, and the other input terminal of the comparator is used for inputting an analog signal input quantity. The decoder module is used for outputting 3-bit output digital quantity. x is [1, 7], and different values of x represent the outputs of different comparators; and y is equal to [1, 8], and different values of y represent input and output of different gate structures.
As shown in fig. 5, the decoder module of the analog-to-digital converter of this embodiment includes a first digital output terminal, a second digital output terminal, a third digital output terminal, and a plurality of gate structures, where the gate structures have the same structure, and include a first gate structure U1, a second gate structure U2, a third gate structure U3, a fourth gate structure U4, a fifth gate structure U5, a sixth gate structure U6, a seventh gate structure U7, an eighth gate structure U8, and a first digital output terminal, a second digital output terminal, and a third digital output terminal, and are configured to output three bits of output digital quantities (OUT1, OUT2, OUT3) from low bits to high bits.
As shown in fig. 5, the comparator module of the analog-to-digital converter of the present embodiment includes seven comparators, each of which includes a comparison unit and a pseudo CMOS inverter unit (including a D flip-flop), where the D flip-flops are a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, and a seventh D flip-flop, respectively;
the first digital quantity of the seventh D trigger is input to the first input end of the first gate structure, the second digital quantity of the seventh D trigger is input to the second input end of the first gate structure, the second digital quantity of the sixth D trigger is input to the third input end of the first gate structure, the first digital quantity of the sixth D trigger is input to the fourth input end of the first gate structure, the first output end of the first gate structure is connected with the second input end of the fifth gate structure, and the second output end of the first gate structure is connected with the first input end of the fifth gate structure;
a first digital quantity of a fifth D trigger is input to a first input end of the second gate structure, a second digital quantity of the fifth D trigger is input to a second input end of the second gate structure, a second digital quantity of a fourth D trigger is input to a third input end of the second gate structure, a first digital quantity of a fourth D trigger is input to a fourth input end of the second gate structure, a first output end of the second gate structure is connected with a fourth input end of the fifth gate structure, and a second output end of the second gate structure is connected with a third input end of the fifth gate structure; a first digital quantity of a third D trigger is input to a first input end of a third gate structure, a second digital quantity of the third D trigger is input to a second input end of the third gate structure, a second digital quantity of the second D trigger is input to a third input end of the third gate structure, a first digital quantity of the second D trigger is input to a fourth input end of the third gate structure, a first output end of the third gate structure is connected with a second input end of a sixth gate structure, and a second output end of the third gate structure is connected with a first input end of the sixth gate structure;
a first digital quantity of a sixth D trigger is input to a first input end of a fourth gate structure, a second digital quantity of the sixth D trigger is input to a second input end of the fourth gate structure, a second digital quantity of the fourth D trigger is input to a third input end of the fourth gate structure, a first digital quantity of the fourth D trigger is input to a fourth input end of the fourth gate structure, a first output end of the fourth gate structure is connected with a second input end of the seventh gate structure, and a second output end of the fourth gate structure is connected with a first input end of the seventh gate structure;
a first output end of the fifth gate structure is connected with a first input end of the eighth gate structure, and a second output end of the fifth gate structure is connected with a second input end of the eighth gate structure;
a third input end of the sixth gate structure inputs the second digital quantity of the first D trigger, a fourth input end of the sixth gate structure inputs the first digital quantity of the first D trigger, a first output end of the sixth gate structure is connected with a third input end of the eighth gate structure, and a second output end of the sixth gate structure is connected with a fourth input end of the eighth gate structure;
a third input end of the seventh gate structure inputs the second digital quantity of the second D trigger, a fourth input end of the seventh gate structure inputs the first digital quantity of the second D trigger, and a first output end of the seventh gate structure is a second digital quantity output end; the first output end of the eighth gate structure is a first digital quantity output end;
the first output end of the eighth gate structure is a first digital quantity output end;
the third digital output terminal outputs the second digital quantity of the fourth D flip-flop, wherein the second digital quantity of the fourth D flip-flop can be obtained by processing two not gate structures U9 arranged in series in the decoder module, or can be obtained by directly outputting the second digital quantity of the fourth D flip-flop.
In the present embodiment, the third terminal of the first thin film transistor T1 and the third terminal of the third thin film transistor receive the same clock signal CLK, and the third terminal of the second thin film transistor T2 and the triggering of the D flip-flop pass the clock signal-CLK opposite to the clock signal CLK.
The embodiment also provides a control method:
a sampling stage: controlling the first thin film transistor T1 and the third thin film transistor T3 to be turned on, and controlling the second thin film transistor T2 to be turned off, and sampling the reference voltage, wherein V isA＝VREFZ，VB＝VC(VA、VB、VCDivided into voltages of point a, point B, and point C), and because point B and point C are the input node and the output node of the inverter module (i.e., the pseudo CMOS inverter unit), respectively, i.e., the potentials of the two are reversed, point B and point C satisfy both equality and reversal, i.e., there is VB＝VC＝1/2VDDThe first field effect transistor Q1 and the second field effect transistor Q2 are in a semi-conducting state, namely in a transition state between high and low levels of an inverter, and a node a1、a2、a3、a4、a5Is in the middle level state between the high level and the low level of the inverter, and is about 5V (V of the embodiment)DD10V).
A comparison stage: the first thin film transistor T1 and the third thin film transistor T3 are controlled to be turned off, and the second thin film transistor T2 is controlled to be turned on to input the analog signal input amount VINAnd a reference voltage VREFZThe comparison process is carried out, and the effect that the voltage at the two ends of the second capacitor C2 can not change suddenly is utilized (for example, when the reference voltage is 1.25V, the input quantity of the analog signal is 2V, and V is the time when V isAIncreasing from 1.25V to 2V, due to the coupling effect of the second capacitor C2, the voltage at point B will also have an increment of the same size (0.75V), i.e. the first comparison quantity, which goes through the step-by-step inversion of odd number of pseudo CMOS inverters (three in this embodiment, and other embodiments may be other numbers), point C gets a low level, and then Qx output by D flip-flop is low level, -Qx is high level, and if (when the reference voltage is 2.5V, the analog signal input is 2V, then V is at this momentAReduced from 2.5V to 2V, and the point B is electrically connected due to the coupling effect of the second capacitor C2The voltage is reduced by 0.5V with the same magnitude, after the variation quantity is subjected to the step-by-step reversal by three pseudo CMOS inverters, a comparison result of a high level state is obtained at a point C, and then Qx output by the D trigger is high-Qx is low).
Q1-Q7, -Q1- (-Q7) are respectively input into the gate structure, so that the decoder module outputs digital quantity. In particular, with VINFor example, 2V means 1.25V, 2.5V, 3.75V, 5V, 6.25V, 7.5V, and 8.75V. The outputs of the first to seventh D flip-flops at this time: Q1-Q6 ═ 1, -Q1 — (-Q6) ═ 0, Q7 ═ 0, -Q7 ═ 1, the output of each gate structure: e1+ F1 is 0, - (E1+ F1) 1, E2+ F2 is 1, - (E2+ F2) 0, E3+ F3 is 1, - (E3+ F3) 0, E4+ F4 is 1, - (E4+ F4) 0, E5+ F5 is 1, - (E5+ F5) 0, (E6+ F6) 0, - (E6+ F6) 1, E7+ F7 is 0, - (E7+ F7) 1, E8+ F8 is 1, - (E8+ F8) 0. Finally, the output digital quantity '001' is obtained. Other VINThe input principle of (2) is similar and will not be described again.
The maximum sampling rate that the analog-to-digital converter (ADC) of this embodiment can achieve is 4Ks/s, and it can be seen from table 1 that the DNL of this ADC is maximum-0.37624 LSB, and the maximum INL is 0.3196LSB, which has very small differential nonlinear error (DNL) and integral nonlinear error (INL), indicating that the analog-to-digital converter of this embodiment has good performance.
Table 1-8 states corresponding input analog signal range and DNL and INL data
| OUT | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 |
| VIN(V) | 0-1.2069 | 1.2069-2.4 | 2.4-3.848 | 3.848-5.3995 | 5.3995-6.1792 | 6.1792-7.6238 | 7.6238-8.8052 | 8.8052-10 |
| DNL(LSB) | -0.03448 | -0.04552 | 0.1584 | 0.2412 | -0.37624 | 0.15568 | -0.05488 | -0.04416 |
| INL(LSB) | -0.03448 | -0.08 | 0.0784 | 0.3196 | -0.05664 | 0.09904 | 0.04416 | 0 |
The embodiment also provides a chip comprising the analog-to-digital converter.
In some alternative embodiments, the embodiments presented and described in the context of the steps of the present invention are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of larger operations are performed independently.
Furthermore, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and/or features may be integrated in a single physical device and/or software module, or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary for an understanding of the present invention. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be understood within the ordinary skill of an engineer, given the nature, function, and internal relationship of the modules. Accordingly, those skilled in the art can, using ordinary skill, practice the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative of and not intended to limit the scope of the invention, which is defined by the appended claims and their full scope of equivalents.
Claims (5)
1. A thin film transistor based analog to digital converter, comprising: the device comprises a reference level module, a comparator module and a decoder module;
the reference level module is connected with the comparator module and is used for providing a plurality of reference voltages for the comparator module;
the comparator module comprises a plurality of comparators, each comparator inputs a reference voltage and an analog signal input quantity, each comparator comprises a comparison unit and a pseudo CMOS inverter unit, the comparison unit is used for comparing the reference voltage with the analog signal input quantity to output a first comparison quantity, and the pseudo CMOS inverter unit is connected with one end of the comparison unit, which outputs the first comparison quantity, and is used for processing the first comparison quantity to obtain a second comparison quantity;
the decoder module is connected with the comparator module and is used for decoding the second comparison quantity output by each comparator to obtain an output digital quantity;
the pseudo CMOS phase inverter unit comprises an odd number of cascaded pseudo CMOS phase inverters, wherein the output end of the last-stage pseudo CMOS phase inverter is connected with the input end of the first-stage pseudo CMOS phase inverter through a third thin film transistor, and the input end of the first-stage pseudo CMOS phase inverter is connected with one end of the comparison unit, which outputs the first comparison quantity;
the pseudo CMOS phase inverter unit further comprises a D trigger, the input end of the D trigger is connected with the output end of the last stage of pseudo CMOS phase inverter, and the output end of the D trigger is used for outputting the second comparison quantity;
the decoder module comprises a first gate structure, wherein the first gate structure comprises a first input end, a second input end, a third input end, a fourth input end, a first output end, a second output end, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor;
the first end of the fifth field effect transistor, the first end of the sixth field effect transistor and the first end of the seventh field effect transistor are connected with a power supply, the second end of the fifth field effect transistor is connected with the second end of the sixth field effect transistor, the first end of the ninth field effect transistor and the third end of the tenth field effect transistor, the second end of the ninth field effect transistor and the second end of the tenth field effect transistor are grounded, the second end of the seventh field effect transistor is connected with the first end of the eighth field effect transistor, and the second end of the eighth field effect transistor is connected with the third end of the ninth field effect transistor and the first end of the tenth field effect transistor;
the third end of the fifth field effect transistor, the third end of the sixth field effect transistor, the third end of the seventh field effect transistor, the third end of the eighth field effect transistor, the third end of the ninth field effect transistor and the third end of the tenth field effect transistor are all grids; the second end of the fifth field effect transistor is the first output end, and the first end of the tenth field effect transistor is the second output end;
a third end of the fifth field effect transistor is the first input end, a third end of the seventh field effect transistor is the second input end, a third end of the sixth field effect transistor is the third input end, and a third end of the eighth field effect transistor is the fourth input end; wherein the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor and the tenth field effect transistor are thin film transistors;
the second comparison quantity comprises a first digital quantity and a second digital quantity, the first digital quantity is the same as the level state of the output end of the pseudo CMOS inverter of the last stage, and the second digital quantity is opposite to the level state of the first digital quantity, wherein the first digital quantity of the D flip-flop of one pseudo CMOS inverter unit is input into the first input end and the second digital quantity is input into the second input end, and the first digital quantity of the D flip-flop of the other pseudo CMOS inverter unit is input into the third input end and the second digital quantity is input into the fourth input end;
the decoder module further comprises a first digital quantity output end, a second digital quantity output end, a third gate structure, a fourth gate structure, a fifth gate structure, a sixth gate structure, a seventh gate structure and an eighth gate structure which are all the same as the first gate structure, wherein the first digital quantity output end, the second digital quantity output end and the third digital quantity output end are used for outputting the output digital quantity;
the first input end of the first gate structure inputs the first digital quantity of the seventh D flip-flop, the second input end of the first gate structure inputs the second digital quantity of the seventh D flip-flop, the third input end of the first gate structure inputs the second digital quantity of the sixth D flip-flop, the fourth input end of the first gate structure inputs the first digital quantity of the sixth D flip-flop, the first output end of the first gate structure is connected with the second input end of the fifth gate structure, and the second output end of the first gate structure is connected with the first input end of the fifth gate structure;
the first input end of the second gate structure inputs the first digital quantity of the fifth D flip-flop, the second input end of the second gate structure inputs the second digital quantity of the fifth D flip-flop, the third input end of the second gate structure inputs the second digital quantity of the fourth D flip-flop, the fourth input end of the second gate structure inputs the first digital quantity of the fourth D flip-flop, the first output end of the second gate structure is connected with the fourth input end of the fifth gate structure, and the second output end of the second gate structure is connected with the third input end of the fifth gate structure;
the first input end of the third gate structure inputs the first digital quantity of the third D flip-flop, the second input end of the third gate structure inputs the second digital quantity of the third D flip-flop, the third input end of the third gate structure inputs the second digital quantity of the second D flip-flop, the fourth input end of the third gate structure inputs the first digital quantity of the second D flip-flop, the first output end of the third gate structure is connected with the second input end of the sixth gate structure, and the second output end of the third gate structure is connected with the first input end of the sixth gate structure;
a first input end of the fourth gate structure inputs the first digital quantity of the sixth D flip-flop, a second input end of the fourth gate structure inputs the second digital quantity of the sixth D flip-flop, a third input end of the fourth gate structure inputs the second digital quantity of the fourth D flip-flop, a fourth input end of the fourth gate structure inputs the first digital quantity of the fourth D flip-flop, a first output end of the fourth gate structure is connected with a second input end of the seventh gate structure, and a second output end of the fourth gate structure is connected with a first input end of the seventh gate structure;
a first output end of the fifth gate structure is connected with a first input end of the eighth gate structure, and a second output end of the fifth gate structure is connected with a second input end of the eighth gate structure;
a third input end of the sixth gate structure inputs the second digital quantity of the first D flip-flop, a fourth input end of the sixth gate structure inputs the first digital quantity of the first D flip-flop, a first output end of the sixth gate structure is connected to a third input end of the eighth gate structure, and a second output end of the sixth gate structure is connected to a fourth input end of the eighth gate structure;
a third input end of the seventh gate structure inputs the second digital quantity of the second D flip-flop, a fourth input end of the seventh gate structure inputs the first digital quantity of the second D flip-flop, and a first output end of the seventh gate structure is the second digital quantity output end;
the first output end of the eighth gate structure is the first digital quantity output end;
and the third digital quantity output end outputs the second digital quantity of the fourth D trigger.
2. The analog-to-digital converter of claim 1, wherein: the comparison unit comprises a first thin film transistor, a second thin film transistor, a first capacitor and a second capacitor, wherein the analog signal input quantity is input into the first end of the second thin film transistor, the second end of the second thin film transistor is connected with the second end of the first thin film transistor, the first end of the first capacitor and the first end of the second capacitor, the reference voltage is input into the first end of the first thin film transistor, the second end of the first capacitor is grounded, the second end of the second capacitor is the end of the comparison unit, which outputs the first comparison quantity, and the third end of the first thin film transistor and the third end of the second thin film transistor are grids.
3. The analog-to-digital converter of claim 1, wherein: each pseudo CMOS phase inverter comprises a first field effect tube, a second field effect tube, a third field effect tube and a fourth field effect tube;
the third end of the first field effect transistor and the third end of the second field effect transistor are connected with one end of the comparison unit, which outputs the comparison quantity, the second end of the first field effect transistor and the second end of the second field effect transistor are grounded, the first end of the first field effect transistor is connected with the second end of the third field effect transistor, the third end of the third field effect transistor and the third end of the fourth field effect transistor, the first end of the second field effect transistor is connected with the second end of the fourth field effect transistor, and the first end of the third field effect transistor and the first end of the fourth field effect transistor are connected with a power supply;
the third end of the first field effect transistor, the third end of the second field effect transistor, the third end of the third field effect transistor and the third end of the fourth field effect transistor are grids; the input end of the pseudo CMOS phase inverter is the third end of the first field effect transistor, and the output end of the pseudo CMOS phase inverter is the first end of the second field effect transistor;
the first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor are thin film transistors.
4. A chip comprising an analog-to-digital converter according to any of claims 1 to 3.
5. A control method applied to the analog-to-digital converter according to claim 1, wherein the comparison unit includes a first thin film transistor, a second thin film transistor, a first capacitor, and a second capacitor, a first end of the second thin film transistor inputs the analog signal input quantity, a second end of the second thin film transistor is connected to a second end of the first thin film transistor, a first end of the first capacitor, and a first end of the second capacitor, the first end of the first thin film transistor inputs the reference voltage, a second end of the first capacitor is grounded, a second end of the second capacitor is an end of the comparison unit that outputs the first comparison quantity, and a third end of the first thin film transistor and a third end of the second thin film transistor are gates; the pseudo CMOS phase inverter unit comprises an odd number of cascaded pseudo CMOS phase inverters, wherein the output end of the last-stage pseudo CMOS phase inverter is connected with the input end of the first-stage pseudo CMOS phase inverter through a third thin film transistor, and the input end of the first-stage pseudo CMOS phase inverter is connected with one end of the comparison unit, which outputs the first comparison quantity;
the control method, in particular, comprises the following control steps for each of the comparators:
controlling the first thin film transistor and the third thin film transistor to be conducted, controlling the second thin film transistor to be turned off, and sampling the reference voltage;
controlling the first thin film transistor and the third thin film transistor to be turned off, controlling the second thin film transistor to be turned on so as to input the analog signal input quantity and the reference voltage for comparison processing, and obtaining the first comparison quantity through the second capacitor;
and processing the first comparison quantity through the pseudo CMOS inverter unit, and outputting the second comparison quantity so that the decoder module obtains the output digital quantity according to the second comparison quantity.
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