CN111679596A - Reconstruction method of satellite I/O board card and reconfigurable satellite I/O board card system - Google Patents
Reconstruction method of satellite I/O board card and reconfigurable satellite I/O board card system Download PDFInfo
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- CN111679596A CN111679596A CN202010338930.3A CN202010338930A CN111679596A CN 111679596 A CN111679596 A CN 111679596A CN 202010338930 A CN202010338930 A CN 202010338930A CN 111679596 A CN111679596 A CN 111679596A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
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Abstract
The invention discloses a reconstruction method of a satellite I/O board card and a reconfigurable satellite I/O board card system, wherein the method is suitable for the reconfigurable satellite I/O board card system, the system comprises a reconfigurable model layer, a reconfigurable logic layer and a general physical layer, and the method comprises the following steps: the reconfigurable model layer constructs an application model according to the received user request; the reconfigurable logic layer configures a corresponding configuration file and/or a corresponding drive file for the application model; and the physical layer runs the application model according to the configuration file and/or the driving file. The invention defines I/O by using the application model, a set of universal hardware platform can adapt to various application models, and the reuse rate of the hardware platform is improved. The application model can be subjected to simulation verification in a digital environment, and the design success rate is improved.
Description
Technical Field
The invention relates to the technical field of industrial control, in particular to a reconstruction method of a satellite I/O board card and a reconfigurable satellite I/O board card system.
Background
The I/O board card is a core component of the industrial control computer and is mainly used for realizing the external signal acquisition and signal output functions of the industrial control computer. The current industrial control computer needs to select different types of I/O boards aiming at different application targets, and the I/O boards are low in reusability, high in cost and high in system integration difficulty. Meanwhile, the scheme of the combined I/O board card in the industrial control computer cannot perform system virtual simulation verification, so that the system iteration time is long.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention provide a method for reconfiguring a satellite I/O board and a reconfigurable satellite I/O board system. The technical scheme is as follows:
in a first aspect, a method for reconfiguring a satellite I/O board is provided, where the method is applicable to a reconfigurable satellite I/O board system, the system includes a reconfigurable model layer, a reconfigurable logic layer, and a general physical layer, and the method includes:
the reconfigurable model layer constructs an application model according to the received user request;
the reconfigurable logic layer configures a corresponding configuration file and/or a corresponding drive file for the application model;
and the physical layer runs the application model according to the configuration file and/or the driving file.
In a second aspect, a reconfigurable satellite I/O board system is provided, including:
the reconfigurable model layer is used for constructing an application model according to the received user request;
the reconfigurable logic layer is used for configuring a corresponding configuration file and/or a corresponding drive file for the application model;
and the general physical layer is used for operating the application model according to the configuration file and/or the drive file.
Further, the reconfigurable model layer includes: the system comprises an application model IP, an application model simulation engine and an application model HDL code generator;
the reconfigurable logic layer includes: HDL code, HDL code synthesis tools, and reconfigurable configuration files;
the common physical layer includes: I/O boards and I/O conditioning circuitry.
Further, the I/O board body includes: PCIe bus, FPGA, FMC connector and FMC daughter card.
In a third aspect, a computer-readable storage medium stores at least one instruction, at least one program, a set of codes, or a set of instructions, which is loaded and executed by a processor to implement the method for reconstructing a satellite I/O board according to the first aspect.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the reconfigurable model layer constructs an application model according to a received user request; the reconfigurable logic layer configures corresponding configuration files and/or drive files for the application model; the physical layer runs the application model according to the configuration file and/or the driver file. The invention defines I/O by using the application model, a set of universal hardware platform can adapt to various application models, and the reuse rate of the hardware platform is improved. The application model can be subjected to simulation verification in a digital environment, and the design success rate is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic view of a scenario for reconfiguration of a satellite I/O board in an embodiment of the present invention;
FIG. 2 is a flowchart of a method for reconfiguring a satellite I/O board in an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a reconfigurable satellite I/O board card system in an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of an I/O board in a common physical layer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a reconstruction method of a satellite I/O board card. The method can be applied to a reconfigurable satellite I/O board card system. The reconfigurable satellite I/O board card system comprises a reconfigurable model layer, a reconfigurable logic layer and a general physical layer. The reconfigurable model layer can complete user algorithm and other service logics, and data is interacted with the universal physical layer through the reconfigurable logic layer; the reconfigurable logic layer is designed based on a bottom layer IP of an FPGA manufacturer and is used for a middle layer of the universal physical layer and the reconfigurable model layer, and the configuration file can be matched with the IP design of the reconfigurable logic layer to complete hardware constraint; the general physical layer is realized by hardware and mainly comprises Xilinx 7 series FPGA/ZYNQ chips, PCIe buses and FMC interfaces, and the final executable file runs on the FPGA/ZYNQ chips. The application scenario of the invention is as shown in fig. 1, the reconfigurable model layer constructs an application model, the reconfigurable logic layer completes the bottom layer design of the FPGA based on IP aiming at the application model, and configures the configuration file of the application model, and finally the physical layer runs the application model on the PC according to the configuration file.
The following describes a reconfiguration processing flow of the satellite I/O board shown in fig. 2 with reference to a specific implementation, where the reconfiguration processing flow may be as follows:
In implementation, the user selects an application to be used according to actual needs, and sends a user request for constructing the application model. After receiving the user request, the constructable model layer determines a corresponding application model according to the content of the user request and constructs the application model.
In implementation, after the application model is built, the reconfigurable logic layer completes the bottom layer design of the FPGA based on the IP according to the application model. The design completes PCIe bus driving in the FPGA, completes general setting of data interaction with an application layer, and reserves a general read-write address for a user through an AXI4 bus. The setting of an IP-based environment, the pin constraint of FPGA hardware and the like can be completed through the configuration file of Matlab.
In step 203, the physical layer runs the application model according to the configuration file and/or the driver file.
In the embodiment of the invention, the reconfigurable model layer constructs an application model according to a received user request; the reconfigurable logic layer configures corresponding configuration files and/or drive files for the application model; the physical layer runs the application model according to the configuration file and/or the driver file.
The invention adopts a visual model mode to quickly construct the satellite I/O board card system, and downloads the configured application model and the configuration file/drive file thereof into the FPGA through an automatic code generation and HDL code synthesis tool, thereby realizing the digital satellite I/O board card system with any combination. The I/O is defined by using the application model, a set of universal hardware platform can adapt to various application models, and the reuse rate of the hardware platform is improved. And each application model of the satellite I/O board card system built in the digital environment can be subjected to simulation verification, and HDL codes automatically generated by the simulated application model can be guaranteed to be completely consistent with simulation verification results in the digital environment after being downloaded to an FPGA on a hardware satellite I/O board card. The application model can be subjected to simulation verification in a digital environment, and the design success rate is improved.
Based on the same technical concept, an embodiment of the present invention further provides a reconfigurable satellite I/O board system, as shown in fig. 3, including:
and the reconfigurable model layer 301 is used for constructing an application model according to the received user request.
And the user can freely set up the required application model on the reconfigurable model layer according to the requirement. The operation of the data read-write buffer pool reserved by the reconfigurable logic layer 302 is matched with the reconfigurable model layer 301. And then integrating the application model into system engineering by using a Simulink design method based on IP, and further generating codes, simulating in-loop and capturing data.
The reconfigurable logic layer 302 is configured to configure a corresponding configuration file and/or a corresponding driver file for the application model.
The reconfigurable logic layer 302 can complete the bottom layer design of the FPGA based on IP, the design completes PCIe bus driving in the FPGA, completes the general setting of data interaction with an application layer, and reserves a general read-write address for a user through an AXI4 bus. The setting of an IP-based environment, the pin constraint of FPGA hardware and the like can be completed through the configuration file of Matlab.
And the universal physical layer 303 is used for running the application model according to the configuration file and/or the drive file.
The generic physical layer 303 can implement the hardware of the reconfigurable FPGA board.
Optionally, the reconfigurable model layer 201 includes: the system comprises an application model IP, an application model simulation engine and an application model HDL code generator;
the reconfigurable logic layer includes: HDL code, HDL code synthesis tools, and reconfigurable configuration files;
the common physical layer includes: I/O boards and I/O conditioning circuitry.
Optionally, as shown in fig. 4, in the above general physical layer, the I/O board body includes: PCIe bus 401, FPGA402, FMC connector 403, and FMC daughter card 404.
Based on the same technical concept, an embodiment of the present invention further provides a computer-readable storage medium, where at least one instruction, at least one program, a code set, or a set of instructions is stored in the storage medium, and the at least one instruction, the at least one program, the code set, or the set of instructions is loaded and executed by a processor to implement the above reconstruction method for a satellite I/O board.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute the method according to the embodiments or some parts of the embodiments.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A reconstruction method of a satellite I/O board is characterized in that the method is suitable for a reconfigurable satellite I/O board system, the system comprises a reconfigurable model layer, a reconfigurable logic layer and a general physical layer, and the method comprises the following steps:
the reconfigurable model layer constructs an application model according to the received user request;
the reconfigurable logic layer configures a corresponding configuration file and/or a corresponding drive file for the application model;
and the physical layer runs the application model according to the configuration file and/or the driving file.
2. A reconfigurable satellite I/O board card system, comprising:
the reconfigurable model layer is used for constructing an application model according to the received user request;
the reconfigurable logic layer is used for configuring a corresponding configuration file and/or a corresponding drive file for the application model;
and the general physical layer is used for operating the application model according to the configuration file and/or the drive file.
3. The system of claim 1,
the reconfigurable model layer includes: the system comprises an application model IP, an application model simulation engine and an application model HDL code generator;
the reconfigurable logic layer includes: HDL code, HDL code synthesis tools, and reconfigurable configuration files;
the common physical layer includes: I/O boards and I/O conditioning circuitry.
4. The system of claim 3, the I/O plate body comprising: PCIe bus, FPGA, FMC connector and FMC daughter card.
5. A computer readable storage medium having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions that is loaded and executed by a processor to implement the method of reconfiguration of a satellite I/O card of claim 1.
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| CN106292336A (en) * | 2016-10-10 | 2017-01-04 | 上海航天控制技术研究所 | The fault simulation system of Satellite attitude and orbit control system based on embedded VxWorks and method |
| CN110489376A (en) * | 2019-08-14 | 2019-11-22 | 上海卫星工程研究所 | The in-orbit reconstruct frame system of the whole star hardware of satellite and reconstructing method |
| US20190361821A1 (en) * | 2018-05-23 | 2019-11-28 | Samsung Electronics Co., Ltd. | Storage device including reconfigurable logic and method of operating the storage device |
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2020
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Patent Citations (6)
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| CN104777757A (en) * | 2014-01-15 | 2015-07-15 | 深圳航天东方红海特卫星有限公司 | Closed-loop simulation testing system and method for ground attitude control of microsatellites |
| CN104777758A (en) * | 2014-01-15 | 2015-07-15 | 深圳航天东方红海特卫星有限公司 | General purpose simulator for microsatellite equipment |
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Application publication date: 20200918 |